SN74HCT273NSR ,Octal D-Type Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT273PW ,Octal D-Type Flip-Flops With Clear SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 ..
SN74HCT273PWLE ,Octal D-Type Flip-Flops With Clear SCLS068E − NOVEMBER 1988 − REVISED AUGUST 2003 ..
SN74HCT273PWR ,Octal D-Type Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT273PWRG4 ,Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT273PWRG4 ,Octal D-Type Flip-Flops With Clear 20-TSSOP -40 to 85/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SNJ5402J ,Quadruple 2-Input Positive-NOR Gates
SNJ5402J ,Quadruple 2-Input Positive-NOR Gates
SNJ5404J ,Hex Inverters/sc/package.FUNCTION TABLE(each inverter)INPUT OUTPUTA YH LL H2POST OFFICE BOX 655303 • DALLAS, TEX ..
SNJ5405J , HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS
SNJ5405J , HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS
SNJ5406J ,Hex Inverter Buffers/Drivers With Open-Collector High-Voltage Outputs/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCT273DBLE-SN74HCT273DBR-SN74HCT273DW-SN74HCT273DWG4-SN74HCT273DWR-SN74HCT273DWRG4-SN74HCT273N-SN74HCT273NSR-SN74HCT273PW-SN74HCT273PWLE-SN74HCT273PWR-SN74HCT273PWRG4
Octal D-Type Flip-Flops With Clear
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max− Buffer/Storage Registers
− Shift Registers
− Pattern GeneratorsCLR
GND
VCC
CLK
SN54HCT273 ...J OR W PACKAGE
SN74HCT273... DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)1QCLR
GND
CLK
SN54HCT273... FK PACKAGE
(TOP VIEW)
description/ordering informationThese devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices
are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the positive-going pulse. When CLK is at either the high or low level, the D input has no effect
at the output. The circuits are designed to prevent false clocking by transitions at CLR.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.