SN74HCT377DW ,Octal D-Type Flip-Flops With Clock Enable SN54HCT377, SN74HCT377 OCTAL D-TYPE FLIP-FLOPSWITH CLOCK ENABLESCLS067D – NOVEMBER 1988 – REVISED ..
SN74HCT377DWR ,Octal D-Type Flip-Flops With Clock Enablemaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCT377DWRG4 , OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN74HCT377DWRG4 , OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN74HCT377N ,Octal D-Type Flip-Flops With Clock Enablemaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCT540DW ,Octal Buffers And Line Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SNJ54175J ,Quadruple D-type Flip-Flops With Clear 16-CDIP -55 to 125
SNJ5417J ,Hex Buffers/Drivers With Open-Collector High-Voltage OutputsFeatures...... 1• Changed R values for SN7404: D (SOIC) from 86 to 86.8, N (PDIP) from 80 to 52.1, ..
SNJ54180J ,9-Bit Odd/Even Parity Generators/Checkersmaximum ratings over operating f/eV-ai-r/mia/turi, rFroinhissirthervitiFrioied)Supply voltage, VCC ..
SNJ54191J , SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SNJ54191J , SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL
SNJ54196J , 50/30/100-MHZ PRESETTABLE DECADE OR BINARY COUNTERS/LATCHES
SN74HCT377DW-SN74HCT377DWR-SN74HCT377N
Octal D-Type Flip-Flops With Clock Enable
±4-mA Output Drive at 5 V
Low Input Current of 1 μA Max Inputs Are TTL-Voltage Compatible– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
description/ordering informationThese devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273
devices, but feature a latched clock-enable (CLKEN) input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or
low level, the D input has no effect at the output. These devices are designed to prevent false clocking by
transitions at CLKEN.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.