SN74HCT74PWLE ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset SCLS169E − DECEMBER 1 ..
SN74HCT74PWR ,Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Presetmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74HCU04 ,Hex Inverters SCLS079E − MARCH 1984 − REVISED MARCH 2004 Wide Operating Voltage ..
SN74HCU04D ,Hex Inverters/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN74HCU04DR ,Hex Invertersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74HCU04DRE4 ,Hex Inverters 14-SOIC -40 to 85 SCLS079E − MARCH 1984 − REVISED MARCH 2004 Wide Operating Voltage ..
SNJ54ABT16374AWD ,16-Bit Edge-Triggered D-type Flip-Flops With 3-State Outputs SN54ABT16374A, SN74ABT16374A 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTSSCBS205C – ..
SNJ54ABT16543WD ,16-Bit Registered Transceivers With 3-State Outputs SN54ABT16543, SN74ABT16543 16-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTSSCBS087C – FEBRUARY 1 ..
SNJ54ABT240J ,Octal Buffers/Drivers With 3-State Outputs SN54ABT240, SN74ABT240A OCTAL BUFFERS/DRIVERSWITH 3-STATE OUTPUTSSCBS098I – JANUARY 1991 – REVISED ..
SNJ54ABT240W ,Octal Buffers/Drivers With 3-State Outputsmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SNJ54ABT244FK ,Octal Buffers Drivers With 3-State Outputsmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SNJ54ABT244J ,Octal Buffers Drivers With 3-State Outputslogic diagram (positive logic)1 191OE 2OE218 11 91A1 1Y1 2A1 2Y1416 13 71A2 1Y2 2A2 2Y2614 15 51A3 ..
SN74HCT74D-SN74HCT74DR-SN74HCT74N-SN74HCT74NSR-SN74HCT74PW-SN74HCT74PWLE-SN74HCT74PWR
Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max Inputs Are TTL-Voltage Compatibledescription/ordering informationThe ’HCT74 devices contain two independent
D-type positive-edge-triggered flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the input may be changed without affecting the
levels at the outputs.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
1CLK
1PRE
GND
2CLK
2PRE
2CLK
2PRE
1CLK
1PRE1CLRNC2Q2CLR
GND
SN54HCT74... FK PACKAGE
(TOP VIEW)NC − No internal connection
