Dual CAN High-Speed Microprocessor# DS80C390QNR+ Technical Documentation
## 1. Application Scenarios
### Typical Use Cases
The DS80C390QNR+ is a dual-can high-speed microcontroller primarily employed in applications requiring robust network communication and real-time data processing. Key use cases include:
- Industrial Control Systems : Serves as the central processor in PLCs (Programmable Logic Controllers) managing multiple CAN bus networks for machine automation
- Automotive Networks : Functions as a gateway controller between various vehicle subsystems (engine control, braking systems, infotainment) using dual CAN 2.0B interfaces
- Medical Monitoring Equipment : Processes sensor data from multiple sources while maintaining reliable communication between diagnostic modules
- Building Automation : Coordinates environmental control systems (HVAC, lighting, security) through distributed CAN networks
### Industry Applications
Automotive Industry :
- Vehicle network gateways
- Advanced driver assistance systems (ADAS)
- Telematics control units
- Body control modules
Industrial Automation :
- Distributed control systems
- Motor control units
- Process monitoring equipment
- Robotics control interfaces
Medical Devices :
- Patient monitoring systems
- Diagnostic equipment controllers
- Laboratory automation
- Medical imaging peripherals
### Practical Advantages and Limitations
Advantages :
- Dual CAN 2.0B Controllers : Enables simultaneous operation on two independent CAN networks with 32 message objects each
- High-Speed Operation : 40 MHz maximum operating frequency with 4-clock machine cycle provides 10 MIPS performance
- Enhanced 8051 Architecture : Maintains code compatibility while offering improved performance through pipelined instruction execution
- Large Memory Addressing : Supports up to 4MB of external memory space
- Low Power Modes : Includes idle and power-down modes for energy-sensitive applications
- Industrial Temperature Range : -40°C to +85°C operation suitable for harsh environments
Limitations :
- Legacy Architecture : Based on 8051 core, which may limit performance compared to modern ARM-based microcontrollers
- Power Consumption : Higher than contemporary low-power microcontrollers in active mode
- Limited On-Chip Memory : Requires external memory for larger applications
- Development Tools : May require specialized tools compared to more common architectures
## 2. Design Considerations
### Common Design Pitfalls and Solutions
Power Supply Decoupling :
- Pitfall : Inadequate decoupling causing voltage droops during high-speed operation
- Solution : Implement 100nF ceramic capacitors at each VCC pin, plus bulk 10μF tantalum capacitors near power entry points
Clock Signal Integrity :
- Pitfall : Poor crystal oscillator layout leading to timing errors
- Solution : Keep crystal and load capacitors close to XTAL pins, use ground plane beneath oscillator circuit, and avoid routing other signals nearby
CAN Bus Termination :
- Pitfall : Missing or incorrect termination resistors causing signal reflections
- Solution : Include 120Ω termination resistors at both ends of each CAN bus, with proper calculation for stub lengths
### Compatibility Issues with Other Components
Memory Interface :
- SRAM Compatibility : Works with standard asynchronous SRAM, but timing must match processor's bus cycle
- Flash Memory : Requires wait states for slower flash devices; configure memory interface control registers accordingly
- Mixed Voltage Systems : 3.3V peripherals need level shifters when interfacing with 5V microcontroller
CAN Transceivers :
- Voltage Matching : Ensure CAN transceivers (e.g., MCP2551, TJA1050) match the microcontroller's I/O voltage levels
- Speed Compatibility : Verify transceiver supports the target CAN bus speed (up to 1Mbps)
Analog Peripherals :
- ADC Interface : External
