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Partno	Mfg	Dc	Qty	Available	Descript
74ALVC00BQ	PHILIPS	N/a	991	avai	Quad 2-input NAND gate

74ALVC00BQ ,Quad 2-input NAND gateFEATURES DESCRIPTION• Wide supply voltage range from 1.65 to 3.6 V The 74ALVC00 is a high-performan ..
74ALVC00D ,Quad 2-input NAND gateLogic diagram for one gate5. Pinning information5.1 Pinning terminal 1index area2 131B 4B1A 1 14 VC ..
74ALVC00MTCX ,Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and OutputsFeaturesThe ALVC00 contains four 2-input NAND gates. This prod-

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74ALVC00BQ
Quad 2-input NAND gate

Philips Semiconductors Product specification
Quad 2-input NAND gate 74ALVC00
FEATURES Wide supply voltage range from 1.65to 3.6V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7to 3.6V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standard:
JESD8-7 (1.65to 1.95V)
JESD8-5 (2.3to 2.7V)
JESD8B/JESD36 (2.7to 3.6 V). ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
DESCRIPTION
The 74ALVC00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
The 74ALVC00 provides the 2-input NAND function.
QUICK REFERENCE DATA
GND=0 V; Tamb =25 °C.
Notes CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in Volts;= total load switching outputs;
Σ(CL× VCC2×fo)= sum of the outputs. The condition is VI= GNDto VCC.
Philips Semiconductors Product specification
Quad 2-input NAND gate 74ALVC00
ORDERING INFORMATION
FUNCTION TABLE
See note1.
Note H= HIGH voltage level;= LOW voltage level.
PINNING
Philips Semiconductors Product specification
Quad 2-input NAND gate 74ALVC00
Philips Semiconductors Product specification
Quad 2-input NAND gate 74ALVC00
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referencedto GND (ground=0 V).
Notes The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC=0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
Philips Semiconductors Product specification
Quad 2-input NAND gate 74ALVC00 CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Note All typical values are measured at Tamb =25 °C.
Philips Semiconductors Product specification
Quad 2-input NAND gate 74ALVC00 CHARACTERISTICS
Note All typical values are measured at Tamb =25 °C. WAVEFORMS
Philips Semiconductors Product specification
Quad 2-input NAND gate 74ALVC00