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74ALVC74BQNXP/PHILIPSN/a3000avaiDual D-type flip-flop with set and reset; positive-edge trigger
74ALVC74BQNXPN/a1654avaiDual D-type flip-flop with set and reset; positive-edge trigger


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74ALVC74BQ
Dual D-type flip-flop with set and reset; positive-edge trigger

Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
FEATURES
Wide supply voltage range from 1.65to 3.6V Complies with JEDEC standard:
JESD8-7 (1.65to 1.95V)
JESD8-5 (2.3to 2.7V)
JESD8B/JESD36 (2.7to 3.6 V). 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7to 3.6V) Power-down mode Latch-up performance exceeds 250 mA ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
DESCRIPTION

The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q andQ outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
mustbe stable one set-up time priorto the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA

GND=0 V; Tamb =25 °C.
Notes
CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in Volts;= total load switching outputs;
Σ(CL× VCC2×fo)= sum of the outputs. The condition is VI= GNDto VCC.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
ORDERING INFORMATION
FUNCTION TABLES
Table 1
See note1
Table 2
See note1
Note
H= HIGH voltage level;= LOW voltage level;= don’t care;= LOW-to-HIGH CP transition;
Qn+1= state after the next LOW-to-HIGH transition of CP.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
PINNING
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referencedto GND (ground=0 V).
Notes
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC=0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74 CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Note
All typical values are measured at Tamb =25 °C.
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74 CHARACTERISTICS
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
Note
All typical values are measured at Tamb =25 °C. WAVEFORMS
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74ALVC74
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