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74LVC14APWNXPN/a30000avaiHex inverting Schmitt-trigger with 5V tolerant input


74LVC14APW ,Hex inverting Schmitt-trigger with 5V tolerant inputPin configuration SO14, SSOP14 and Fig 5.
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74LVC14APW
Hex inverting Schmitt trigger with 5 V tolerant input
1. General description
The 74LVC14A provides six inverting buffers with Schmitt trigger input. It is capable of
transforming slowly-changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device as a translator in mixed 3.3 V and 5 V applications.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6V5 V tolerant input for interfacing with 5 V logic CMOS low-power consumption Direct interface with TTL levels Unlimited input rise and fall times Inputs accept voltages up to 5.5 V Complies with JEDEC standard JESD8-C/JESD36 (2.7Vto 3.6V) ESD protection: HBM JESD22-A114F exceeds 2000V MM JESD22-A115-B exceeds 200V CDM JESD22-C101E exceeds 1000V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers for highly noisy environments Astable multivibrators Monostable multivibrators
74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input
Rev. 5 — 23 December 2011 Product data sheet
NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input
4. Ordering information

5. Functional diagram

Table 1. Ordering information

74LVC14AD 40 C to +125 C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LVC14ADB 40 C to +125 C SSOP14 plastic thin shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LVC14APW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LVC14ABQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads;14 terminals;
body 2.53 0.85 mm
SOT762-1
NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input
6. Pinning information
6.1 Pinning

6.2 Pin description

7. Functional description

[1] H= HIGH voltage level; L= LOW voltage level
Table 2. Pin description

1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 data input , 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 data output
GND 7 ground (0V)
VCC 14 supply voltage
Table 3. Function table[1]

NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input
8. Limiting values

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation.
[4] For SO14 packages: Ptot derates linearly with 8 mW/K above 70C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60C.
9. Recommended operating conditions

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground =0V).
VCC supply voltage 0.5 +6.5 V input voltage [1] 0.5 +6.5 V output voltage [2][3] 0.5 VCC + 0.5 V
IIK input clamping current VI < 0V 50 - mA
IOK output clamping current VO > VCC or VO < 0V - 50 mA output current VO = 0 V to VCC - 50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C [4] -500 mW
Table 5. Recommended operating conditions

VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V input voltage 0 - 5.5 V output voltage 0 - VCC V
Tamb ambient temperature 40 - +125 C
NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input
10. Static characteristics

[1] All typical values are measured at VCC=3.3 V (unless stated otherwise) and Tamb =25C.
11. Dynamic characteristics

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
VOH HIGH-level
output voltage =VT+or VT= 100 A;
VCC= 1.65Vto 3.6V
VCC 0.2 --VCC 0.3- V= 4mA; VCC = 1.65 V 1.2 - - 1.05 - V= 8mA; VCC = 2.3V 1.8 - - 1.65 - V= 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V= 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V= 24 mA; VCC = 3.0 V 2.2 --2.0 -V
VOL LOW-level
voltage output =VT+or VT= 100 A; VCC = 1.65 V to 3.6V - - 0.2 - 0.3 V =4 mA; VCC = 1.65 V - - 0.45 - 0.65 V =8 mA; VCC = 2.3V - - 0.6 - 0.8 V
IO = 12 mA; VCC = 2.7V - - 0.4 - 0.6 V
IO = 24 mA; VCC = 3.0V - - 0.55 - 0.8 V input leakage
current
VCC = 3.6 V; VI = 5.5 V or GND - 0.1 5- 20 A
ICC supply current VCC = 3.6 V; VI = VCC or GND; =0A
-0.1 10 - 40 A
ICC additional
supply current
per input pin; VCC = 2.7 V to 3.6V; =VCC  0.6 V; IO = 0A 5 500 - 5000 A input
capacitance
VCC= 0 V to 3.6 V; VI = GND to VCC - 4.0 -- -pF
Table 7. Dynamic characteristics

Voltages are referenced to GND (ground =0 V). For test circuit see Figure7.
tpd propagation delay nA to nY; see Figure6 [2]
VCC = 1.2 V - 16 - - - ns
VCC = 1.65 V to 1.95 V 1.0 6.1 12.7 1.0 14.7 ns
VCC = 2.3 V to 2.7V 1.5 3.5 7.8 1.5 10.0 ns
VCC = 2.7V 1.5 3.6 7.5 1.5 9.5 ns
VCC = 3.0 V to 3.6V 1.0 3.2 6.4 1.0 8.0 ns
tsk(o) output skew time VCC= 3.0 V to 3.6V [3] - - 1.0 - 1.5 ns
NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input

[1] Typical values are measured at Tamb =25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W). =CPD VCC2fi N+ (CL VCC2fo) where: = input frequency in MHz; fo= output frequency in MHz= output load capacitance inpF
VCC= supply voltage in Volts= number of inputs switching
(CL VCC2fo)= sum of the outputs.
12. Waveforms

CPD power dissipation
capacitance
per buffer; VI =GNDto VCC [4]
VCC = 1.65 V to 1.95 V - 9.0 - - - pF
VCC = 2.3 V to 2.7 V - 12.5 - - - pF
VCC = 3.0 V to 3.6 V - 15.6 - - - pF
Table 7. Dynamic characteristics …continued

Voltages are referenced to GND (ground =0 V). For test circuit see Figure7.
NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input

Table 8. Test data

1.2V VCC  2 ns 30pF 1 k
1.65Vto 1.95V VCC  2 ns 30pF 1 k
2.3Vto 2.7V VCC  2 ns 30pF 500
2.7 V 2.7V  2.5ns 50pF 500
3.0Vto 3.6V 2.7V  2.5ns 50pF 500
NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input
13. Transfer characteristics

[1] Typical transfer characteristic is displayed in Figure9.
Table 9. Transfer characteristics

Voltages are referenced to GND (ground = 0 V); see Figure8.
VT+ positive-going
threshold voltage
VCC = 1.2 V 0.2 1.0 0.2 1.0 V
VCC = 1.65V 0.4 1.3 0.4 1.3 V
VCC = 1.95V 0.6 1.5 0.6 1.5 V
VCC = 2.3V 0.8 1.7 0.8 1.7 V
VCC = 2.5V 0.9 1.7 0.9 1.7 V
VCC = 2.7V 1.1 2 1.1 2 V
VCC = 3V 1.2 2 1.2 2 V
VCC = 3.6V 1.2 2 1.2 2 V
VT negative-going
threshold voltage
VCC = 1.2 V 0.12 0.75 0.12 0.75 V
VCC = 1.65 V 0.15 0.85 0.15 0.85 V
VCC = 1.95V 0.25 0.95 0.25 0.95 V
VCC = 2.3V 0.4 1.1 0.4 1.1 V
VCC = 2.5V 0.4 1.2 0.4 1.2 V
VCC = 2.7V 0.8 1.4 0.8 1.4 V
VCC = 3V 0.8 1.5 0.8 1.5 V
VCC = 3.6V 0.8 1.5 0.8 1.5 V hysteresis voltage
(VT+ VT)
VCC = 1.2 V 0.1 1.0 0.1 1.0 V
VCC = 1.65 V 0.2 1.15 0.2 1.15 V
VCC = 1.95V 0.2 1.25 0.2 1.25 V
VCC = 2.3V 0.3 1.3 0.3 1.3 V
VCC = 2.5V 0.3 1.3 0.3 1.3 V
VCC = 2.7V 0.3 1.1 0.3 1.1 V
VCC = 3V 0.3 1.2 0.3 1.2 V
VCC = 3.6V [1] 0.3 1.2 0.3 1.2 V
NXP Semiconductors 74L VC14A
Hex inverting Schmitt trigger with 5 V tolerant input
14. Waveforms transfer characteristics

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