74LVC1G175GW Fast Delivery |IC PHOENIX CO.,LIMITED

74LVC1G175GW ,Single D-type flip-flop with reset; positive-edge triggerapplications using I . The I OFF OFFcircuitry disables the output, preventing the damaging backflow ..
74LVC1G175GW ,Single D-type flip-flop with reset; positive-edge triggerFeatures■ Wide supply voltage range from 1.65 V to 5.5 V■ 5 V tolerant inputs for interfacing with ..
74LVC1G175GW ,Single D-type flip-flop with reset; positive-edge triggerGeneral descriptionThe 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type ..
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74LVC1G175GW
Single D-type flip-flop with reset; positive-edge trigger
General descriptionThe 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior most advanced CMOS compatible TTL families.
The input can be driven from either 3.3 Vor5 V devices. This feature allows the use of
this device in a mixed 3.3 V and5 V environment.
This deviceis fully speciﬁedfor partial power-down applications using Ioff. TheIoff circuitry
disables the output, preventing the damaging backﬂow current through the device when is powered down.
The 74LVC1G175 is a single positive edge triggered D-type ﬂip-ﬂop with individual
data (D) input, clock (CP) input, master reset (MR) input, and Q output.
The master reset (MR) is an asynchronous active LOW input and operate independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger actionatall inputs makes the circuit highly tolerantto slower input rise and
fall times. Features Wide supply voltage range from 1.65 Vto 5.5V5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 Vto 1.95V) JESD8-5 (2.3 Vto 2.7V) JESD8B/JESD36 (2.7 Vto 3.6 V). ±24 mA output drive (VCC= 3.0V) ESD protection: HBM EIA/JESD22-A114-B exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V. CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5V Multiple package options Speciﬁed from −40 °Cto+85 °C and −40°Cto +125 °C.
74L VC1G175
Single D-type ﬂip-ﬂop with reset; positive-edge trigger
Philips Semiconductors 74L VC1G175 Quick reference data
[1] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in Volts;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
[2] The condition is VI= GND to VCC. Ordering information Functional diagram
Table 1: Quick reference data
GND=0 V; Tamb =25 °C; tr =tf≤ 2.5 ns.
tPHL, tPLH propagation delay to Q=50 pF; VCC= 3.3V 1.0 3.1 5.7 ns
propagation delay to Q=50 pF; VCC= 3.3V 1.0 2.5 5.8 ns
fmax maximum clock
frequency=50 pF; VCC= 3.3V 175 300 - MHz input capacitance - 2.5 - pF
CPD power dissipation
capacitance
VCC= 3.3V [1][2] -14 - pF
Table 2: Ordering information
74LVC1G175GW −40°Cto +125°C SC-88 plastic surface mounted package; 6 leads SOT363
74LVC1G175GV −40°Cto +125°C SC-74 plastic surface mounted package; 6 leads SOT457
74LVC1G175GM −40°Cto +125°C XSON6 plastic extremely thin small outline package; no
leads; 6 terminals; body 1 × 1.45 × 0.5 mm
SOT886
Philips Semiconductors 74L VC1G175 Pinning information
6.1 Pinning
6.2 Pin description
Table 3: Pin description 1 clock input (LOW-to-HIGH, edge-triggered)
GND 2 ground (0V) 3 data input 4 ﬂip-ﬂop output
VCC 5 supply voltage 6 master reset input (active LOW)
Philips Semiconductors 74L VC1G175 Functional description
7.1 Function table
[1]H= HIGH voltage level;= HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW voltage level;= LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;= LOW-to-HIGH CP transition;= don’t care. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC=0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. Recommended operating conditions
Table 4: Function table[1]
Reset (clear) L X X L
Load ‘1’ H ↑ hH
Load ‘0’ H ↑ lL
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI <0V - −50 mA input voltage [1] −0.5 +6.5 V
IOK output diode current VO >VCC or VO <0V - ±50 mA output voltage active mode [1][2] −0.5 VCC+ 0.5V
Power-down mode [1][2] −0.5 +6.5 V output diode current VO =0 VtoVCC - ±50 mA
ICC, IGND VCC or GND current - ±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb= −40 °C to +125°C - 250 mW
Table 6: Recommended operating conditions
VCC supply voltage 1.65 5.5 V input voltage 0 5.5 V output voltage active mode 0 VCC V
Power-down mode; VCC=0V 0 5.5 V
Philips Semiconductors 74L VC1G175
10. Static characteristics
Tamb ambient temperature −40 +125 °C
tr, tf input rise and fall times VCC= 1.65 V to 2.7V 0 20 ns/V
VCC= 2.7 V to 5.5V 0 10 ns/V
Table 6: Recommended operating conditions …continued
Table 7: Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Tamb = −40 °C to +85°C[1]
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 × VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VOH HIGH-level output
voltage
VI = VIH or VIL= −100 μA; VCC= 1.65Vto5.5V VCC − 0.1 - - V
IO = −4 mA; VCC = 1.65 V 1.2 1.54 - V
IO = −8 mA; VCC = 2.3 V 1.9 2.15 - V
IO = −12 mA; VCC = 2.7 V 2.2 2.50 - V
IO = −24 mA; VCC = 3.0 V 2.3 2.62 - V
IO = −32 mA; VCC = 4.5 V 3.8 4.11 - V
VOL LOW-level output
voltage
VI = VIH or VIL
IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.10 V
IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V
IO = 8 mA; VCC = 2.3 V - 0.12 0.30 V
IO = 12 mA; VCC = 2.7 V - 0.17 0.40 V
IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V
IO = 32 mA; VCC = 4.5 V - 0.39 0.55 V
ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V - ±0.1 ±5 μA
Ioff power OFF leakage
current
VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 μA
ICC quiescent supply current VI = VCC or GND; IO = 0A;
VCC= 5.5V 0.1 10 μA
ΔICC additional quiescent
supply current per pin
VI = VCC − 0.6 V; IO = 0A;
VCC= 2.3 V to 5.5 V 5 500 μA input capacitance - 2.5 - pF
Philips Semiconductors 74L VC1G175
[1] All typical values are measured at Tamb = 25°C.
Tamb = −40 °C to +125°C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 × VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCCV
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VOH HIGH-level output
voltage
VI = VIH or VIL= −100 μA; VCC= 1.65Vto5.5V VCC − 0.1 - - V
IO = −4 mA; VCC = 1.65 V 0.95 - - V
IO = −8 mA; VCC = 2.3 V 1.7 - - V
IO = −12 mA; VCC = 2.7 V 1.9 - - V
IO = −24 mA; VCC = 3.0 V 2.0 - - V
IO = −32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output
voltage
VI = VIH or VIL
IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.10 V
IO = 4 mA; VCC = 1.65 V - - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.80 V
IO = 32 mA; VCC = 4.5 V - - 0.80 V
ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V - - ±20 μA
Ioff power OFF leakage
current
VI or VO = 5.5 V; VCC = 0 V - - ±20 μA
ICC quiescent supply current VI = VCC or GND; IO = 0A;
VCC= 5.5V 40 μA
ΔICC additional quiescent
supply current per pin
VI = VCC − 0.6 V; IO = 0A;
VCC= 2.3 V to 5.5 V - 5000 μA
Table 7: Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Philips Semiconductors 74L VC1G175
11. Dynamic characteristics
Table 8: Dynamic characteristics
GND = 0 V; see Figure8
Tamb = −40 °C to +85°C[1]
tPHL, tPLH propagation delay CP to Q see Figure6
VCC = 1.65 V to 1.95 V 1.5 4.9 13.4 ns
VCC = 2.3 V to 2.7 V 1.0 3.1 7.1 ns
VCC = 2.7 V 1.0 3.2 7.1 ns
VCC = 3.0 V to 3.6 V [2] 1.0 3.1 5.7 ns
VCC = 4.5 V to 5.5 V 1.0 2.2 4.0 ns
propagation delay MR to Q see Figure7
VCC = 1.65 V to 1.95 V 1.5 4.3 12.9 ns
VCC = 2.3 V to 2.7 V 1.0 2.8 7.0 ns
VCC = 2.7 V 1.0 3.0 7.0 ns
VCC = 3.0 V to 3.6 V [2] 1.0 2.5 5.8 ns
VCC = 4.5 V to 5.5 V 1.0 2.0 4.1 ns clock pulse width HIGH or
LOW
see Figure6
VCC = 1.65 V to 1.95 V 6.2 - - ns
VCC = 2.3 V to 2.7 V 2.7 - - ns
VCC = 2.7 V 2.7 - - ns
VCC = 3.0 V to 3.6 V [2] 2.7 1.3 - ns
VCC = 4.5 V to 5.5 V 2.0 - - ns
master reset pulse width
LOW
see Figure7
VCC = 1.65 V to 1.95 V 6.2 - - ns
VCC = 2.3 V to 2.7 V 2.7 - - ns
VCC = 2.7 V 2.7 - - ns
VCC = 3.0 V to 3.6 V [2] 2.7 1.6 - ns
VCC = 4.5 V to 5.5 V 2.0 - - ns
trem removal time master reset see Figure7
VCC = 1.65 V to 1.95 V 1.9 - - ns
VCC = 2.3 V to 2.7 V 1.4 - - ns
VCC = 2.7 V 1.3 - - ns
VCC = 3.0 V to 3.6 V [2] 1.2 0.4 - ns
VCC = 4.5 V to 5.5 V 1.0 - - ns
tsu set-up time D to CP see Figure6
VCC = 1.65 V to 1.95 V 2.9 - - ns
VCC = 2.3 V to 2.7 V 1.7 - - ns
VCC = 2.7 V 1.7 - - ns
VCC = 3.0 V to 3.6 V [2] 1.3 0.5 - ns
VCC = 4.5 V to 5.5 V 1.1 - - ns
Philips Semiconductors 74L VC1G175 hold time D to CP see Figure6
VCC = 1.65 V to 1.95 V 0.0 - - ns
VCC = 2.3 V to 2.7 V 0.3 - - ns
VCC = 2.7 V 0.5 - - ns
VCC = 3.0 V to 3.6 V [2] 1.2 0.2 - ns
VCC = 4.5 V to 5.5 V 0.5 - - ns
fmax maximum clock pulse
frequency
see Figure6
VCC = 1.65 V to 1.95 V 80 125 - MHz
VCC = 2.3 V to 2.7 V 175 - - MHz
VCC = 2.7 V 175 - - MHz
VCC = 3.0 V to 3.6 V [2] 175 300 - MHz
VCC = 4.5 V to 5.5 V 200 - - MHz
CPD power dissipation
capacitance
VCC= 3.3V [3][4] -14 - pF
Tamb = −40 °C to +125°C
tPHL, tPLH propagation delay CP to Q see Figure6
VCC = 1.65 V to 1.95 V 1.5 - 17 ns
VCC = 2.3 V to 2.7 V 1.0 - 9.0 ns
VCC = 2.7 V 1.0 - 9.0 ns
VCC = 3.0 V to 3.6 V 0.5 - 7.5 ns
VCC = 4.5 V to 5.5 V 0.5 - 5.5 ns
propagation delay MR to Q see Figure7
VCC = 1.65 V to 1.95 V 1.5 - 17 ns
VCC = 2.3 V to 2.7 V 1.0 - 9.0 ns
VCC = 2.7 V 1.0 - 9.0 ns
VCC = 3.0 V to 3.6 V 0.5 - 7.5 ns
VCC = 4.5 V to 5.5 V 0.5 - 5.5 ns clock pulse width HIGH or
LOW
see Figure6
VCC = 1.65 V to 1.95 V 6.2 - - ns
VCC = 2.3 V to 2.7 V 2.7 - - ns
VCC = 2.7 V 2.7 - - ns
VCC = 3.0 V to 3.6 V 2.7 - - ns
VCC = 4.5 V to 5.5 V 2.0 - - ns
master reset pulse width
LOW
see Figure7
VCC = 1.65 V to 1.95 V 6.2 - - ns
VCC = 2.3 V to 2.7 V 2.7 - - ns
VCC = 2.7 V 2.7 - - ns
VCC = 3.0 V to 3.6 V 2.7 - - ns
VCC = 4.5 V to 5.5 V 2.0 - - ns
Table 8: Dynamic characteristics …continued
GND = 0 V; see Figure8
Philips Semiconductors 74L VC1G175
[1] All typical values are measured at Tamb = 25°C.
[2] These typical values are measured at VCC = 3.3 V.
[3] CPD is used to determine the dynamic power dissipation (PDin μW). =CPD× VCC2×fi× N+ Σ(CL× VCC2×fo) where:= input frequency in MHz;= output frequency in MHz;= output load capacitance in pF;
VCC= supply voltage in Volts;= number of inputs switching;
Σ(CL× VCC2×fo)= sum of the outputs.
[4] The condition is VI= GND to VCC.
trem removal time master reset see Figure7
VCC = 1.65 V to 1.95 V 1.9 - - ns
VCC = 2.3 V to 2.7 V 1.4 - - ns
VCC = 2.7 V 1.3 - - ns
VCC = 3.0 V to 3.6 V 1.2 - - ns
VCC = 4.5 V to 5.5 V 1.0 - - ns
tsu set-up time D to CP see Figure6
VCC = 1.65 V to 1.95 V 2.9 - - ns
VCC = 2.3 V to 2.7 V 1.7 - - ns
VCC = 2.7 V 1.7 - - ns
VCC = 3.0 V to 3.6 V 1.3 - - ns
VCC = 4.5 V to 5.5 V 1.1 - - ns hold time D to CP see Figure6
VCC = 1.65 V to 1.95 V 0.0 - - ns
VCC = 2.3 V to 2.7 V 0.3 - - ns
VCC = 2.7 V 0.5 - - ns
VCC = 3.0 V to 3.6 V 1.2 - - ns
VCC = 4.5 V to 5.5 V 0.5 - - ns
fmax maximum clock pulse
frequency
see Figure6
VCC = 1.65 V to 1.95 V 80 - - MHz
VCC = 2.3 V to 2.7 V 175 - - MHz
VCC = 2.7 V 175 - - MHz
VCC = 3.0 V to 3.6 V 175 - - MHz
VCC = 4.5 V to 5.5 V 200 - - MHz
Table 8: Dynamic characteristics …continued
GND = 0 V; see Figure8

Partno	Mfg	Dc	Qty	Available	Descript
74LVC1G175GW	PHI	N/a	1100	avai	Single D-type flip-flop with reset; positive-edge trigger