80C32 ,80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHzapplications that require pulse width modulation, high-speed I/O andup/down counting capabilities s ..
80C321 , CMOS SINGLE CHIP MICROCONTROLLER
80C32-12 , CMOS 0 to 44 MHz Single Chip 8-bit Microntroller
80C32-16 , CMOS 0 to 44 MHz Single Chip 8-bit Microntroller
80C35 ,CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)TOSH I BA TMP80C48A/35ACMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)TM P80C48AP /TMP80C48AP- 6TM ..
80C51 ,CMOS 0 to 42 MHz Single-Chip 8 Bit MicrocontrollerFEATURESThe Philips 8XC51/31 is a high-performance static 80C51 design• 8051 Central Processing Uni ..
93LC46C , 1K Microwire Compatible Serial EEPROM Low-Power CMOS Technology
93LC46SN , 1K/2K/4K 2.5V Microwire Serial EEPROM
93LC66AI/P , 4K Microwire Compatible Serial EEPROM
93LC66A-I/P , 4K Microwire Compatible Serial EEPROM
93LC66A-I/P , 4K Microwire Compatible Serial EEPROM
93LC66AI/SN , 4K Microwire Compatible Serial EEPROM
80C32-87C52-P80C32SBAA-P80C32SBBB-P80C32SFAA-P80C32SFBB-P80C32UBAA-P80C32UBBB-P80C32UBPN-P80C32UFAA-P80C32UFBB-P80C32UFPN-P80C51FA-4A-P80C51FA-4B-P80C51FA-5A-P80C51FA-5B-P80C51FA-JB-P80C51RA+4A-P80C51RA+4B-P80C51RA+5A-P80C51RA+5B-P80C51RA+JB-P
80C51 8-bit microcontroller family 8K.64K/256.1K OTP/ROM/ROMless, low voltage 2.7V.5.5V, low power, high speed 33 MHz
Product specification
Supersedes data of 1998 Jun 04
IC20 Data Handbook
1999 Apr 01
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
DESCRIPTIONThree different Single-Chip 8-Bit Microcontroller families are
presented in this datasheet: 80C32/8XC52/8XC54/8XC58 80C51FA/8XC51FA/8XC51FB/8XC51FC 80C51RA+/8XC51RA+/8XC51RB+/8XC51RC+/8XC51RD+
For applications requiring 4K ROM/EPROM, see the 8XC51/80C31
8-bit CMOS (low voltage, low power, and high speed)
microcontroller families datasheet.
All the families are Single-Chip 8-Bit Microcontrollers manufactured
in advanced CMOS process and are derivatives of the 80C51
microcontroller family. All the devices have the same instruction set
as the 80C51.
These devices provide architectural enhancements that make them
applicable in a variety of applications for general control systems.
The ROMless devices, 80C32, 80C51FA, and 80C51RA+ can
address up to 64K of external memory. All the devices have four
8-bit I/O ports, three 16-bit timer/event counters, a multi-source,
four-priority-level, nested interrupt structure, an enhanced UART
and on-chip oscillator and timing circuits. For systems that require
extra memory capability up to 64k bytes, each can be expanded
using standard TTL-compatible memories and logic.
Its added features make it an even more powerful microcontroller for
applications that require pulse width modulation, high-speed I/O and
up/down counting capabilities such as motor control. It also has a
more versatile serial channel that facilitates multiprocessor
communications.
FEATURES 80C51 Central Processing Unit Speed up to 33MHz Full static operation Operating voltage range: 2.7V to 5.5V @ 16MHz Security bits:
ROM – 2 bits
OTP–EPROM – 3 bits Encryption array – 64 bytes RAM expandable to 64K bytes 4 level priority interrupt 6 or7 interrupt sources, depending on device Four 8-bit I/O ports Full-duplex enhanced UART
Framing error detection
Automatic address recognition Power control modes
Clock can be stopped and resumed
Idle mode
Power down mode Programmable clock out Second DPTR register Asynchronous port reset Low EMI (inhibit ALE)
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
BLOCK DIAGRAM
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
LOGIC SYMBOL
PIN CONFIGURATIONS
DUAL IN-LINE PACKAGE PIN FUNCTIONS
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
PIN DESCRIPTIONS
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
PIN DESCRIPTIONS (Continued)
NOTE:To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS – 0.5V, respectively.
80C51 8-bit microcontroller family
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
AND 80C32 ORDERING INFORMA
TIONime Programmable devices, See P89C51RX+ Flash datasheet.
80C51 8-bit microcontroller family
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
ORDERING
INFORMA
TIONime Programmable devices, See P89C51RX+ Flash datasheet.
80C51 8-bit microcontroller family
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
AND 80C51RA+ ORDERING INFORMA
TIONime Programmable devices, See P89C51RX+ Flash datasheet.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Table 1. 8XC52/54/58/80C32 Special Function Registers SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs. Reserved bits.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Table 2. 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers SFRs are bit addressable.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Table 2. 8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers (Continued) SFRs are bit addressable. SFRs are modified from or added to the 80C51 SFRs. Reserved bits.
OSCILLATOR CHARACTERISTICSXTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESETA reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VCC and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above VIH1 (min.) is applied to RESET.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
LOW POWER MODES
Stop Clock ModeThe static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
Idle ModeIn the idle mode (see Table 3), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
Power-Down ModeTo save even more power, a Power Down mode (see Table 3) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0V and care must be taken to return VCC to
the minimum specified operating voltages before the Power Down
Mode is terminated.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the oscillator
but bringing the pin back high completes the exit. Once the interrupt
is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put the device into Power Down.
LPEPThe LPEP bit (AUXR.4), only needs to be set for applications
operating at VCC less than 4V.
POWER OFF FLAGThe Power Off Flag (POF) is set by on-chip circuitry when the VCC
level on the 8XC51FX/8XC51RX+ rises from 0 to 5V. The POF bit
can be set or cleared by software allowing a user to determine if the
reset is the result of a power-on or a warm start after powerdown.
The VCC level must remain above 3V for the POF to remain
unaffected by the VCC level.
Design Consideration• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
ONCE ModeThe ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by: Pull ALE low while the device is in reset and PSEN is high; Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-OutA 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed: to input the external clock for Timer/Counter 2, or to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a
16MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
Oscillator Frequency (65536 RCAP2H,RCAP2L)
Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
Table 3. External Pin Status During Idle and Power-Down Mode
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
TIMER 2 OPERATION
Timer 2Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes: Capture, Auto-reload (up or down counting), and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 4.
Capture ModeIn the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but
with the added feature that a 1-to-0 transition at external input T2EX
causes the current value in the Timer 2 registers, TL2 and TH2, to
be captured into registers RCAP2L and RCAP2H, respectively. In
addition, the transition at T2EX causes bit EXF2 in T2CON to be
set, and EXF2 like TF2 can generate an interrupt (which vectors to
the same location as Timer 2 overflow interrupt. The Timer 2
interrupt service routine can interrogate TF2 and EXF2 to determine
which event caused the interrupt). The capture mode is illustrated in
Figure 2. (There is no reload value for TL2 and TH2 in this mode.
Even when a capture event occurs from T2EX, the counter keeps on
counting T2EX pin transitions or osc/12 pulses.)
Auto-Reload Mode (Up or Down Counter)In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter [C/T2* in T2CON]) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
In Figure 5 DCEN=1, which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16–bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Table 4. Timer 2 Operating Modes
Figure 2. Timer 2 in Capture Mode
Figure 3. Timer 2 Mode (T2MOD) Control Register
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Figure 6. Timer 2 in Baud Rate Generator Mode
Table 5. Timer 2 Generated Commonly Used
Baud Rates
Baud Rate Generator ModeBits TCLK and/or RCLK in T2CON (Table 5) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Modes1 and3 Baud Rates� Timer2 Overflow Rate
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Oscillator Frequency
[32� [65536� (RCAP2H,RCAP2L)]]
Modes 1 and 3 Baud Rates =
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
Table 5 shows commonly used baud rates and how they can be
obtained from Timer 2.
Summary Of Baud Rate EquationsTimer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Baud Rate� Timer2 Overflow Rate
If Timer 2 is being clocked internally , the baud rate is:
Baud Rate� fOSC
[32 �[65536 �(RCAP2H,RCAP2L)]]
Where fOSC= Oscillator Frequency
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
RCAP2H,RCAP2L� 65536�� fOSC �Baud Rate�
Timer/Counter 2 Set-upExcept for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. See Table 6 for set-up
of Timer 2 as a timer. Also see Table 7 for set-up of Timer 2 as a
counter.
Table 6. Timer 2 as a Timer
Table 7. Timer 2 as a Counter
NOTES: Capture/reload occurs only on timer/counter overflow. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Enhanced UARTThe UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication as does the standard 80C51 UART.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
Automatic Address RecognitionAutomatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Slave 0 SADDR = 1100 0000
SADEN =
Given = 1100 00X0
Slave 1 SADDR = 1100 0000
SADEN =
Given = 1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0 SADDR = 1100 0000
SADEN = 1111 1001
Given = 1100 0XX0
Slave 1 SADDR = 1110 0000
SADEN = 1111 1010
Given = 1110 0X0X
Slave 2 SADDR = 1110 0000
SADEN = 1111 1100
Given = 1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Figure 7. SCON: Serial Port Control Register
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Figure 8. UART Framing Error Detection
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Interrupt Priority StructureThe 8XC51FA/FB/FC and 8XC51RA+/RB+/RC+/RD+ have a
7-source four-level interrupt structure (see Table 8). The
80C52/54/58 and 80C32 only have a 6-source four-level interrupt
structure because these devices do not have a PCA.
There are 3 SFRs associated with the four-level interrupt. They are
the IE, IP, and IPH. (See Figures 10, 11, and 12.) The IPH (Interrupt
Priority High) register makes the four-level interrupt structure
possible. The IPH is located at SFR address B7H. The structure of
the IPH register and a description of its bits is shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
Table 8. Interrupt Table
NOTES: L = Level activated T = Transition activated
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Figure 11. IP Registers
Figure 12. IPH Registers
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
Reduced EMI ModeThe AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
Reduced EMI Mode
AUXR (8EH) 6 54 32 1 0
AUXR.1 EXTRAM (RX+ only)
AUXR.0 AO Turns off ALE output.
Dual DPTRThe dual DPTR structure (see Figure 13) is a way by which the chip
will specify the address of an external data memory location. There
are two 16-bit DPTR registers that address the external memory,
and a single bit called DPS = AUXR1/bit0 that allows the program
code to switch between them. New Register Name: AUXR1# SFR Address: A2H Reset Value: xxxx00x0B 54 32 10
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg DPS
DPTR0 0
DPTR1 1
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
The GF3 bit is a general purpose user–defined flag. Note that bit 2 is
not writable and is always read as a zero. This allows the DPS bit to
be quickly toggled simply by executing an INC DPTR instruction
without affecting the GF3 or LPEP bits.
Figure 13.
DPTR InstructionsThe instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR Increments the data pointer by 1
MOV DPTR, #data16 Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR Move code byte relative to DPTR to ACC
MOVX A, @ DPTR Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
(8XC51FX and 8XC51RX+ ONLY)
Programmable Counter Array (PCA)
(8XC51FX and 8XC51RX+ only)The Programmable Counter Array available on the 8XC51FX and
8XC51RX+ is a special 16-bit Timer that has five 16-bit
capture/compare modules associated with it. Each of the modules
can be programmed to operate in one of four modes: rising and/or
falling edge capture, software timer, high-speed output, or pulse
width modulator. Each module has a pin associated with it in port 1.
Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc.
The basic PCA configuration is shown in Figure 14.
The PCA timer is a common time base for all five modules and can
be programmed to run at: 1/12 the oscillator frequency, 1/4 the
oscillator frequency, the Timer 0 overflow, or the input on the ECI pin
(P1.2). The timer count source is determined from the CPS1 and
CPS0 bits in the CMOD SFR as follows (see Figure 17):
CPS1 CPS0 PCA Timer Count Source 0 1/12 oscillator frequency 1 1/4 oscillator frequency 0 Timer 0 overflow 1 External Input at ECI pin
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function on
module 4, and ECF which when set causes an interrupt and the
PCA overflow flag CF (in the CCON SFR) to be set when the PCA
timer overflows. These functions are shown in Figure 15.
The watchdog timer function is implemented in module 4 (see
Figure 24).
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and each module (refer to Figure 18).
To run the PCA the CR bit (CCON.6) must be set by software. The
PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when
the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set, The CF bit can only be cleared
by software. Bits 0 through 4 of the CCON register are the flags for
the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set
by hardware when either a match or a capture occurs. These flags
also can only be cleared by software. The PCA interrupt system
shown in Figure 16.
Each module in the PCA has a special function register associated
with it. These registers are: CCAPM0 for module 0, CCAPM1 for
module 1, etc. (see Figure 19). The registers contain the bits that
control the mode that each module will operate in. The ECCF bit
(CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt
when a match or compare occurs in the associated module. PWM
(CCAPMn.1) enables the pulse width modulation mode. The TOG
bit (CCAPMn.2) when set causes the CEX output associated with
the module to toggle when there is a match between the PCA
counter and the module’s capture/compare register. The match bit
MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter
and the module’s capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the
positive edge. If both bits are set both edges will be enabled and a
capture will occur for either transition. The last bit in the register
ECOM (CCAPMn.6) when set enables the comparator function.
Figure 20 shows the CCAPMn settings for the various PCA
functions.
There are two additional registers associated with each of the PCA
modules. They are CCAPnH and CCAPnL and these are the
registers that store the 16-bit count when a capture occurs or a
compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output.
Figure 14. Programmable Counter Array (PCA)
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
(8XC51FX and 8XC51RX+ ONLY)
Figure 15. PCA Timer/Counter
Figure 16. PCA Interrupt System
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
(8XC51FX and 8XC51RX+ ONLY)
Figure 17. CMOD: PCA Counter Mode Register
Philips Semiconductors Product specification
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
(8XC51FX and 8XC51RX+ ONLY)
Figure 19. CCAPMn: PCA Modules Compare/Capture Registers
Figure 20. PCA Module Modes (CCAPMn Register)
PCA Capture ModeTo use one of the PCA modules in the capture mode either one or
both of the CCAPM bits CAPN and CAPP for that module must be
set. The external CEX input for the module (on port 1) is sampled for
a transition. When a valid transition occurs the PCA hardware loads
the value of the PCA counter registers (CH and CL) into the
module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit
for the module in the CCON SFR and the ECCFn bit in the CCAPMn
SFR are set then an interrupt will be generated. Refer to Figure 21.
16-bit Software Timer ModeThe PCA modules can be used as software timers by setting both
the ECOM and MAT bits in the modules CCAPMn register. The PCA
timer will be compared to the module’s capture registers and when a
match occurs an interrupt will occur if the CCFn (CCON SFR) and
the ECCFn (CCAPMn SFR) bits for the module are both set (see
High Speed Output ModeIn this mode the CEX output (on port 1) associated with the PCA
module will toggle each time a match occurs between the PCA
counter and the module’s capture registers. To activate this mode
the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must
be set (see Figure 23).
Pulse Width Modulator ModeAll of the PCA modules can be used as PWM outputs. Figure 24
shows the PWM function. The frequency of the output depends on
the source for the PCA timer. All of the modules will have the same
frequency of output because they all share the PCA timer. The duty
cycle of each module is independently variable using the module’s
capture register CCAPLn. When the value of the PCA CL SFR is
less than the value in the module’s CCAPLn SFR the output will be
low, when it is equal to or greater than the output will be high. When
