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80C35 ,CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)TOSH I BA TMP80C48A/35ACMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)TM P80C48AP /TMP80C48AP- 6TM ..
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93LC66A-I/SN , 4K Microwire Compatible Serial EEPROM

80C35
CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)
TOSH I BA TMP80C48A/3SA
CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)
TM P80C48AP /TM P80C48AP- 6
TM P80C35AP /TM P80C3 SAP- 6
TM P80C48AU/TM P80C48AU-6
l. GENERAL DESCRIPTION AND FEATURES
The TMP80C48A is a single chip microcomputer fabricated in Silicon Gate CMOS
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included in a single
chip; an 8-bit CPU, 64x8 RAM data memory, le8 ROM program memory, 27 I/O
lines and an 8-bit timer/event counter.
The TMP80C48A is particularly efficient as a controller. It has extensive bit handling
capability as well as facilities for both binary and BCD arithmetic.
The TMP80C35A/-6 is the equivalent of a TMP8OC48A/-6 without ROM program
memory on chip. By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP8OC48AP/-6 and TMP80C35AP/-6 are in a standard Dual Inline Package.
The TMP80C48AU/-6 is in a 44-pin Micro Flat Package.
FEATURES
0 TMP8OC48AP/TMP80C35AP/TMP80C48AU
1 B6ps Instruction Cycle Time -40oC to 85°C, 5V i‘ 10%
0 TMP80C48AP-6/TMP80C35AP-6/TMP8OC48AU-6
2.5ps Instruction Cycle Time -40oC) to 85°C, 5V i 20%
0 Software Upward Compatible with TMP8048AP/INTEL'S 8048
0 1K X 8 masked ROM/64 X 8 RAM
0 Low Power
10mA MAX. in Normal Operation (VCC = 5V, fXTAL = 6MHz)
lOpA MAX. in Power Down Mode (VCC =5V, fXTAL : DC)
0 Power Down Mode (Stand-by Mode)
0 Halt Mode(Id1e Mode)
MCU48-1
TOSHI BA TMP80C48A/35A
2. PIN CONNECTIONS AND PIN FUNCTIONS
2.1 Pin Connections (Top View)
T0121 V 40 J Vcc(+5V)
XTAL. t2 39 1 T1
XTAL2 C3 38 y P27
RESET C4 37 3 P25
5 L 5 36 :1 P25
FN-Tt:6 35 3 P24
EA E7 34 l P17
TIt5C8 33 l P15
PSEN " 32 J P15
-Vimro 31 1 P14
ALE E 11 30 3 P13
DBoE12 29 Cl P12
DB; C13 28 3 P11
DB2 E 14 27 l P10
DB3 C 15 26 3 R
DB4 E 16 25 J PROG
DBs E 17 24 3 P23
DB6 E 18 23 3 P22
DB7 E 19 22 i] P21
Vss C20 21 2 P20
Figure 2.1 DIP Pin Connections
iisri-sizc-pjiseas,
DO tii-stat-ir/F/ia, 'Els,
DBs NC
DBs XTAL2
DB7 XTAL1
Vss To
Pao Vcc
P21 T1
P22 p27
P23 P26
PROG P25
Figure 2.1 Micro Flat Package Pin Connections
MCU48-2
TOSHI BA TMP80C48A/35A
Pin Names And Pin Description
0 VSS (Power Supply)
Circuit GND potential
0 Vcc (Power Supply)
+ 5V during operation
0 'PT? (Input)
The control signal for the power saving at the power down mode (Active Low)
It PROG (Output)
Output strobe for the TMP82C43P I/O expander.
0 1310-1317 (Input/Output) Portl
8-bit quasi-bidirectionalp0rt(Interna1 Pulh1p=50KQ).
o P204327 (Input/Output) Port2
8-bit quasi-bidirectional port (Internal Pullup=50KQ).
P20-P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the TMP82C43P.
o DBo-DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using the
TID, W strobes. The port can also be statically latched. Contains the 8 low order
program counter bits during an external program memory fetch, and receives the
addressed instruction under the control of FEW.
Also contains the address and data during an external RAM data store
instruction, under control of ALE, R-D, and W.
0 To (Input/Output)
Input pin testable using the conditional transfer instructions J TO and J NTO. T0
can be designated as a clock output using ENTO CLK instruction.
0 T1 (Input)
Input pin testable using the JTl and JNTl instruction. Can be designated the
event counter input using the timer/STRT CNT instruction.
0 INT“ (Input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. Also testable with conditionaljump instruction.
(Active low)
MCU48-3
TOSHIBA TMP80C48A/35A
0 "1tTo (Output)
Output strobe activated during a Bus read. Can be used to enable data onto the
Bus from an external device. Used as a Read Strobe to External Data Memory
(Active Low).
It WR (Output)
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
0 RESET (Input)
Active Low signal which is used to initialize the Processor. Also used during the
power down mode.
0 ALE (Output)
Address Latch Enable. This signal occurs once during each cycle and is useful
as a clock output. The negative edge of ALE strobes address into external data and
program memory.
0 PSEN (Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
0 E (Input)
Single step input can be used in conjunction with ALE to "single step" processor
through each instruction when §S is low the CPU is placed into a wait state after it
has completed the instruction being executed. Also used during the power down
0 EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing and
program verification. (Active High)
0 XTAL1 (Input)
One side of crystal input for internal oscillator. Also input for external source.
It XTAL2 (Input)
Other side of crystal input.
M CU48-4
TOSHIBA TMP80C48A/35A
2.3 Block Diagram
DBo-DB7 P1o-P17 on-P27
[RT PORTOBUFFER PORT1 BUFFER PORT2BUFFER
wi"'? f? f? 4
OUTPUT OUTPUT OUTPUT MASK ROM
f LATCH LATCH LATCH 2
XT AL a:"'e, ----2/)) 1K x 8
1/32 1 (PROGRAM AREA)
INTERRUPT TIMER/
CIRCUIT - COUNTER PCH PCL F
ACCUMU- TEMPO-
LATOR RARY REG FLAGS j E E i)
RAM ADDRESS
i} INSTRUC- PS REGISTER
ACCUMULA- RAM
TOR LATCH TION
REGISTER/ 6 64 x 8
DECODER TIMER
Fo F1 lCARRY
ACCUMULATORA CONDITIONAL
BITTEST / JUMPCIRCUIT
To T, W
POWER 1 , f
SAVE PT
XTAL1 XTALZ RESET W EA Ts ALE PSEN W WR PROG
's'--------) _ _ l- m '- a. w u.- Lu _ a: Lu
n: m D a. D mu Lu m to ca < w LLI m
or-- o. D CL mm _ Lu 0 O _ m Ch O
_ 3 a a: a (r .J m a: n: c: < O a at
< o. - n: _ 0 Lu cu r- _ o m < _
_, 2 Lu 0 m u: cy m m F- th, W
-' - r- F-- < _l < m 8
_ nu Z 0 I u:
U m - A 2 U i?
m Lu < - _ n:
o a: z m < O
(I -: O
LLI Q:
; 020989
Note 1 : The lower order 4 bit ofport 2 output latch are used also for inputs/output operations
with the I/O expander.
Note 2 : The output latch ofport 0 is also used for address output.
Figure 2.3 Block Diagram
MCU48-5
TOSHIBA TMP80C48A/35A
3. MACHINE INSTRUCTION
The following symbols and codes are used in the list of machine instruction.
Symbol Meaning
Rp Working register(0Pp l/O port address P; (0.13!) Branch instruction in accordance with bit content (b) of operand
aH Higherorder3 bits ofa
aN Medium order4bits ofa
aL Lowerorder4 bits ofa
aML Medium orderorlowerorder8bits ofa
(a) Content ofa
I] (a) , Content of RAM addressed by a
EXT[ (a) il Content of external RAM addressed by a
PROC (a) il Content of ROM addressed by a
atm) Value at bit position m of a
atm:ny Value at bit position mtonofa
a4-b Store a into b
ae-rl: Exchangeaforb
. Connection
tl . 1 complement ofa
a+b a plus b (Addition)
a-b a minus b (Subtraction)
a/\b LogicalANDforaand b
avb Logical ORforaand b
aVb Exclusive ORfora and b
a=b a is equal to b
aCrb ais not equaltob
(a) BCD Converted value of accumulator
MCU48-6
TOSHIBA TMP80C48A/35A
List of TLCS-48 Machine Instruction (1/4)
ObjectCode
E Assembler (Ist) Flag
'ie (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
A00 A,Rr 01101rwp 68+r (A)e(A)+(Rr) P--0-7 _.... i“; __.. 1
RL A 11100111 E7 (A) <-(A) 1
w----.-..----- .V__P_.VFVFP.PV_V.PP_. .P.__V.r_.rr_ Jh)f/)?t(l).)f.l.ir ................... 9f9:9 ___-___-rl..--.-.
RLC A 11110111 F7 (A)tn+1Y '-(A)O) t 1
(C)<-(A)<7>
--------FW.--------.-r- .(1N).f/l?...t.,(f.)...._..., __ry-rprf....., -_-- _pt_r_ _Wv____ .__._.
RR A 01110111 77 (A)4-(A) n=0.-6 1
--t---t-l-.r-tt.,t-t--_---_ (A)<7>*(A)<°> _-_-_-F-__-___
RRC A 01100111 67 (A)<-(A) t 1
(C)e(A)40Y
(A)477 <-(C) n--0.-6
It! ......... 9.12.”??? ......... 1tlt.lil.19op..,.p.?tp ...... (9)5939.) -rrlr._F._PVl_.__. 971’? -_____e____________._P__V 3
(ll/ll-Ct.,.? ........... 99.91.1999... 1!lte, J _epl..t(/)) .............................. P111? .................. _ il.
o ANL Pp,#1 100110pp 98+p (Pp)e(Pp)/Vi P=1,2 2
> ---_-N-.____r__V_ 1.1111111. ,,._,..i.,o.' "rr-r-__-___..'.'.'-''''''''''''''"'.'.''''-''''''''''''.''''''''""'.''''''''''''""'"'''''''''"''''"'''''"'
ORL Pp.#1 100010pp 88+p (Pp) <-(Pp)\/1' P=1,2 2
iiiiiiii ii
MCU48-7
TOSHIBA TMP80C48A/35A
List of TLCS-48 Machine Instruction (2/4)
ObjectCode
E Assembler (1st) Flag
'ie . (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
Jllf ...... A...z...BU5. . 00001000 08 (N*(BUS) ................ 2
OUTL ”BUS, A ......... iii'fiijiii'i'iij ........ 02 ....... (BUS)¢-(AC) V.Vl'V'P'.l'PV"lPl.F_''l'''P..'_P-P--- ii -
jiiir - iii'jiyir''"ii'oiiri'i'iiiij ........ 98 TirjiFiiiijer)'i) ................................................................ i' .......
iiiiiiii ii
O 00L ..... 01-1-3219}; ........... "iiiiiihuiij' ........ iiir" 'rii'tj'i)'H'iiijej''ih'' m--..--.-.--.----,-. i' ......
N iiiiiiii ii
- MOVDAPp ........ iiiiifijrihrik'i') ....... "('rii:i:'iir'i-'('"irp'')' ................... ’34:? _PrP..V'P_FPVPVPVr'VPl-. ii -
(A)<7:4> H)
100011pp
INC RP 00011ppp 18+p ..I.(l1.:).rtL(.l1.r..).1t.1 _.------------..
DEC Rp 11001ppp C8+r (Rr) '-(Rr)-1
JMP a aH00100 aH+4 (PC)<10:0> <-a
aML (PC)411) 4-(DBF)
0041515000 .................... 10101000101. ........ iii ....... "('ii'djk''i:''i)'rdi'iiijri'iieFi - i >“(HA)hj ............................... ji -
ifji'ii'"'"ii'/',% ........... "i'iiiji'r':/'/"'" E041" ....... "('ii'ri'd('ii/j'-r'1' m-.------..--..-.--.----.-. it .......
aML if(Rr) '0then(PC)0:iDeaML
else no operation
JCa1111011010..”15.6.“”iuf”(“CU)';1winé'n.(quC)2705'05040-‘a1ML -_e.e-._t-...-t-t-t- ii -
. ..................... aML else no operation . . . .
S jiiir' a ........... 'fi'iij'i'i'iij ........ Eém "in"ej'--j'iia"i'('irdjk'r'.'iN'-'diii', ..................................... ii .......
J, -.P_._F.F.--t--- Ill ........ ts.1s.i.erptr.t.optr.afp.'y. ................
y, JI a 11000110 """ 06"” "'1'f(A)=0 thén(PC)<'7'é'0'>'<'~éML """""""""""""""" ji -
= P_.i.PrFP_...I.F.F...- Ill ............. t.s..l.si.t..1trf.ro?I.aA1?.n. .___.V.l_.Pt......V.P__...tFe_W_lt._-t--
C, VJNZ a 10010110 _ 06'" "1"f('A)==0 then(Pc)(7ADeaNL 2
E aML e1se no operation
I 'J'T'OHMé .................... 00.110110 ........ 00 ....... "i'i"iiiu'r''ii'ai"('ie)kj/iN'a/L -t-.-_Fr._Vl.I__..._. ii .......
E .F.r'.F.lPP_F__.-.--_ itll, ....................... 1l.s.itptrSp,t.et.1t.y'! ---l--.--r--r.lFt-N--...-..-
m JNTO a 00100110 26 if T0=0 then(PC)47:0Fal4L 2
t; aML else no operation
'dir-ll .................... iiiiirdiiij ........ 56 ....... 'iCir--r1"thdl/(jrd')k'j1.'iN'-'t'iiir, -.__.r.-.V_.._.P__._P_-P_r-Ftr- 2 ......
al/L else no operation
JNfimé ____________________ 01000-110 - ii" "'irii-iii'''tj'ailj'e)''t''i':"ij'y'iaTL' .W_.____V_rP_P'lV_-tl.r-_ 2. ......
_________ aML else no operation
JFOa _ _ 10110110 ........ iii'lrt'''r'ii'rr'.i'''t'i'ail'i'e)k''i':"ij'y''dd'iiL' ........................................ ii .......
aML else no operation
'{J'F'iwué .................... 011110.110.” W76 ''ij'"ri--h'''''t''r'ai'je)kj':''ijSl-'diiil --''-''-r-- "''2' __
IIIIIIIII aML else no operation
JTFHM'a .................. "0'iii''1'iir1''r''''u"' .. 'rt''iiu''f''t''iaije)ki.d'rdi'sii', .................................. i ......
aML else no operation
(1) ..... Register Instruction 020989
MCU48-8
TOSHIBA TMP80C48A/35A
List of TLCS-48 Machine Instruction (3/4)
Object Code
E Assembler (1st) Flag
'pe (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
JNI a 10000110 86 it INT =0 then(P0)O:0eaNL 2
aML else no operation
(2) 131-8011111410 .................... ijihri(jjii'riririi ......... 1 'f'''(''/i'j'd'j'i'--'-'r''t'iid'n' ...................................... 2 .......
aML (Pc)0:0)real4L
. else no operation b--0-7
CALL a aH10100 aH+14 [(SP)] +(PSW)<7:4>-(PC) 2
aML (SP) 4-(SP)+1
(PC)<10:0> +a
(PC)411y e(0BF) ‘1}
(3) 1111 ............................. 10010001111 ........ 80 ...... '('eir)'i-j'i'io''j.'-r1 V_.F_Vlrt------_-'l.VtV.tFt__-r-.l_ 2 -
(PC) -C(SPH411:0y
"ii'E'"iii"''"''''''''" 1100100111 ........ .93. (SP)1-(SP)-1 ___..-.------.'..''".-'.-' 1...: ........... ii .......
(PC) eC(Sp)lC11:0)
(PSU)47:45 +[(SP)]<15:12>
CLR C 10010111 97 (C)e0
........ 1 H
CPL F1 10110101 B5 (F1reNOT(F1) """" 'i'"'"
NOV A , " 11111ppp F8+r (A )e (Rr) r=0~7 1 V
(e) ....... A IGRF ........ 'iii'ii')'i'i)'/'''F'0V'r', .......... (A) 411R1)j”"”"” H- ”1%011 ................... ..1 ,
'MOV ...... A [#1 ......... '00100011” ...... 'ii'"'''')')'''';-')' Tr-ll..-.--------..-.-'-.-.- 2 -
1.1111111. ii t---l--t------'-rr-rrrrl.--_
C 110v._..1_.R.r.._._1_\ ........... 11111111111]:1111111.]111.111.1111.......Z......,-...... ....r.=.0:7 __1,
o MOV Mir, A 1010000r A0+r [(Rr)]e( A) r=0,1 1
J, Mo0”“'11y#1 .......... 10 1 11r'bE" 081k ...... 1RF)#1 ....................... 'h¥0li ....................... .2 n
5 ................................... .1..1111..11.1........1.1 w-_-r-tIll.----"-'-''''''''-'"-'.--
t, MOV @Rr,#1 1011000r 80+r C(Rr')Y-i r=0.1 2
m . iiiiiiii ii __________
E 001 ....... 1.130 ........ 11000111" "C7' ”1AjML1Psw) ................................................ 1. 1
w M00” ”RSWIA ........... "iiiriijii''1'''''''''dj'' ‘1bsw5';11 'rr-lr-FTF-VIP-PP.-" ..1.-“
C' x01::::i:Ai;:1iriii:iijitiij 1111:1113:21111:: :1'1'1“4»“<'R1>“i:':iiii:i:1:i::j;:;:;;:'.::r"=i'c:+1;:i:i:jiij'ii'::::::iiii“ .11
E XCH A,@RP 0010000r 20+r (A) I-tu. (RP) r=0,1 1
x0H0‘”AXORr '"'i)'di'i'0jiirr"':i'd'i'r', "1A)<3;0>«+[1Rr)<3 0>] """"" "1 -
iiiji/)Ciii'/',jx ....... 1001000'h"'00¥} ..... EXTf1thj ............................ h=0l1 ........................ .11
MOVX””AféRr ___-___.-. 1000000} ”0011"" 1A5 #5111 (ii/l. j ........... r=011 .1
'kii/i'''h,''i'/i'" T i0iikiri1 . A3' '1A) +PRQ[( (PC) <11: 8> (A)j' ___.. 1'
"ds/slr',''''''''""'''"')')'')"'''"'''?'':'."'''))" i-joiibt''(''ie)''t'i'iy.' 011 (A)j """"""" 1
(2) '.... Branchlnstruction (3) -... Subroutinelnstruction 010989
(4) ..... Flag Instruction
MCU48-9
TOSHIBA TMP80C48A/35A
List of TLCS-48 Machine Instruction (4/4)
ObjectCode
E Assembler (1st) Flag
'd (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
" 99.9 ....... SJ. ............... 99.999999 ........ Ir..,... 1.99.909). V-------..-------......----- l .......
9 .999 ....... 9.3.9 ............... 99999999 - 92 .1999999.) .V.F-.--.-F.--F-r-------- l .......
2' STRT T 01010101 55 Start Timer, 1
o ...................................................................................................................................................................................
U STRT CNT 01000101 45 Start Counter' 1
l' 9999’...-9.99.99.11.1199.999999........99..I..$99.9..99999929999999.......-........I...f.1..........-1......II....-1.9T...-
F- EN ......... TENT! ........... 99.1.9919} ........ ilr ....... .E..e1lt...T..iIt.t.r'./fPy.n..t..tr.r..r.l.tftypt. .............................. 1 -
DIS TCNTI 00110101 35 Disable Timer/Counter Interrupt 1
999...: .................... 99999999-. 9.9 ....... .E..elo..lt...E..x.rtsI.n.N..,.l.r1.t.ttT.yp..t, -._.l.l..V_.._....._l* l .......
.999 ........ I .................... fl 9.999999... 19 ....... p.1ti.i1plt...E..x.1tr.r.1N....r..rrtery.y..p..t. Pl''''."''''.'....-..-. l .......
G fill.-..,.....??.?. ............... 999999.99 ........ 99 ....... 999.139 .P.P_Fi_P.Pl.VFF_rVFl_..VlF_PV.__F.VPP._.VF.PlVtl. l .......
t 999......999 ............... 99.999999 ........ 99 ....... (991:9 '_-----------.-----''....---- l .......
g 9.99 ....... !f!l?...,.......,..,.1.1.1p..011.1. ........ 9.9 ....... <.99..F..>.-:..9 P----------.-.-......------ l .......
u .999 ....... .999 ............... 1.111p1l1_.f..1...._.(.p.il..F.1t.1. V.........-...-.-.-..-..--....--.-.--- l .......
.9910 ..... 99.9. ............... 9.1.9.9999.9......7.9 ....... Ii.n..t.s,lo.ltf..l.tyA.9r1,p.y..t....opIo. ......................................... l .......
HALT 00000001 01 Halt 1
(5) NOP 00000000 00 no operation 1
(5) ..... Other 020989
MCU48-10
TOSHIBA TMP80C48A/35A
4. ELECTRICALCHARACTERISTICS
4.1 Absolute Maximum Ratings
TMP80C48AP/C3SAP/C48AU
SYMBOL ITEM RATING
Vcc Vcc Supply Voltage (with respect to GND Nss)) - 0.5V to + 7V
VINA lnputVoltage(Except EA) -0SV to VCC+0.5
VINB Input Voltage(On|y EA) -0.5V to 13V
Po Power Dissipation (Ta = 85°C) 250mW
TSOLDER Soldering Temperature (Soldering Time 10 sec) 260°C
TSTG Storage Temperatu re - 65°C to 150°C
TopR Operating Temperature - 40°C to 85°C
4.2 DC Characteristics
TM P80C48AP/C35AP/C48AU
TopR = - 40°C to 85°C, Vcc = f 5V t 10%, l/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage -
VIL (Except XTALI,XTAL2,RESET) - 0.5 0.8 V
Input Low Voltage -
VIL1 (XTAL1, XEALL RESET) --0.5 0.6 V
Input Hig Voltage - -
VIH Except X'LAL1, XTAL2, RESET, S) 2.2 Vcc V
Input Hig Voltage - 0.7 x -
VI HI (XTAL1, XTAL2, RESET, PS) Vcc Vcc V
Output Low Voltage - _ -
VOL (gite/,'tt'r'g)jl1/gl'ae-e''27) lOL=1.6mA 0.45 v
u pu ow o age - - -
VOL1 (l'iid,1t7il2/'g), IOL =1.2mA 0.45 v
utput I9 0 tage - - - -
VOH11 gxgep: ',.'/t/,'1ja''titP) 1OH= 1.6mA V2.4 V
upu lg 0 age -- cc- - -
VOH12 (Excepth-En. on-P27) IOH - 400PA 0.8 V
Output Hig Voltage - - - -
VOH21 (lr1,ii,''u1t7r,r',g/'/2g)t IOH - 50PA V2.4 V
utput :9 0 age _ - cc - - _
VOH22 (20u-'t'igs'?t','ye) IOH - 25PA 0.8 V
npu_t ea grent - -
ILI (T1, INT, EA, PS) N/srl-SN/INST/cc t10 pA
ILI1 I(gg‘ugELseéaTl; Current VsrSVINSVcc - - -50 pA
Input LeakCurrent V55+0.45VSVIN - - -
ILI2 P10-P17, P20-P27) S Vcc 500 PA
ILO Output Leak Current(BUS,To) Vsrr0.45VSVlN - - +10 A
(Hiqh impedance condition) s Vcc - ll
ICC1 Norma] Vcc--. 5V, - - 10
Vcc Supply operation fXTAL=5MHZ mA
Current VIH =Vcc-0.2V - -
ICCH1 HALT Mode VIL=0.2V 2.5
Normal Vcc= W, - -
ICC2 Vcc Supply operation fxTAL=11MHz 15 mA
ICCH2 Current HALT Mode 3:5:556‘ 0.2V - - 4.0
MCU48-11
TOSHIBA
TMP80C48A/35A
4.3 AC Charactristics
TMP80C48AP/C35AP/C48AU
TOPR = - 40°C to 85°C, Vcc = + 5V , 10%, vss = 0V, unless otherwise noted.
SYMBOL PARAM ETER TEST CONDITION f (t) UNIT
MIN. MAX.
.t Clock Period Note 2 1/xtal f 90.9 1000 ns
tLL ALE Pulse Width 3.5t - 170 150 - ns
tAL Address SetupTime (ALE) 2t- 110 70 - ns
ttA Address Hold Time (ALE) CL = 20pF t - 40 50 - ns
Control Pulse Width
tcc; (km, Wm) 7.5t - 200 480 - ns
Control Pulse Width
tcc2 (W) tit - 200 350 - ns
Data Setup Time -
tow (W) 6.5t 200 390 ns
Data Hold Time
two (W) CL_20pF t-50 40 - ns
Data Hold Time
tDR (i1B,P7;tiri) CL_20pF I.5t-30 0 110 ns
tRD1 Datallput Read Time 5.5t -120 - 375 ns
Data Input Read Time -
tRD2 (PSEN) 4t 120 240 ns
Address Setup Time
wa (VIR) 5t - 150 300 - ns
tADI Add-EES Setup Time 10t - 170 - 730 ns
Add ress Setup Time .
tAD2 (W) 7t 170 460 ns
Add ress Float Time
tAFc1 (W, VTR) CL - 20pF 2t - 40 140 - ns
Address Float Time
tAFC2 (m) CL=20PF 0.5t-40 1O - ns
ALE to Control Time
tLApc1 (RB, WTi) 3t - 75 200 - ns
ALE to Control Time
tLAFC2 (W) 1.5t - 75 60 - ns
Control to ALE Time
tcp; (W, vrm, PROG) t - 65 25 - ns
Control to ALE Time
MCU48-12
TOSHIBA TMP80C48A/35A
AC CHARACTRISTICS CONTINUE .
TopR = - 40 °C to 85 © ,Vcc = + 5 i 10%, I/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f(t) UNIT
MIN. MAX.
Port Control Setup Time
tcp (PROG) 1.5t 80 50 ns
Port Control Hold Time
tpc (FROG) t 260 100 ns
Port2 Input Data SetupTime - -
tpR (PROG) 8.5t 120 650 ns
Port 2 Input Data Hold Time
th (PROG) 1.5t 0 140 ns
Port 2 Output Data Setup Time
t 6 -29 250 -
DP (PROG) t 0 ns
Port 2 Output Data Hold Time
. - 4 -
tpD (PROG) 1 St 90 0 ns
tpp PROG Pulse Width 10.5t-250 700 - ns
Port 2 HO Data Setup Time
tpL (ALE) At 200 60 ns
tLp Port 2 l/O Data Hold Time (ALE) 0.5t - 3O 15 - ns
tpv Port Output Delay Time (ALE) 4.5t+ 100 - 510 ns
topRR To Clock Period 3t 270 - ns
tcy Cycle Time 15t 1.36 15.0 ps
Note : 1. Control Output CL = 80pF. BUS Output CL= 150pF.
2. The f(t) assumes 50% duty cycle on XTAL1 and XTAL2.
The Max. Clock frequency is llMHz. and the Min. Clock frequency is lMHz.
MCU48-13
TOSHIBA TMP80C48A/35A
4.4 Absolute Maximum Ratings
TM P80C48AP-6/TMP80C35AP-6/TMP80C48AU-6
SYMBOL ITEM RATING
Vcc Vcc Supply Voltage (with respect to GND Nss)) - 0.5V to + 7V
VINA InputVoltage(Except EA) -0SV to Vcc+0.5V
VINB Input Voltage (Only EA) -0.5V to 13V
Po Power Dissipation (Ta = 85°C) 250mW
TSQLDER Soldering Temperature (Soldering Time 10 sec) 260°C
TSTG Storage Temperature - 65''C to 150°C
TopR Operating Temperature - 40°C to 85°C
4.5 DC Characteristics (I)
TMP80C48AP-6/TMP80C35AP-6/TM P80C48AU-6 .
TOPR = - 40°C to 85°C, Vcc = + 5V , 10%, I/ss = 0V, unless otherwise noted
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
VIL Input Low Voltage -0.5 - 0.8 V
VIH 12:22; itlff,tjgeu, W, is) 2.2 - Vcc V
VIH1 (t/,'yui',",itig1t,tl-'ryi-i-,v,-s) 5:. - Vcc v
VOL (c322: sL,:,"C',"7',lt,,i'j',-e,,27) IOL = 1.6mA - - 0.45 v
VOL1 (te,u1t,L;"gl/,tt)a9e IOL = 1.2mA - - 0.45 v
VOHH tef, 1it),11teC27) IOH = =1.6mA 2.4 - - v
VOH12 2:33:12? "tll/tta" IOH= -400PA Ich- - - v
VOH21 fl:)'',),',,'",,''')),,'),?"" IOH = - 50PA 2.4 - - v
VOH22 jt,t,u,t,,"jtl,1,/2tt"e IOH = - 25PA V35 - - v
ILI _ri',',ul-),1irts,c-)-,1-,-r,-)rent Vss s VIN s Vcc - - t 10 PA
fLll 1-tu#i-,eEa,k) Current I/ss s VIN E Vcc - - - 50 PA
.4 vs VIN
ILI2 (l/cf/tit/tCi'" :32.“ - - -500 PA
ILO 001p0t Leak Current(00S,To) V55+0.45V§VIN - - t10 PA
(High impedance condition) SVcc
ICC1 Vcc Supply ygégiilon X3: :ZIMHZ - - 10 mA
ICCH1 Current HALT Mode a:l-YSVOIV - - 2.5
MCU48-14
TOSHIBA TMP80C48A/35A
4.6 DC Characteristics (II)
TM P80C48AP-6/TM P80C35AP-6/TM P80C48AU-6 .
TopR = - 40"C to 85°C, Vcc = + 5V i 20%, vss = 0V, unless otherwise noted
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
VIL I L V l 0 5 - 0.5 V
nput ow o tage - . x Vcc
Input High Voltage 0.5
VIH --_--- w - V V
(Except XTAL1, XTAL2, RESET, PS) x Vcc CC
Input High Voltage 0.7
VIH1 - - - V V
(XTAL1,XTAL2, RESET, PS) x Vcc CC
Output Low Voltage
VOL IOL:1.6mA - - 0.45 V
(Except P10-P17, on-P27)
Output Low Voltage
VOLI iOL =1.2mA - - 0.45 V
(P10-P17. on-P27)
OutputHigh Voltage Vcc-
I H = -4 A - - V
VOH11 (Except P10-P17, on-P27) O 00p 0.8
Output High Voltage Vcc -
VOH22 IOH = -25 A - - V
(P1o-P17. on-P27) p (h8
Input Leak Current
- - V s VINS V - - 11 A
ILI (T1, INT, EA, PS) ss CC 0 p
Input LeakCurrent < = - - -Vcc
ILH ers, W) Vsrs VINE Vcc 0.1 pA
ILI2 Input LeakCurrent Vss+0.45V§VIN - - -Vcc PA
(P1o-P17. on-P27) s Vcc th01
ILO (1try.t Leak Current (005, To) Vss + 0.45V VIN - - l 10 pA
(High impedance condition) E Vcc
Normal Vcc= 5V,
. - - 1
lCCI Vcc Supply operation fXTAL=6MHZ 0 mA
Current VIH =Vcc-0.2V - -
lCCHI HALT Mode VlL=0.2V 2.5
MCU48-15
TOSHIBA V TMP80C48A/35A
4.7 AC Charactristics
TM P80C48AP-6/T M P80C35AP-6/T M P80C48AU-6 .
TopR = - 40°C to 85°C, Vcc = + 5V , 20%, l/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f (t) UNIT
MIN. MAX.
t Clock Period Note 2 1/xtalf 166.6 1000 ns
tLL ALE Pulse Width 3.5t - 170 410 - ns
tAL Address Setup Time (ALE) 2t - 110 220 - ns
hp Address Hold Time(ALE) CL=20pF t-40 120 - ns
Control Pulse Width
- .__._ 7. - 200 1 50 -
tcc1 (RD, WR) 5t 0 ns
Control Pulse Width
tcc2 (m) 6t - 200 800 - ns
Data Setup Time .
tow (WTi) 6.5t 200 880 ns
Data Hold Time
two (W) CL=20PF t-50 120 - ns
Data Hold Time
tDR (KEVSEN) CL=20PF 1.St-30 0 220 ns
tam Dat1llput Read Time 5.5t - 120 - 800 ns
Data Input Read Time -
mu (m) 4t 120 550 ns
Address Setup Time
tAw (W) St 150 680 ns
tAm ACME” Setup Time 10t - 170 - 1500 ns
Address Setup Time
- - 7 - 1
1AD2 (PSEN) 7t 1 0 000 ns
Address Float Time
tAFCl (W, W) CL - 20pF 2t - 40 290 - ns
Add ress Float Time
tAFC2 (m) CL - 20pF 0.5t - 40 40 - ns
ALE to Control Time
tLAFC1 (E, Thm 3t - 75 420 - ns
ALE to Control Time
- 1. - 7 17 -
tLAFC2 (PSEN) St l 5 ns
Control to ALE Time .
tCA1 (W, m, PROG) t 65 100 ns
Control to ALE Time
tCA2 (W) 4t - 70 590 - ns
MCU48-16
TOSHIBA
TM P80C48A/35A
AC Charactristics (Continue) .
TopR = - 40°C to 85°C, Vcc = + 5V i 20%, l/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f(t) UNIT
MIN. MAX.
Port Control Setup Time
tcp (PROG) 1.5t-80 170 ns
Port Control Hold Time
4 - 26 4 -
tPC (PROG) t 0 00 ns
Port 2 Input Data Setup Time
. - 2 -
tpR (PROG) 8 St 1 0 1290 ns
Port 2 Input Data Hold Time
tpp (PROG) IEt 0 250 ns
Port 2 Output Data Setup
6t- 290 710 -
IDP Time (PROG) ns
Port 2 Output Data Hold Time
tpD (PROG) 1.5t 90 160 ns
tpp PROG Pulse Width 10.5t-250 1500 - ns
Port 2 " Data Setup Time _
tpL (ALE) At 200 460 ns
Port 2 HO Data Hold Time
tLp (ALE) 0.5t - 30 130 ns
tpv PortOutput Delay Time (ALE) 4.5t+100 - 850 ns
tOPRR To Clock Period 3t 500 - ns
tcy CycleTime 15t 2.5 15.0 IIS
Note : 1. Control Output CL=80pF. BUS Output CL=150pF.
2. The f(t) assumes 50% duty cycle on XTAL1 and XTAL2.
The Max. Clock frequency is 6MHz. and the Min. Clock frequency is IMHz.
MCU48-17
TOSHIBA TMP80C48A/35A
4.8 Timing Waveform
A. Instruction Fetch from External Program Memory
in ------
- tcc - - --- tLAFC2 - tCA2 -
tAL =t-hr-c
DBO-7 1jjljijlllfiljht'jfdt ////////M~STW°~ "llollh,
-= tAD2
B. Read from External Data Memory
trAFC1 tCAI- -
l ,___._
- A tc 1 7
RD N c r
tAFc1 --i-- 1mm - - --tDit
DBO_7 ///////////// ADDRESS ffffffffff INPUT DATA
"tADI ----
MCU48-18
TO SHI BA TMP80C48A/35A
C. Write into External Data Memory
trpFty tcal, -
- tow ' -two
7///////////
-uw -----
A_EESRXW/Z ///// OUTPUT DATA
D. Timing of port 2 during Expander Instruction Execution
PORT 1,2
PORT 20-23
PORT 20-23
_/_\____J
-"""""-'"-"-"""""Nc_....v/
i- th - tcal----
PORT l, 2 DATA NEW PORT l, 2 DATA
PORT 20-23
P RT -
005223 CONTROL
PORT OUT PUT DATA
----eF
PORT 20-23
PCH PORT 20-23 PORT
DATA CONTROL
--'----
MCU48-19
TOSHIBA TMP8OC48A/35A
4.9 Stand-By Function
4.9.1 Power Down Mode (l) ... Data Hold Mode in RAM
The operation of oscillation circuit is suspended by setting Pg terminal to low level
afterm terminal has been set to low level. Consequently, all the data in RAM area
can be held in low power consumption.
The minimum hold voltage ofVcc in this mode is 2V.
PE terminal is set to high level to resume oscillation after Vcc has been reset to 5V,
and then -REiE'I? terminal is set to high level, thus, the normal mode is restarted from
the initialize operation (address O).
(1) DC Characteristics
TMP80C48AP/C35AP/C48AU
TMP80C48AP-6/C35AP-6/C48AU-6 : TopR = - 40--85''C , vss = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
VSB1 Standby Voltage (1) 2.0 - 6.0 V
1531 Standby Current (1) Ici: it'.vdll."il/jc - 0.5 10 pA
(2) AC Characteristics
TMP8OC48AP/C35AP/C48AU : Mcc = + 5V , 10%, Mss = 0V
TMP80C48AP-6/C35AP-6/C48AU-6 : Vee = + 5V t 20%, Viii = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
tngR Power Save Hold Time (RESET) 10 - - ps
tPSSR Power Save Setup Time (RESET) 10 - - ms
tVH Vcc Hold Time (F5) 5 - - ps
tvs Vcc Setup Time (P-S) 5 - - ps
Note : tcy=2.5ps (fXTAL=6MHz) 020989
(3) Timing Waveform
--9 - - tvs --))r"""""""'""--""'-"'
-e-- l "
M---------
---F - tPSHR
MCU48-20
TOSHI BA TMP80C48A/35A
4.9.2 Power Down Mode (II) ... ALL Data Hold Mode
The operation of oscillation circuit is suspended by setting P-S terminal to low level
after E terminal has been set to low level. Consequently, all data can be held in low
'power consumption.
The minimum hold voltage of Vcc in this mode is 3V.
pg terminal is set to high level to resume oscillation after Vcc has been reset to 5V,
and then 93 terminal is set to high level, thus, the normal mode is restarted
continuously form the state just before the power down mode (11).
(1) DC Characteristics
TM P80C48AP/C3SAP/C48AU
TM P80C48AP-6/C35AP-6/C48AU-6 2 Tom = - 40 to 85''C ' l/ss = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
VSB2 Standby Voltaagen (2) 3.0 - 6.0 V
Vcc = 5v, VIH = Vcc
[SB2 Standby Current(2) -0.2V, VIL=0.2V - 0.5 10 pA
(2) AC Characteristics
TljRR?4"/fuP/fi/3c53/)lT18/l)ilsAu, 2 ti: :23 i 3832: 32;:33
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
tngR Power Save Hold Time (rs) 10 - - ps
tpSSR Power Save Setup Time (55) 10 - - ms
tVH Vcc Hold Time (P-S) 5 - - ps
tvs Vcc Setup Time (rs) 5 - - ps
Note : tcy=2.5ps (fXTAL=6MHz) 020989
(3) Timing Waveform
_ - - tus
f - tVH
SS ti /
PS - SS -e
--v - tngg tPsss
MCU48-21
TOSHIBA TMP80C48A/35A
4.9.3 HALT MODE
HALT INSTRUCTION
OP code is "01H". HALT INSTRUCTION is an additional instruction to the standard
8048/8049 instruction set.
Entry to HALT MODE
On the execution of HALT INSTRUCTION, TMP80C48A/TMP80C35A enter HALT
Status in HALT MODE
The oscillator continues its operation, however, the internal clocks and internal logic
values just prior to the execution of HALT INSTRUCTION are maintained. Power
consumption in HALT MODE is less than 50% of normal operation. The status of each
pins are described in the following table.
Release from HALT MODE
HALT MODE is released by either of two signals (RESET, INT).
(4.1) RE SET Release Mode : An active RESET input signal causes the normal reset
function. TMP80048A/TMP80035A start the program
at address "OOO H''.
(4.2) I TRelease Mode : An active INT input signal causes the normal
operation.
o In case of interrupt enable mode (EI MODE), TMP80C48A/TMP80C35A
execute the interrupt service routine, after the execution of one instruction which
is located at the next address after HALT INSTRUCTION.
0 In case of interrupt disable mode (DI MODE), TMP80C48A/TMP80C35A
execute normal operation from the next address after HALT INSTRUCTION.
Supply Voltage Range in HALT MODE
The operating supply voltage range and the operating temperature range are same as
in normal operation.
TMP80C48AP/C35AP/C48AU : Vcc = 5 i 10%
TMP80C48AP..6/C35AP-6/C48AU-6 : Vcc = 5 f, 20%
MCU48-22
TOSHIBA
TMP80C48A/35A
4.9.4 Pin Status In Power Down Mode (I) (ll)
PIN NAME STATUS
DBO~DB7
Pur-P17 :2'33111222‘333”
P20-P27
To High Impedance, inputdisable
T1 Inputdisable
XTAL1 High Impedance
XTAL2 Output "High" level
RESET, fiS Input disabled when oscillator is stopped. Pull-up transistors turn off.
IN-T, EA input disabled when oscillator is stopped.
1icvl,mpr,(-)-l-f High Impedance
4.9.5 Pin Status In HALT MODE
C20989
PIN NAME STATUS
DBo--DB7
P10~P17 Values prior to the execution of HALT INSTRUCTION are maintained.
P20--P27
To Status prior to the execution of HALT INSTRUCTION is maintained.
T1 Inputdisable
XTALI, XTAL2
Continue oscillation
RESET, iNT Inputenabled
Ts, EA Inputdisabled
PROG, PS-EN Output High level
ALE Output "Low" Level
MCU48-23
TOSHIBA TMP80C48A/35A
5. OSCILLATOR
QUARTZ CRYSTAL
f=1MHzto 4MHz :C1=C2=30pF XTAL,
f=4MHzto11MHz 2C1=C2=20pF C1 JT
CERAMIC RESONATOR 3
f=1MHzto3MHz :C1=C2=100pF C2 -l.- XTAL2
f=3MHzto11MHz :C1=C2=30PF JT
"f, 020989
6. TYPICAL CHARACTERISTICS
Vcc = 5V, Ta = 25°C, unless otherwise noted.
3 .,ev,-w'''''''i"
5 10 15 fXTAL(MHZ)
VCC‘fMAX. TYPICAL CURVE
5 10 15 fXTAL(MHZ)
fXTAL-lcc TYPICAL CURVE
0 1 2 3 4 5 VOUT (V)
VOUT‘IOL TYPICAL CURVE
1 2 3 4 s VOUTM
-..--"
Vcyur-loH TYPICAL CURVE
(PORT 1, 2)
MCU48-24
TOSH I BA TMP80C48A/35A
tRESET
(ms) 1 2 3 4 5 VOUT (V)
30 ",,,,,/'"
20 -10 //
-15 -..--'" -'"'
0.01 0.02 0.03 0.06 0.1 0.2 0.3 CRESET |0H
(pF) (mA)
CRESET-tRssET TYPICAL CURVE VouT-IOH TYPICAL CURVE
(DB, CONTROL)
7. OUTLINE DRAWING
7.1 Outline Drawing For TMP80C48AP/-6, TMP80C35AP/-6
(DIP: Dual Inline Package)
DlP40-P-600
Unit: mm
r-lr-tr-IC-II-Tr-Ir-Ir-Ironic'?)]''?'-'.-?'-.)'-, -
I-ii-IL..';'-.''-'.-.,';;;..-.];;;;;,-:;.-,; -
%~25 —0 05
l l "i rn
tir-tyr-
m_v' m.
fir-h-Jn.'
14+01 os+01 G m
1.22TYP - _ _ - .
Note : 1. This dimension is measured at the center ofbending point ofleads.
2. Each lead pitch is 2.54mm, and all the leads are located within ic0.25mm from their theoritical
positions with respect to No. 1 and No.401eads.
MCU48-25
TOSHIBA TMP80C48A/35A
7.2 Outline Drawing For TMP8OC48AU/-6
(Micro Flat Package)
QFP44-P-1010A
Unit: mm
10.0:0.2
Fslrs" Ct
N otes:
13.8:0.3
1. The above dimensions don't include the burr of package and the residue of tie-bar cut.
The burr of package and the residue of tie-bar cut should be 0.15 mm (Max.)
2. Applied to the lead flat portion.
MCU48-26
TOSH I BA TMP80C49A/39A
CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)
TM P80C49AP /TM P80C49AP- 6
TM P80C39AP /TMP80C39AP- 6
TM P80C49AU/TMP8OC49AU-6
1. GENERAL DESCRIPTION AND FEATURES
The TMP80C49A is a single chip microcomputer fabricated in Silicon Gate CMOS
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been included in a single
chip; an 8-bit CPU, 128X8 RAM data memory, 2KX8 ROM program memory, 27 lk)
lines and an 8-bit timer/event counter.
The TMP80C49A is particularly efficient as a controller. It has extensive bit handling
capability as well as facilities for both binary and BCD arithmetic.
The TMP80C39A/-6 is the equivalent of a TMP80C49AI-6 without ROM program
memory on chip. By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80C49AP/-6 and TMP80C39AP/-6 are in a standard Dual Inline Package.
The TMP80C49AUl-6 is in a 44-pin Micro Flat Package.
FEATURES
It TMP80C49AP/TMP8OC39AP/TMP80049AU
1.36ps Instruction Cycle Time -40''C to 85°C, 5V i 10%
o TMP80C49AP-6/TMP80C39AP-6/TMP80C49AU-6
2.5ps Instruction Cycle Time - 40°C to 85°C, 5V i 20%
0 Software Upward Compatible with TMP8049AP/INTEL's 8049
o 2KX8masked ROM/128X8RAM
tt Low Power
10mA MAX. in Normal Operation (VCC = 5V, fXTAL = 6MHz)
10pA MAX. in Power Down Mode (VCC = 5V, fXTAL : DC)
0 Power Down Mode (Stand-by Mode)
0 Halt Mode (Idle Mode)
MCU48-27
TOSHIBA TMP80C49A/39A
2. PIN CONNECTIONS AND PIN FUNCTIONS
2.1 Pin Connections (Top View)
To Cl U 403Vcc(+5V)
XTAL1 Lil 39 ilTI
XTAL2 C3 38 3 P27
RESET C4 37 , P26
g E 5 36 l P25
W126 35 l P24
EA C7 34 1 P17
my t 8 33 l P15
W119 32 Cl P15
VV_RE10 31 1 P14
ALE C 11 30 il P13
030 C12 29 1 P12
DB1 (13 28 i] P11
Dh t 14 27 Cl P10
033 E 15 26 1 pr;
DB4 E 16 25 i] PROG
DBs E 17 24 1 P23
DB6 t 18 23 1 P22
DB7 t 19 22 1 P21
l/ss E20 21 J P20 040989
Figure 2.1(1) DIP Pin Connections
rr~~olumu1 -
agaoagtfa-l WQ alum
no iiiiat/iiesy-v,
D84 Wfrft
D85 NC
D36 XTAL2
DB7 XTAL,
Vss To
P20 Vcc
Figure 2.1 (2) Micro Flat Package Pin Connections
MCU48-28
TOSHIBA TMP80C49A/39A
2.2 Pin Names And Pin Description
0 VSS (Power Supply)
Circuit GND potential
o Vcc (Power Supply)
+ 5V during operation
0 P-S (Input)
The control signal for the power saving at the power down mode (Active Low)
0 PROG (Output)
Output strobe for the TMP82C43P I/O expander.
o P10-P17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup= 50KQ).
o on-P27 (Input/Output) Port 2
8-bit quasi-bidirectional port (Internal Pullup= 50KQ).
P20-P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the TMP82C43P.
0 DBo-DB7 (Input/Output, Tri-State)
True bidirectional port which can be written or read synchronously using the
RD, WR strobes. The port can also be statically latched. Contains the 8 low order
program counter bits during an external program.memory fetch, and receives the
addressed instruction under the control of m.
Also contains the address and data during an external RAM data store
instruction, under control of ALE, RB, and WK
It To (Input/O utput)
Input pin testable using the conditional transfer instructions J T0 and J NTO. T0
can be designated as a clock output using ENTO CLK instruction.
0 T1 (Input)
Input pin testable using the JTl and JNTl instruction. Can be designated the
event counter input using the timer/STRT CNT instruction.
0 IN-T (Input)
External interrupt input. Initiates an interrupt ifinterrupt is enabled.
Interrupt is disabled after a reset. Also testable with conditionaljump instruction.
(Active low)
MCU48-29
TOSHI BA TMP80C49A/39A
0 m (Output)
Output strobe activated during a Bus read. Can be used to enable data onto the
Bus from an external device. Used as a Read Strobe to External Data Memory
(Active Low).
0 WR (Output)
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
0 RESET (Input)
Active Low signal which is used to initialize the Processor. Also used during the
power down mode.
0 ALE (Output)
Address Latch Enable. This signal occurs once during each cycle and is useful
as a clock output. The negative edge of ALE strobes address into external data and
program memory.
0 PSEN (Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
0 gg (Input)
Single step input can be used in conjunction with ALE to "single step" processor
through each instruction when W? is low the CPU is placed into a wait state after it
has completed the instruction being executed. Also used during the power down
0 EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing and
program verification. (Active High)
0 XTAL 1 (Input)
One side of crystal input for internal oscillator. Also input for external source.
0 XTAL 2 (Input)
Other side of crystal input.
MCU48-30
TOSHIBA TMP80C49A/39A
2.3 Block Diagram
DBO-DB, P1o-P17 on-P27
W PORTOBUFFER PORT1BUFFER PORT2BUFFER
(2) (1) 4
OUTPUT OUTPUT OUTPUT MASK ROM
LATCH LATCH LATCH
f /1 5
XTAL "s Cs 2K x 8
1/32 1 Hm? (PROGRAM AREA)
INTERRUPT TIMER/
CIR'CUIT - COUNTER
I I C: /\
ACCUMU- TEMPO-
LATOR RARY REG FLAGS
! RAM ADDRESS
INSTRUC- PSW REGISTER
ACCUMULA- RAM
TOR LATCH TION I-r,
REGISTER/ TIMER 7 128 x 8
DECODER FLAG 1/
Fo F1 lCARRY
ACCUMULATOR Sl/ll/fl)]))
BIT TEST J
To T, Wt
POWER f 1 f
SAVE p-s
XTAL1 XTAL2 RESET m‘T EA TT; ALE PSEN AD vim PROG
'c----'' r- _ -1 o. m Lu W” n:
m D n. < m Lu m Lu m W Lu
0 o. D a m _ F- Lu I m 0 m Cy Lu
F- a o: c: UJ U m n: L) O o: < O a m
4 - a: F- m u: Lu a _ cc _ - a: < 0
.4 m Lu 2) F- a _, U-I t2 < F- w < F- o. n:
.4 _ _ '- o. x CI Lu .1 < -1 vs Cy v1 x _
- D Lu 2 2 Lu < m 0 if W m
U n. Uh - - Z
w E : a 5
CL 040939
Note 1 : The lower order 4 bit of port 2 output latch are used also for input/output operations
with the I/O expander.
Note 2 : The output latch of port 0 is also used for address output.
Figure 2.3 Block Diagram
MCU48-31
TOSHIBA TMP80C49A/39A
3. MACHINE INSTRUCTION
The following symbols and codes are used in the list of machine instruction.
Symbol Meaning
Rr' Working register (0Pp l/O portaddress P; (0JBb Branch instruction in accordance with bit content(b) of operand
aH Higherorder3 bits ofa
aM Mediumorder4bits ofa
aL Lowerorder4bits ofa
aML Mediumorderorlowerorder8bits ofa
(a) Content ofa
C (a) , Content of RAM addressed by a
EXT[ (a) I Content of external RAM addressed by a
PROC (a) , Content of ROM addressed by a
atm), Value at bit position m of a
a Value atbit position mtonofa
ar-b Store a into b
tie-rl, Exchangeaforb
Connection
A Icomplement ofa
a+b a plus b (Addition)
a-b a minus b (Subtraction)
a/\b LogicalANDforaand b
a\/b Logical OR for a and b
aVb Exclusive OR for a and b
a=b a is equal to b
aOb a is notequaftob
(a) BCD Converted value of accumulator
MCU48-32
TOSHIBA TMP80C49A/39A
List of TLCS-48 Machine Instruction (1/4)
ObjectCode
E Assembler (1st) Flag
'ie (2nd) Function Cycle
_ Mnemonic . C,AC
Bin Hex
.399 ....... A...z....R.'.". ........ I)l1?1ry.rrr,.i8ltr.' ....... m(/.r..)t(.l)..).t.H.r.) ........................ FfFH ................ 1...; ............ l -
APP ....... 5.1.9.3.? ........ .il1.1p,.0fi.lr...plltrr.' ....... (.5.).‘.‘.(..‘.‘).f[.(.3.'.‘.).] ................... ???r} ............... Ct ............ l .......
ADD A,#i 00000011 03 (A)e(A)+i tt
iiiiiiii ii
.'/ijo'i'irr'.'ii.".'.',riii.'.".' ..... iii'iriF/rjiiii, _______ ('iiji-jjijijj'irjij'd')" ............ Eébli -.__.Fl-F_r._ t ............ 1 .......
.éiibféifAIi}iéBjEI...I1.1.1.1090}...10%....i(AiiéiéﬁtKiéﬁiijfftiicifilﬂIi.i%§.§jiffjiiiiii.ifjifijilijf}.Ifliiiiffi
A000 A ,#1 00010011 13 (A)HA)+i+(c) tt 2
iiiiiiii ii
71M ....... A:";""r'1"r'"" .... iiiiiriFr/" "iii-Tir'" (irjj-(iyjr/rrijij, -..e-_...._._.. F9021 .................................... 1 -
jiiit ....... 'r''Jiiir',' ....... ijufiijiiif/''' 505913“ j'h'j'i-'ljC/'il'l'ii'rj'] -.--t- #011 .................................... 1 .......
3 AM ....... Amik'i ........... ijiiiiiiiirl' ........ 5.3. ....... 'iji'ii-TiC/'i'i' .F....__l._.__.V.V....VFP.P_VVP..V.V.VVrP'.''PP._'Pt.-r- ii -
C ............... iiiiiiii ii .....................................................
; §??LI....L.I1..§IRIE ........ iii.iijii(rrrr. 113.116.... 1.115(1)-MW)..-.j.......i.r.1i0:7j§if--. .jQIjIQIII. '..r.rir..r,
1 URL A ,0Rr 0100000r 40+r (A)e(A) v[(Rr)] r=0,1 1
C, 'diiL' ....... A"”,"#'1 ........... (iiiiiiiiliii ........ .43. ....... 'dij'i-rij'''i(/''o'' Pll__V_..r._-V..l.V.P_V.P...._VN''.''FP'"'."lt-- ii -
E iiiiiiii ii
t MI, ....... 9...:93P ........ 1yl.11)flllr..,ll?.tt ....... (./.r.)t(/)1eC.(.!.1.r.r)..) .............. ???,2} ................................... l -
- XRL A,#1 11010011 03 (A)<-(A)V1' 2
2 .. iiiiiiii ii ______
E ENE...Ii.?¥fliiiiiiff..f.13.00.10.111...fifiiifiiii.?1.)i€<.é)f+.1]III...f...IITiff...i'iiijﬁfff'fjfl”fi..f...jfi...1jffﬁi
3 DEC A 00000111 07 (A)e(A)-1 1
[t .th - a .-.-__ "iiriijij'i'r1' ........ ij ....... (AS'i-b 'me..-'--.--------------.--.-.....'. .1. -
q ”C'P'L ....... A ._v_.OP..P'''_'F 00110111 ........ ij ______ '(hFiidiljij' --t.lel_V._..._V_.VV_.VF.V__P_P.V'e'P''"'''-'-.- i .......
RL A 11100111 E7 (A) <-(A) 1
(A)<0> e-(A)s(7y n=0~6 -
'R'L'é ....... 'ii'''""''"'''''''))"';'''"''"'''''?'', ....... '(')i'')k'iih''r'dijijG'y' ....................................... t ................ i' .......
(0)e(A)47)
(A)40Y ¢-(C) n--0-.6
1'21: ......... A .................... ijri'riiri"''ij"(''dy'G')r'dl''iijk''n''i'i'jr' .............. 11%0';6 ................................... i' .......
' (A)<7> t(Nf!l?. _ V
iiiie ..--. A .................... 01100111 ........ iii''''' 'rjijdn''y''''i-''(jijk"r/ii'jr' P'----..---.-.- t ................ i' 1111111
(C)(~(A)
(A)<7> 4-(C) n--0-6
IN ..A...’ Pp .. 000010pp 08+p (AMER) _.__.F_.__l_.___q_qV.q.. ??.?:2 ............ 3.. T
ajiif" PpLWA ......... ijiii''1''fddij'''iiViCjjii's'") e(A) P=1,2 ........ ' __.
o 'jiiiL'''''''ioio'yii' ........... "lair,)")')"""'':)')'-;-')'''"'')')''')')'''"-')'''''')')'): ....................... HIE _._FVPP___V_r_rlr-_ g .......
b. iiiiiiii ii
'd‘réL""""r'>'p”,'#1 ........... 'iijiiij'iiihCiiiiii] - "(jsijl'i'iiijji/i ....................... #112. ................................... i .......
iiiiiiii ii
MCU48-33
TOSHIBA TMP80C49A/39A
List of TLCS-48 Machine Instruction (2/4)
ObjectCode
E Assembler (1st) Flag
'd . (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
INS. ....... /)...,....f.l.t.lf. ...... 99.901000 08 (ANBUS) 2
OUTL BUS, A ii'iiiii'iirfij"iii" (BUS)<~(AC) ..._rr_l__F_._Fl.P.Pl___--_V_-_Vr__PV. ii .......
jiiiL ..... BU$#1'10011000 ........ 08 ....... '('ii'tj'iF(''iiij'i'r7Gi 'l-tm-l-Fl-ll-tFl.-.-.- i .......
iiiiiiii ii
0 URL ..... iiijiyij .......... 10001000 ........ 08 ....... (BUS)<~(BUS)V1 .P..l.l_P.Pl.lV_Pl_PVll.. ii ......
\ iiiiiiii ii . _
- .11.be - 'Am'Pp. ........ 000011pp 00% ....... '('hj'diriri-'i'ip'j' ................... is"--UL''7' ................................... ii .......
..................... (Nfri.f?_.tt.l.._.._._, _ -P.V....8eet ., _
MQWIZfP.pg..A ....... 'p'j.iiiiiiiir". .3515jo .'<.’F?b.)-.t(.4\..)$§.s.9.>. ................... iii-ij.))'..').".'..''.]'.."..". '..'.'.r'.r.''.,'.'.'.'r, 'I"".2I...”
ANLD P.p......A.iI...Ifidéi'i‘i'pbi'960"" (Pp) t(fy)./).(/))fA.fl? - ly-Pr:? """"""""" ii ..
'diirir''jiif, AI . 16061155 _ 0044b ....... "('isi'Cdiiiijjr/(jijk':irdS' 'p;4;.7 ................................. ii .......
Jr/f Rp 00011rrr 18+p (RP) e(Rc)+1 p=0-7 1
(1) iiie ..... iiii/ 'mr_rwmF_.w.-r._m 'iiiiirdiiifriiiii, - ijii/jj"'ij'jii/jjiri .............. Egon P'..-''''''-"''"''--. 1 .......
'[VJ'ECWWRHr ._.rWe_...V 'iiiiii'i'//'/''"'eii'i,'" '?iiF'i'V-'i'ii'/'j'-''r'''''''''''''''"ruiir7' .r..q.i.F__...l.V.-W- .1. ......
JMP a aH00100 aH+4 (PC)<10:0> E-a 2
aML (PC)<11> +(DBF)
'J'Mbbmé'li ................... "iiiiiijirii" ....... iii" ”(IPCH)? 'ii'ii'yi-iiiiiir'iia''c'jkri':''iir'riij'j .................... ii .......
Ei'riCiir',% ........... ri'i'iiir'/''/'"''E'ii.'i.'i, ....... '('ii'pr'd('ii'/')'"-'-'i''"''"''''''F--'irr7' ._.....l...-._F.l- .2 .......
aML if(Rr') ==0then(PC)<7:0><-aML
else no operation
.jc.........é .................... '1rfii)''ii'ii'"ii'i ....... "i''i'ii:'j"--i''tjar(j'e)k'j"TiN'-'diiL' -_..rwr.r.m_r'''-''._.'w.-.m.w'rrrrmrr_m i: ......
aML else no operation
3 'JNCIIU-ma' -__-__..__FPr__.. 11100110.”WHE'GWH"1'1‘('-.C”)N=H0mfnén("l5ci)2790514‘51‘11 ----t_PP_lPt-t-t- ji -
J, ................................. aML 91.59. 99...??? F6391?" .......................
y, Ji a . - 110040110 ........ 'e'iCit"i'j(')''i'iy 'tjar(j'oir)2'j':"'ij'y"'Cdiir .............................. ii .......
z .--l---..-P-r- ?ML. ........................ 1l.s.i.t..yr/opt,et.1?..n. w--.---.-.....--------
m JNZ a 10010110 96 1f(A)=0 then(PC)<7:0>4-aML 2
E aML else no operation
I ",jiif''''"'i', .................... ijiiriijiiij ........ ii's''''''''i''t''"''T'ij'--''r''iii'G'('ie)'ki.''ijri-uir --V...l.._.W_F_l.-_ i' .......
I' ........................................... Ill ........................ 1l1tr.1trt.optr.1aA1t.y] _-r------..------.---.
m JNTO a 00100110 26 if T0=0 then(P0)0:(DeaNL 2
5 aML else no operation
'jii''''''''d .................... iiiiiiijiiij ........ 56 ....... 'i't''''ir-rfiGr'i'(j'e)'l:i:'ij''Sla'ii'- ......................................... ii .......
. .................................... aML else nn operation . _
Jiiir' a 010-00110. ........ 46 '"irir--'f'tiaiiie)k'r:'iirddiii', ....................................... ii .......
. ................................ aML e1se no operation _..
JFO a 16116116 ___.- iii" "i'r)j'--iirarje)'i:'r."ijy'diiiL """""""""""""""""""" ii """"
lllllll aML else no operation
0151 ..... a .................. 01110-110 ........ 76...... "Ort'''')'',--''.':'.';''':'')"?''?'''..')"')';'-';')'', ......................................... ji .......
______________ aML else no operation
JTF .. .a ................. 00010-1110“ "iii''" "'irir--i'iia'/('irtjt'j''/ii"y'laiL' ......................................... ji .......
aML else no operation
(1) ..... Register Instruction
MCU48-34
TO S H I BA TMP80C49A/39A
List of TLCS-48 Machine Instruction (3/4)
ObjectCode
E Assembler (1st) Flag
'd . (2nd) Function Cycle
- Mnemomc . C,AC
Bin Hex
JNI a 10000110 86 if INT =0 then(PC)<7:0>1-aML 2
........................................ MI, 9‘5?..[‘9..9.P_?F§P.".9.’.‘..................._........._.. ___F.____v___.
(2) JBb a ijLtriiiir1iCtr+'ri'"i''t' (A)aNL (Pc)tr.0yeaNL
else no operation b--0-7
CALL a aH10100 aH+14 [(SP)]1-(PSW)<7:4>-(PC) 2
aML (SP) +(SP)+1
(PC)<10:0> Fa
..rr.w.rrt.rW.__..._mr._rm..__.r...w_wwr_._w.wrwwer._r.F_rtF._s..r.rrrr-wt._ ( '.'f.).f11?.t(p.frFr.,._...,....,.....,...,
(3) RET 10000011 P ii" (SP)+(SP)-1 2
(PC) +[(SP)]<11:0> ________
'iii'iii ........................... 10010011 ........ iii" "('iir)'ir(''i'ii')c'1 t_-r-_-_---...-.--.-- Ft ......... ii .. _
(PC) er(SP)yC11:0)
(PSU)47:4y -r(SP)YC15:12y
919......9 .................... 199191.11 ........ 9.7. - . ...(..C...).f9 -._._-.V_V...lV__.P_llll__e_e_e__e_e_______ 1 -
991......9 ............... 1.9190111. .A7 ..(C.)999..T..<.9) ............................................................. 1....
(4) _i'ij.ir.r..tj.i,'r.'.'.'..r. ...... 1999919195900 ....
991.-....99 .................. 19.919191 ........ 9.9.... ....(.f.9.)...f.'.“.9T.(..F.9). -r.--t-l.-.tr...l._Pl-l..VP_. 1 .......
919......91 .................. 19199191 ...... 99 ,..<91>.,.r9 _---------------.-.--.---. 1 .......
CPL F1 10110101 "35"" '(11) H20T(FI) 1
MOV A ' Rp 11111ppp F8+r (A)1-(Rr) P--0-7 1
MOVP3 A,0A 11100011 E3 (A ))w'i12,li)r(-'i'ir))-f:-11-11f., 011. (A)] 1
(2) ..... Branch Instruction (3) ..... Subroutine Instruction 020989
(4) ----- Flag Instruction
MCU48-35
TOSHIBA TMP80C49A/39A
List of TLCS-48 Machine Instruction (4/4)
ObjectCode
E Assembler (1st) Flag
'/d (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
" ly ...... 6.2.? _______________ 91.999919 ........ 42.12.):118), _.-----------------.-. l .......
tll 119v ....... T..,?. ............... 9.1199919 ........ lit....).?.).!-.!.!)..) VF----------.--.-.......------ 1 -
Z STRT T 01010101 55 Start Timer 1
o .................................................................................................................................................................................
Q) STRT CNT 01000101 45 Start Counter 1
E iSiéIFZ’IIfCNTIIIII0.111001101-ilijiit‘éﬁéiiijii$101}IiiirﬁéjﬁkﬁééébﬁéfﬁIIIZIIIIIIIL1ijIiQQIQLI-IifL'jTiiIiT”
: .EN....-.-T.C.NT.1 ........... 99.199191 ........ 2.5. ....... .E,.relolt..I.iItsI./fty/.nAt.irJ..rrt..e/.ty/,p,.t. .............................. 1 .......
DIS TCNTI 00110101 35 Disab1eT1’mer/Counter‘ Interrupt 1
..E.N........I .................... 1p.p.p.01l1 ........ 9.5. ....... _r.ry.1lo,.lt...E.r.t..tryPr..l1.trrTyp..t. ._.F.Vl_FP''''''''lt-.. 1 .......
915......1 -.lF....-_ 999191.91 ........ lf - [l1qt.trrt.,.E.r..t.?..r.ry.1..l..l.rr11rTy.0. ---tl..F_V-.P_tlt. l -
G §§k...-N.B.9 ............... 11.999191 ........ ??.......(-B-$-)f-9 __-_-t__-__-Ft-Fr-l-r-r-------' _1,
: Ji.E1-..._N.3.,1. ............... 1191.91.91 ........ P5.......(P.3-).‘i.-1 _._Fl9P_...-----lPltVFPP" _._,1,
C .551. ....... 1.4.3.9 ............... 1.11.11.91.01 ........ E5......,.<.P.'.3,.F..)....‘i-9 -._..._P.._._FlPl.P-.l''.'_P--.l. 1 .......
e .311. ....... N.3.1.........,-...1.1...1..1.9.1.91....-f.5. - .(.rlflf.)....t..1 Ve-------..-.-.--.--.-- l .......
FNTP - 'll-f, ............... 91.119191. ........ 7.5. ....... _E.1is.lolt..f.l.qf..1.py.1.py..t_./y.C.t.o .................................... .1.
HALT 00000001 01 Halt 1
(5) NOP 00000000 00 no operation 1
(5) ----- Other 020989
MCU48-36
TOSHIBA TMP80C49A/39A
4. ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Ratings
TMP80C49AP/C39AP/C49AU
SYMBOL ITEM RATTING
VCC Vcc Supply Voltage (with respect to GND (VSS)) - 0.5V to + 7V
VINA Input Voltage(Except EA) -0.5Vto VCC+0.5V
VINE Input Voltage (Only EA) -0.5Vto+13v
PD Power Dissipation (Ta = 85°C) 250mW
TSOLDER Soldering Temperature (Soldering Time 10 sec) 260°C
TSTG Storage Temperature - 65°C to 150°C
Too Operating Temperature - 40°C to 85°C
4.2 DC Characteristics
TMP80C49AP/C39AP/C49AU .
TopR = - 40°C to 85°C, VCC = + 5V t 10%, Vss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage _ -
VIL (Except XTAL1, XTAL2, RESET) 0.5 0.8 V
Input Low Voltage - -
VlL1 (XTAL1, XTAL2, RESET) 0.5 0.6 V
Input High Voltage - -
VIH (ExceptXTALI,XTAL2, RESET, PS) 2.2 VCC V
Input High Voltage - 0.7x -
VIH) QOutput Low Voltage - - -
VOL gxcept 1e,fatPa2gi,''27) IOL =1.6mA 0.45 v
utput ow o tage _ - -
VOL1 (/l1,tfu1t7i.l'ii/'g), IOL=1.2mA 0.45 V
utput lg o tage = _ - -
VOHH gxcept Emmi] {3204327) IOH 1.6mA V2.4 v
utput l) 0 tage - _ cc - -
VOH12 (Except P10-P17, on-sz) IOH - 400PA _ 0.8 v
Output High Voltage - -
V = - .
OH21 (/,r1ftu',1t7;i'pd'/2g), IOH SOpA V2 4 V
u put lg otage - - CC - -
VOH22 93104317, PkZOC'PN) lOH - 25PA - 0.8 v
anLea 1Lrrent < v -
ILI f2r,"t1lifhlfr'), V53:V|N§Vcc t10 pA
Igput Lea Current - - - _
Ill (SS, RESET)' vsss VIN S. Vc 50 pA
Output LeakCurrent Vsss-0.45N/ENhN - - -
ILI2 $gt,''uh2yl2u7,) (BUS T ) \jvcco 45V 'v 500 pA
u pu ea urrent ' 0 ss+ . : IN - -
ILO (Hiqh imedace condition) la' Vcc t10 p/I
ICCI Normal VCC = SV, - - 10
VccSupply Operatlon fXTAL=6MHZ mA
C ent VlH=Vcc-fh2V - -
ICCH1 urr HALT Mode V|L=O.2V 2.5
Normal Vcc = w, - -
ICC2 Vcc Supply operation fXTAL=11MHz 15 mA
C re t VlH---Vcc-0.2V - -
ICCH2 U r n HALT Mode VIL:0.2V 4.0
MCU48-37.
TOSHIBA
TM P80C49A/39A
4.3 AC Charactristics
TM P80C49AP/C39AP/C49AU
TOPR = - 40°C to 85°C, Vcc = + 5V , 10%, vss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f(t) UNIT
MIN. MAX.
t Clock Period Note 2 1/xtalf 90.9 1000 ns
tLL ALE Pulse Width 3.5t- 170 150 - ns
tAL Address Setup Time (ALE) 2t - 110 70 - ns
tLA Address Hold Time (ALE) CL=20pF t-40 50 - ns
Control Pulse Width
tcc1 (W. WA) 7.5t - 200 480 ns
Control Pulse Width
tcc2 (W) 6t - 200 350 - ns
Data Setup Time
t - . - -
DW (WR) 6 St 200 390 ns
Data Hold Time
t -__ L= F - 4 -
WD (WR) C 20p t 50 0 ns
Data Hold Time
tDR (Ara,PrEN) CL=20PF 1.5t-30 0 110 ns
tRD1 Dataluput Read Time 5.5t- 120 - 375 ns
Data Input Read Time
tRD2 (PTtTi) 4t 120 240 ns
Address SetupTime
tAW (W) St - 150 300 - ns
Address Setup Time
tADI (m) 10t- 170 730 ns
Address Setup Time
tAD2 (PS-EN-) 7t-. 170 460 ns
Address Float Time
tAFCI (R-D,VI/R) CL=20PF 2t-40 140 - ns
Address Float Time
t - = A - -
AFC2 (PSEN) CL 20pF 0 5t 40 10 ns
ALE to Control Time
tLAFCI (PB, W) 3t - 75 200 - ns
ALE to Control Time
t ---- _ - _
LAFC2 (PSEN) 1 5t 75 60 ns
Control to ALE Time
tcal (AriTim,PROG) t-65 25 ns
Control to ALE Time
tCA2 (PStN) 4t - 70 290 - ns
MCU48-38
TOSHIBA
TMP80C49A/39A
AC Charactristics (Continue) .
TOpR = - 40°C to 85°C, Vcc = + 5V t 10%, I/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f(t) UNIT
MIN. MAX.
PortControl Setup Time
tcp (PROG) 1.5t 80 50 ns
Port Control Hold Time
tpc (PROG) 4t - 260 100 - ns
Port2 Input Data SetupTime - -
tpR (PROG) 8.5t 120 650 ns
Port 2 Input Data Hold Time
t 1.5t 0 140
PF (PROG) ns
Port 2 Output Data Setup Time
top (PROG) 6t 90 250 ns
Port 2 Output Data Hold Time
tpD (PROG) 1.5t 90 40 ns
tpp PROG Pulse Width 10.5t - 250 700 - ns
Port 2 l/C) Data Setup Time
in (ALE) 4t 200 160 ns
ttp Port 2 l/O Data Hold Time (ALE) 0.5t - 30 15 - ns
tpv Port Output Delay Time (ALE) 4.5t + 100 - 510 ns
topRR To Clock Period 3t 270 _ ns
tcy Cycle Time 15t 1.36 15.0 ps
Note: 1. Control Output CL = 80pF. BUS Output CL = 150pF.
2. The f(t) assumes 50% duty cycle on XTAL1 and XTAL2.
The Max. Clock frequency is 11MHz. and the Min. Clock frequency is IMHz.
MCU48-39
TOSHIBA TMP80C49A/39A
4.4 Absolute Maximum Ratings
TM P80C49AP-6/TM P80C39AP-6/TMP80C49AU-6
SYMBOL ITEM RATTING
Vcc Vcc Supply Voltage (with respect to GND (N/ss)) - 0.5V to + 7V
VINA Input Voltage (Except EA) -0.5V to VCC+0.5V
VINE Input Voltage(Onfy EA) -0.5V to+13V
PD Power Dissipation (Ta = 85°C) 250mW
TSOLDER Soldering Temperature (Soldering Time 10 sec) 260°C
TSTG Storage Temperature - 65°C to 150°C
TopR Operating Temperature - 40°C to 85''C
4.5 DC Characteristics (I)
TMP80C49AP-67MP80C39AP-6/TMP80C49AU-6 .
TOPR = - 40°C to 85''C, Vcc = + 5V t 10%, Vss = 0V, unless otherwise noted
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
VIL Input Low Voltage -0.5 - 0.8 V
Input High Voltage - -
VIH (Except XTAL1, XTAL2, RESET, PS) 2.2 Vcc V
Input High Voltage - 0.7 -
VIH1 (XTAL1, XTALz, RESET, PS) x Vcc Vcc V
Output Low Voltage - - -
VOL (ExceptP10-P17,P20-P27) IOL=1.6mA 0.45 v
Output Low Voltage - - -
VOL1 (P10-P17, on-P27) IOL-1.2mA 0.45 V
Output High Voltage - - - -
VOH11 (Except P10-P17.P20-P27) IOH - 1.6mA 2.4 v
Output High Voltage - - Vcc - -
VOHI2 (P104317, on-P27) IOH _ 400pA - 0.8 v
Output High Voltage - - - -
Output High Voltage - - Vcc - -
VOH22 (P109171 P204327) IOH _ 25pA -0.8 v
Inpu_t_Leak Cirrent (: - -
Il (T1,INT, EA, PS) VssSVi-EVcc i 10 pA
Iwut Leak Current (,7 <_ - - _
Ill (SS, RESET) V55: VIN -- Vcc 50 pA
Input Leak Current V55+0.45V§V1N - - -
'le (P10-P17. on-P27) E Vcc 500 pA
Output LeakCurrent(BUS,T0) V55+0.45V;V|N - -
ILO (High impedance condition) S- Vcc t10 pA
Normal V = 5V - -
lCC1 . CC ' 10
Vcc Supply operation fxTAL= 6MHz mA
Current VIH =Vcc-0.2V - -
ICCH1 HALT Mode V|L=O.2V 2.5
MCU48-40
TOSHIBA
TM P80C49A/39A
4.6 DC Characteristics (II)
TMP80C49AP-6/TMP8OC39AP-6/TMP80C49AU-6 .
TopR = - 40°C to 85°C, Vcc = + 5V i 20%, I/ss = 0V, unless otherwise noted
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
VIL Input Low Voltage -0.5 - X V
In t Hi h V lta
VIH pu lg o ge - 0.5 x - Vcc V
(Except XTAL1, XTAL2, RESET, S) Vcc
In ut Hi h Volta e
Vim p g g - 0.7 M - Vcc v
(XTAL1, XTALz, RESET, PS) Vcc
Output Low Voltage
VOL lOL =1.6mA - - 0.45 V
(Except P10-Pw,P20-P27)
VOL1 Output Low Voltage IOL =1 2mA - - o 45 v
(P104317, on-P27) - I .
Output HighVoltage Vcc-
VOH12 IOH= -400 A - - V
(Except P1o-P17, P20-P27) p 0.8
Output High Voltage Vcc -
VOH22 IOH = -.. 25 A - - V
(P104317, on-P27) p 0.8
iLl Input LeakCurrent V SVINSV - - fc10 A
(T1,fNT,EA,PT) 55: _- CC - p
Input Leak Current - Vcc
- - s VIN S V - -
Im (SS, RESET) Vss CC 0.1 PA
ILI2 Input Leak Current Vss+fh45VSVIN - - -1/cc A
(P104317, on-P27) s, Vcc 0.01 p
Out ut Leak Current(BUS,T ) . E
ILO . p . .. o Vss+0.45V VIN - - +10 PA
(High impedance condition) SN/cc
ICC1 Esziziion Kit“... - - w
Vcc Supply Current mA
ICCH1 HALTM d VlH=Vcc-0.2V - - 2 5
t9 e VIL = 0.2V .
MCU48-41
TOSHI BA TMP80C49A/39A
4.7 AC Charactristics
TM P80C49AP-6/T M P80C39AP-6/T M P80C49AU-6 .
TopR = - 40°C to 85°C, Vcc = + 5V t 20%, I/ss = 0V, unless otherwise noted.
SEMBOL PARAMETER CONDITION it) MIN. MAX. U
t Clock Period Note 2 1 /xtal f 166.6 1000 ns
tu. ALE Pulse Width 3.5t- 170 410 - ns
tAt. Address SetupTime (ALE) 2t-- 110 220 - ns
tLA Address Hold Time (ALE) CL=20pF t-40 120 - ns
Control Pulse Width
__ 7.5t-200 1050 -
tcc; (RD,WR) ns
Control Pulse Width
_r_.._ - 0 -
tcc2 (PSEN) St 200 80 ns
Data Setup Time -
tow (WIT) 6.5t 200 880 ns
Data Hold Time
t - CL = 20 F t - 50 120 -
WD (WR) p ns
Data Hold Time
_ - L = F 1. - 22
tDR (RD,PSEN) C 20p St 30 0 0 ns
tam Data_lnput Read Time 5.5t - 120 - 880 ns
Data Input Read Time
t _.. 4t-. 12 - 550
RD2 (PSEN) 0 ns
t Address SetupTime St- 150 680 - ns
AW (W/iT)
tAm Addgss Setup Time 10t -170 - 1500 ns
Address Setup Time
----- 7 - 17 - 1
tAD2 (PSEN) t 0 000 ns
t Address Float Time CL - 20 F 2t - 40 290 - ns
AFC1 (W, Vim)) - p T
Address Float Time -
tAFC2 (PSEN) CL=20PF 0.5t-40 40 ns
ALE to Control Time -
tLAFC1 (rt0yT/rt) 3t - 75 420 ns
ALE to Control Time -
tLAFC2 (m) 1.5t - 75 175 ns
Control to ALE Time -
tCA1 (WIWIPROG) t-65 100 ns
Control to ALE Time -
tCA2 (m) At - 70 590 ns
MCU48-42
TOSHIBA
TM P80C49A/39A
AC Charactristics (Continue) .
TopR = -400C to 85°C, Vcc = + 5V t 10%, l/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f(t) UNIT
MIN. MAX.
Port Control Setup Time
1. - 170 - ns
tcp (PROG) 5t 80
Port Control Hold Time
- 4 - ns
tpc (PROG) 4t 260 00
Port 2 input Data Setup Time
. - 12 - 1290 ns
tPR (PROG) 8 St 0
Port 2 Input Data Hold Time
1. t 0 250 ns
t" (PROG) 5
Port 2 Output Data Setup
- 71 -
IDP Time (PROG) tit 290 0 ns
Port 2 Output Data Hold Time
tPD (PROG) 1.5t 90 160 ns
tpp PROG Pulse Width 10.5t-250 1500 - ns
Port 2 l/O Data Setup Time -
tpL (ALE) 4t 200 460 ns
Port 2 HO Data Hold Time
0.5t- 3 1 -
tLP (ALE) 0 30 ns
tpv Port Output Delay Time (ALE) 4.5t+ 100 - 850 ns
topRR To Clock Period 3t 500 - ns
tcy Cycle Time 1St 2.5 15.0 ps
(M0989
Note : 1. Control Output CL=80pF. BUS Output CL-- 150pF.
2. The f(t) assumes 50% duty cycle on XTAL1 and XTAL2.
The Max. Clock frequency is 6MHz. and the Min. Clock frequency is lMHz.
MCU48-43
TOSHIBA TM P80c49A/39A
4.8 Timing Waveform
A. Instruction Fetch from External Program Memory
- tcp2 -
B. Read from External Data Memory
e--------
tLAFc1 tCAI- -
DBo.7 'tttttttttttti INPUT DATA (ttey
MCU48-44
TOSHIBA
TMP80C49A/39A
C. Write into External Data Memotry
- tcc1 ---K
X///////
DBo-7 Tl1jjjllllji,
//////
- tDW _ - two
OUTPUT DATA
D. Timing of Port 2 during Expander Instruction Execution
_ W - tCAI-- -
PORT l, 2 PORT l, 2 DATA NEW PORT l, 2 DATA
- tLP -
- RT 2 .2 PORT
PORT 20-22 POFBTA$223 X PCH PCDATOA 3 CONTROL OUTPUT DATA
- top 2. £0
PORT 20-23 PORT 20-23 PORT INPUT
PORT 20-23 DATA X PCH X DATA >$ CONTROL DATA k
to: tpc - !
- th - r
- tpR ---F f'""-
PROG N --- tpp ----t/
MCU48-45
TOSHIBA
TMP80C49A/39A
4.9 Stand-By Function
4.9.1 PoweR Down Mode (I) ..... Data Hold Mode in RAM
The operation of oscillation circuit is suspended by setting PS" terminal to low level
after RESET terminal has been set to low level. Consequently, all the data in RAM area
can be held in low power consumption.
The minimum hold voltage of Vcc in this mode is 2V.
P-S" terminal is set to high level to resume oscillation after Vcc has been reset to 5V,
and then RESET terminal is set to high level, thus, the normal mode is restarted from
the initialize operation (address 0).
(1) DC Characteristics
TMP80C49AP/C39AP/C49AU
TM P80C49AP-6/C39AP-6/C49AU-6
: TopR = - 40°C to 85°C, I/ss = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
VSB1 Standby Voltage (1) 2.0 - 6.0 V
Vcc = 5V, VIH = Vcc -
ISB1 Standby Current (1) -0.2V, VIL=0.2V 0.5 10 pA
(2) AC Characteristics
TMP80C49AP/C39AP/C49AU Mcc = + 5 , 10%, Mss = 0V
TM P80C49AP-6/C39AP-6/C50AU-6 CC = + 5V i 20%, Viii = 0V
SYMBOL PARAMETER TEST CONDITION MIN TYP. MAX. UNIT
tngR Power Save Hold Time (RESET) IO - - ps
tpssR Power Save Setup Time (RESET) 10 - - ms
tVH Vcc Hold Time (P-S) 5 - - ps
tvs Vcc Setup Time (PT) 5 - - ps
Note : tcy = 2.5ps (fXTAL=6MHz) 040989
(3) Timing Waveform
----- tPSSR
Oa0989
MCU48-46
TOSHIBA TMP80C49A/39A
4.9.2 Power Down Mode (ll) ..... ALL Data Hold Mode
The operation of oscillation circuit is suspended by setting FS terminal to low level
after gg terminal has been set to low level. Consequently, all data can be held in low
power consumption.
The minimum hold voltage of Vcc in this mode is 3V.
rrg terminal is set to high level to resume oscillation after Vcc has been reset to 5V,
and then E terminal is set to high level, thus, the normal mode is restarted
continuously from the state just before the power down mode (II).
(1) AC Characteristics
TM P80C49AP/C39AP/C49AU
TM P80C49AP-6/C39AP-6/C49AU-6 I TopR = - 40°C to 85°C, vss = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
VSB2 Standby Voltage (2) 3.0 - 6.0 V
1582 Standby Current (2) It :SVQIY'E‘Oj/VCC - 0.5 10 pA
(2) AC Characteristics
TMP80C49AP/C39AP/C49AU I Mcc = + 5V , 10%, Mss = 0V
TMP80C49AP-6/C39AP-6/C49AU-6 : vee = + 5V t 20%, Vii; = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
tPSHR Power Save Hold Time (TS) 10 - - ps
tpsga Power Save Setup Time (TS) 10 - - ms
tVH Vcc Hold Time (P-S) 5 - - ps
tvs Vcc Setup Time (FC) 5 - - 115
Note : tcy = 2.5ys (fXTAL= 6MHz) 040989
(3) Timing Waveform
- ---91 - tVH - - tus
PS _ l "
- 6 tPSHS tPSSS
MCU48-47
TOSHIBA TMP80C49A/39A
4.9.3 HALT MODE
(1) HALTINSTRUCTION
OP code is "01H". HALT INSTRUCTION is an additional instruction to the standard
.8048/8049 instruction set.
(2) Entry to HALT MODE
On the execution of HALT INSTRUCTION, TMP80C49A/TMP80C39A enter HALT
(3) Status in HALT MODE
The oscillator continues its operation, however, the internal clocks and internal logic
values just prior to the execution of HALT INSTRUCTION are maintained. Power
consumption in HALT MODE is less than 50% of normal operation. The status of each
pins are described in the following table.
(4) Release from HALT MODE
HALT MODE is released by either of two signals (RESET, INT).
(4.1) RESET Release Mode .' An active RESET input signal causes the normal reset
function. TMP80C49A/TMP80C39A start the program
at address ''000H".
(4.2) I TRelease Mode : An active TNT input signal causes the normal
operation.
0 In case of interrupt enable mode (E1 MODE), TMP8OC49A/TMP80C39A
execute the interrupt service routine, after the execution of one instruction
which is located at the next address after HALT INSTRUCTION.
O In case of interrupt disable mode (DI MODE), TMP80C49A/TMP80C39A
execute normal operation from the next address after HALT INSTRUCTION.
(5) Supply Voltage Range in HALT MODE
The operating supply voltage range and the operating temperature range are same as
in normal operation.
TMP80C49AP/C39AP/C49AU : Vcc = 5V i 10%
TMP80C49AP-6/C39AP-6/C49AU-6 : Vcc = 5V 1' 20%
MCU48-48
TOSHIBA TMP80C49A/39A
4.9.4 Pin Status In Power Down Mode (I) (II)
PIN NAME STATUS
DBo-DB7
High impedance
Pu) P17 Inputdisabled
P20-P27
To High impedance, inputdisabled
T1 Inputdisabled
XTAL1 High impedance
XTAL2 Output "High" Level
RESET, Ts Input disabled when oscillator is stopped. Pull-up transistors turn off.
W, EA Input disabled when oscilltor is stopped.
ATO, W, ALE . .
PROG, PS-EN High impedance
4.9.5 Pin Status In HALT MODE
PIN NAME STATUS
DBo~DB7
P10~P17 Values priorto the execution of HALT INSTRUCTION are maintained.
P20-P27
To Status prior to the execution of HALT INSTRUCTION is maintained.
T1 Inputdisabled
XTAL1, XTAL2 Continue oscillation
RESET, W Input enabled
S-S, EA Inputdisabled
PROG, PS-EN Output High level
ALE Output "Low" level
MCU48-49
TOSHIBA TMP80C49A/39A
5. OSCILLATOR
QUARTZ CRYSTAL
f=1MHzto 4MHz :C1=C2 =30pF XTAL;
. - CI -u 2 /
f=4MHzto11MHz :Cl=C2=20pF T
CERAMIC RESONATOR 3
f=1MHzto 3MHz :C1=C2=100pF C2 L XTALz "
f=3MHzto11MHz :c1=c2= 30PF T
A 040989
6. TYPICAL CHARACTERISTICS
:Vcc = 5V,Ta = 25°C, unless Otherwise noted.
Vcc IOL
(V) (mA)
/ 20 /"
ww'" 10
3 ,1 /
5 10 15 fXTAL (MHz) 0 1 2 3 4 5 VOUT (V)
Vcc-huAx. TYPICAL CURVE VouT-loLTYPlCALCURVE
ICC 1 2 3 4 5 VOUT(V)
10 -50 /L/
-100 "--''"'"
x" - _--''"
s / 150 s----"
w,,,,-"''''''''''" -200
5 IO 15 fXTAL(MHz) (uA)
fXTAL - lcc TYPICAL CURVE
VouT-loH TYPICAL CURVE
(PORT 1, 2)
MCU48-50
TOSH I BA TMP80C49A/39A
tRESET
(ms) 1 2 3 4 5 Vour (V)
60 _5 7
20 -10 e,.,.,.,,.-''''''''
-15 -...-" '
0.01 0.02 0.03 0.06 0.1 0.2 0.3 CRESET IOH
(pF) (mA)
CREssT-tRESET TYPICAL CURVE I/our-- IOH TYPICAL CURVE
(DB, CONTRO L)
7. OUTLINE DRAWING
7.1 Outline Drawing For TMP80C49AP/-6,TMP80C39AP/-6
(plp:Dual Inline Package)
DIP40-P-600
Unitzmm
4O 21 f
C-lr-nr-lr-Tr-Tr-lr-lr-lr-II-hr-II-Tr-lr-Tr-lr-lr-Ir-Ir-I CD
13.4i0.2
L-JE-IL-lL-IL-Ir-rl-lc-lui';);;:;;;;);
1 20 "i/
50.7t0.2 - .
CD a:;
+ir-+e-
4 0 H05 0.1 F, m
1.22TYP l. , .1 . i . _
I Ir ll [jLcltlo:jif./[) CD
5 270289
Note: 1. This dimension is measured at the center ofbending point ofleads.
2. Each lead pitch is 2.54mm, and all the leads are located within i0.25mm from their
theoritical positions with respect to No.1 and No.40 leads.
MCU48-51
TOSHIBA TMP80C49A/39A
7.2 Outline Drawing For TMP80C49AU/-6
(Micro Flat Package)
QFP44-P-1010A
138:0.3 Unit:mm
ii3vmum2i
10 0:0 2
0.35 , 0.1
3.05MAX
f:_:sl0._' s;
'270289
Note: 1. The above dimensions don't include the burr ofpackage and the residue oftie-bar cut.
The burr of package and the residure of tie-bar cut should be 0.15 mm (Max.).
2. Applied ti the lead flat porttion.
MCU48-52
TOSH I BA TMP80C50A/40A
CMOS 8-BIT SINGLE-CHIP MICROCOIVIPUTER (TLCS-48C)
TMP80C50AP /TM P80C50AP- 6
TM P80C4OAP /TlVI P80C40AP- 6
TM P80C50AU/TIVIP80C50AU-6
l. GENERAL DESCRIPTION AND FEATURES
The TMP80C50A is a single chip microcomputer fabricated in Silicon Gate CMOS
technology which provides internal 8-bit parallel architecture.
The following basic architectural functions ofa computer have been included in a single
chip; an 8-bit CPU, 256X8 RAM data memory, 4KX8 ROM program memory, 27 I/O
lines and an 8-bit timer/event counter.
The TMP80C50A is particularly efficient as a controller. It has extensive bit
handling capability us well as facilities for both binary and BCD arithmetic.
The TMP80C40A/-6 is the equivalent of a TMP80C50A/-6 without ROM program
memory on chip. By using this device with external EPROM or RAM, software
debugging becomes easy.
The TMP80C50AP/-6 and TMP8OC40APl-6 are in a standard Dual Inline Package.
The TMP80C50AUI-6 is in a 44-pin Micro Flat Package.
FEATURES
0 TMP80C50AP/TMP80C40AP/TMP8OC5OAU
1.36ps Instruction Cycle Time - 40°C to 85°C, 5V i‘ 10%
0 TMP80C50AP-6/TMP80C40AP-6/TMP80C50AU-6
2.5ps Instruction Cycle Time -400C to 85°C, 5V i 20%
. Software Upward Compatible with TMP8049AP/INTEL'S 8049.
0 4KM8 masked ROM/256x8 RAM
0 Low Power
10mA MAX. in Normal Operation(Vcc = 5V, fXTAL = GMHZ)
10pA MAX. in Power Down Mode (VCC =5V, fXTAL ". DC)
0 Power Down Mode (Stand-by Mode)
ct Halt Mode (Idle Mode)
MCU48-53
TOSHIBA
TMP80CSOA/40A
2. PIN CONNECTIONS AND PIN FUNCTIONS
2.1 Pin Connections (Top View)
Figure 2.1 (1)
tiiiiiiii?i'l;
oo130<1§
Figure 2.1 (2)
1 K-f4o
WEN E9 32
W E 10 31
ALE E11 30
D80 E 12 29
DB1 E13 28
DB2 C 14 27
033 E 15 26
DB4 E 16 25
DBs E 17 24
036 E 18 23
D87 E 19 22
Vss 1120 21
UUUMUUJUUUHUMUUUUUUU
Micro Flat Package Pin Connections
Vcc ( + 5V)
DIP Pin Connections
'tflfd < Slip
0.11.1.1 1.11
MCU48-54
TOSHIBA TMP80C50A/40A
Pin Names And Pin Description
0 VSS (Power Supply)
Circuit GND potential
0 Vcc (Power Supply)
+ 5V during operation
o PSI (Input)
The control signal for the power saving at the power down mode (Active Low)
0 PROG (Output)
Output strobe for the TMP82C43P I/O expander.
tt P10-Prr(h1put/Output)Port1
8-bit quasi-bidirectional port (Internal Pullup=50KQ).
0 P20-P27 (Input/Output) Port2
8-bit quasi-bidirectionaI port (Internal Pullup = SOKQ).
P20-P23 contain the four high order program counter bits during an external
program memory fetch and serve as a 4-bit I/O expander bus for the TMP82C43P.
ct DBo-DB7 (Inpiit/Output, Tri-State)
True bidirectional port which can be written or read synchronously using the
IRD, wrt strobes. The port can also be statically latched. Contains the 8 low order
program counter bits during an external program memory fetch, and receives the
addressed instruction under the control of m.
Also contains the address and data during an external RAM data store
_ instruction, under control of ALE, m, and W.
0 To (Input/Output)
Input pin testable using the conditional transfer instructions JTO and JNTO. To
can be designated as a clock output using ENTO CLK instruction.
It T1 (Input)
Input pin testable using the JTl and JNTl instruction. Can be designated the
event counter input using the timer/STRT CNT instruction.
0 INT (input)
External interrupt input. Initiates an interrupt if interrupt is enabled.
Interrupt is disabled after a reset. Also testable with conditionaljump instruction.
(Active low)
MCU48-55
TOSHIBA TMP80C50A/40A
RTI" (Output)
Output strobe activated during a Bus read. Can be used to enable data onto the
Bus from an external device. Used as a Read Strobe to External Data Memory
(Active Low).
wm (Output)
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
RESET (Input)
Active Low signal which is used to initialize the Processor. Also used during the
power down mode.
ALE (Output)
Address Latch Enable. This signal occurs once during each cycle and is useful
as a clock output. The negative edge of ALE strobes address into external data and
program memory.
PSEN (Output)
Program Store Enable. This output occurs only during a fetch to external
program memory (Active Low).
s-s (Input)
Single step input can be used in conjunction with ALE to "single step" processor
through each instruction when S-S- is low the CPU is placed into a wait state after it
has completed the instruction being executed. Also used during the power down
EA (Input)
External Access input which forces all program memory fetches to reference
external memory. Useful for emulation and debug and essential for testing and
program verification. (Active High)
XTAL 1 (Input)
One side of crystal input for internal oscillator. Also input for external source.
XTAL 2 (Input)
Other side of crystal input.
MCU48-56
TOSHIBA
TMP80C50A/40A
2.3 Block Diagram
DBo-DB7 PurPw P20-P27
T] 8 i 8
WT PORTOBUFFER PORT1BUFFER PORT2BUFFER
(2) (1) 4
OUTPUT OUTPUT OUTPUT MASK ROM
fxTAL” S LATCH LATCH LATCH ==zzi)
l 's {F "h, 4K A 8
1/32 1 (PROGRAM AREA)
INTERRUPT TIMER/
CIRCUIT - COUNTER PCH PCL
c, ij, ( irs'""s J
ACCUMU- TEMPO- (li: Ci;
LATOR RARY REG FLAGS
{} INSTRUC PSW ADDRESS
ACCUMULA- TION REGISTER RAM
TOR LATCH
REGISTER/ 8 256 X 8
DECODER TIMER
lCARRY
I ACCUMULATOR 2)),1TI?crt)
BIT TEST
To T, HTT
POWER T l
SAVE p-s
XTAL, XTAL2 RESET W EA 3 ALE Frcrv T Nk PROG
"r,rs---/ _ _ _1 n. m E <--v---2 a:
O D 2) < m Lu m Lu q Lu m u;
F- a. a: a w _ _ LLl I m cg m Lu 0 Lu
< ae o: H ty: Lu u m u: U 0 c) O m 2 m
-: - ug D U.l 0: Lu Cy _ n: O u: < o < O
_, r- F-- m _ CI -' Lu CY < _ n: _ _ c: o. x
- 3 _ a a x CY tag -l < -' w o. w < _ X _
L) 0. Lu - - Lu < W 0 CI m u; v1
:0 Z W a
CD - m -
o: w 040989
Note 1 '. The lower order 4 bit of port 2 output latch are used also for input/output operations
with the I/O expander.
Note 2: The output latch of port 0 is also used for address output.
Figure 2.3 Block Diagram
MCU48-57
TOSHIBA TMP80C50AMOA
3. MACHINE INSTRUCTION
The following symbols and codes are used in the list of machine instruction.
Symbol Meaning
Rp Working register (OPp I/O portaddress P; (0JBb Branch instruction in accordance with bit content (b) of operand
aH Higher order3 bits ofa
aN Mediumorder4bits ofa
aL Lowerorder4bits ofa
aML Mediumorderorlowerorder8bits ofa
(a) Content of a
C (a) . Content of RAM addressed by a
EXT[ (a) . Content of external RAM addressed by a
PROC (a) , Content of ROM addressed by a
aOD Value at bit position m of a
atrn:ny Valueat bit position mto nofa
ae-b Store a into b
ae-rb Exchange a for b
Connection
a 1complemetot ofa
a+b a plus b (Addition)
a-b a minus b (Subtraction)
a/\b LogicalAND foraand b
avb LogicalOR foraandb
aVb ExclusiveORfora and b
a=b a is equal to b
aCrb a is not equaltob
(a) BCD Converted value ofaccumulator
MCU48-58
TOSHIBA TMP80C50A/40A
List of TLCS-48 Machine Instruction (1/4)
ObjectCode
E Assembler (1st) Flag
'ce (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
A00 A,Rr 01101rrr 68+p (A)4-(A)+(flc) r=0~7 - 1w; -- 1
RL A 11100111 E7 (A) +(A) 1
we---...-..-.-- ._____-________._PV__ .16).??? t(.1))f??. ................... 0.19:6. ........................................
RLC A 11110111 F7 (A) e-(A)tny t 1
(C)e(A)<7)
_.--'"--.-'"''''-'..---' - __ _.(../))f/l,rtr(f)_.._._.p.--..i.r.rp,., __ .__V_.___ .PF_F_FPFPFFV.__
RR A 01110111 77 (A) '-(A)O+1) n=0-6 1
A .. TVtt_T._t .. ..(.,A.)..<.??..f.(f‘)<,9? _-tr_r_.ll.l-tttlt-''''"'''-'_'.'PVFPFPF__
RRC A 01100111 67 (A)4nye(A)0+1) t 1
(C)e(A)40y
(A)<7> +(C) n--0-6
Ir). ......... A....~....P.P. ........ 990.910.99.95? _(.l))t.(.?p).,,_._.!lr1,,.i, .................... il ......
PIT, - PP.:....‘.‘ ........... .0.p.11.1flNr.iult? _____ (39.1.1131. ........ . ........ 91.11.? ................. 2. ......
C) ANL Pp.#1 100110pp 98+p (Pp) w-(pp)/Ni P=1,2 2
ls -P-__l____F.______ 11.11.1111. __ _.i_i. _-------------------- ___, ..
ORL Pp,#1 100010pp 88+p (Pp)e(Pp)N/i P=1,2 2
iiiiiiii ii
MCU48-59
TOSHIBA TMP80C50A/40A
List of TLCS-48 Machine Instruction (2/4)
ObjectCode
E Assembler (1st) Flag
'dl (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
[ff ....... 6.1.5.145... 00001000 08 (0)5159?) ................................. l .......
bijirl _B1lli, Al .. 000-00010 ........ 02 ....... I(HBUS'VIIAQ) ............................................... 2 -
jiiiL ..... 00.3.2511: ........... 'iiiiirii'iiii)" ........ iii ....... '('iiijeiFiiii.iir'yG' -t_t__.___._e.__..._._...__...t.t._t_.t._.l..F.qVFe__. 2
....................... 1.11.111“ . ii - . _.....-------------.-------
o ijiiir'"ii't"ii','jy''i" 10661666 ...- '80 """" '('isuiFl'iiije'j vi 2 _
N 'N----.------ .iiii'i‘ITL .11. -lt_-...V._._.rVlt-t--t-------tt_--..l.-l.-l-
- MOVD A Pp 000011pp 00+p (A)<3:0> 1-(Pp) p=4--7 2
................... (.lr)fl.i..4?..ti.l._, -.. " . _..--.--.. 'FV..
.i4'j.h.)lr'ri.a.ii'.,r./.'irr.'..' 291211622 32621522 1915.)?EQK3].=.9.>.........j.IIQ2I=AE7Ifﬁ.._._. (r.'.',.' i. [Z . 2;? .......
ANLO 1.3.9.10 ........ 10.9.1101) 9616";1.9.9.).,.sr_<..?p.1_/.\.<.A).<§;0>...p=4~7.2.4............I..j; ....... a .......
’6'RL'6' Pp,'A" ' iiiiiihu'r"ikri-is" (Pp) +(Pp)\/(A)<3:I0u>‘ "'p'é417‘ """ 2
INQ__...BF .................. 99.911?" 18+r (RP..).._f(B."_)fl ._....l.l. F297? ..V._._l._V-F..t.- _...1..,
(I) 1N9. 981‘ ........ Miriijiitr/"iiji/ - tjjr)jj.',F.-triii:j.r.ri.' .Irl,.1 ...._._. ' .......... 1 .......
bie . Rr .......... 'iii'ihF/'/'''eiV'r', ....... I(IR'r) 'diii/j'-'''l' ................ 220;? .................. 1
JMP a aH00100 aH+4 (PC)<10:0> I-a 2
aML (PC)<11> t-(DBF)
51413650611 ................... 10110011 ........ 03 ....... '(je)k"'i:'dsi-iiiiijr''(''ii'cyririijsvijr)') ................................ .2. .......
Ejiir''i'iCi ........... 'iii'ih'i:/ir' 150;}; ....... (RF)"(RP)-1 ...... "''''''''''''''""r,'"='iiL'j' ----_---- if .......
aML if(Rr) '0then(PC)47ADeaNL
___-...-...? else no operation
00 -.- é V__P.P_. PF' 111-10110 ........ 156 ....... "i"t'rej''--'r''t''ta'i'('i'e)k'"j''/ijrdiii'L' ......................................... .2. .......
................ aML f.l.s.t.s...1t./opt.rra.,t,1Y. . .. _ . _..
g (iid': - a ...... 11100-110 ........ ES ...... "i''t''("'eFt'i'iGr'ilj'e)2'j'':hG-'t'iii'c' .................................... 2, ,,,,,,
T, ........................................... Ill ......... 1l.s.e.yr/rp..?I.a..tly1. ............................................
3 JI a 11000110 p...., ie'' {f(A)'=0 't'i'ailj'e)ki.''ijri-'diiL' PVV.PP_PVV.'V'"'V'-'FP'''P"'"Ft''. 2 .
= ........................................... WF ....................... 1lteIf,ryt.ry1..t,1t.P, ....................................................................
C, JNZ a 10010110 '96 if(AVO theMPc)47:0realriL 2
E _________________ aML e1se no operation .
= JTO . a ............... 001101.10 ........ 30 ....... 'i'?''iiirrit'ailj'e)F7''.'-'ij'r''i-ui'L' 'VP.V'PFVV-V"'''I'"9" ii .......
Z _V_r_.PlPl.....FV.P...l_ ?MF ........................ tl.it..ryrf..p..tr..aAliT. -_F-N--tlrt_-t------_
m JNTO a 00100110 26 if T0=0 then(Pc)0ADe-abtL 2
t; _ aML else no operation
'ji'i"''''''a' .................... iiiiiri'i''1'ii ........ 5'6.” "i't''ii'--rtj'Gil'i'e)ki:'ii'y'l'air .F.._..t...VP..'"P_-l-- ii -
'r'.VPP'VFlV''lFl..P-r_ aML. else no Operation
Jiiii a . "61660116 """" 'iii'''"'')''?""'')-))''''."-)'')?:'')'?)'''..)')'';')', """"""""""""""""""""" 2 """"
"'''''P.'''lP_._Pl-- Mr else no operation A .. - .
JFO a 10116116 _...-- iii, -.. ‘1'?"'F'6é'1"”thé'r'i(156)27'365L'éML _-_.---..-....--.-.,..--. 2 """"
______________________________ aML else no operation
(iii'" a V . "61116116 """" "iii''"'")"''?'',--'''.'';';'')'''?:'")'':')'''..'')''-'-';')', """"""""""""""""""""" 2 -_____
.......................................... Mr... _ else no operation '_r..__. .
iii"' a iiiiifiijiiij ....... "iii"'"')'?'"')'')"--']""').')')'''?:'")'':')''..'';')'")''-"-''')'?'. ................................ ji .......
aML else no operation
(1) ..... Register Instruction
MCU48-60
TOSHIBA TMP80C50A/40A
List of TLCS-48 Machine Instruction (3/4)
ObjectCode
E Assembler (1st) Flag
: (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
JNI a 10000110 86 if INT =0 then(PC)trADeaNL 2
aML else no operation
(2) ',j'iii'o''''''''d .................... ijihr1'iiir1'ir'io'l'rr'"ir(')i'j''t'ijr-'-''i"'iiii// 'PVlP't_FV_P__V'VFl.tV.V.P'P"P'.'lt'V_.V “2..
aML (PC)t7:0yeaNL
else no operation b=0~7
CALL a aH10100 aH+14 [(SP)] '-(PSfl)t7:4F(Pc) 2
aML (SP) <-(SP)+1
(PC)<10:0> ea
-Fm----_rr---F--.-F- (PC)<11> e-(0BF) _
(3) RET 10000011 ..... 03 ...... 'js'ir)'lri'iiiij'-'-''1 V_V.V_F_V_P_P.FVPV_PVPVP.'VlPV_P.P_FlF_P_VPPNPFPV_ .2.
(PC) '-C(SP)y:11:0y
'ii'i'i'ii"''''''"''''rjii'1'ii'i''1''1' ........ iii ....... '("eirii-j''iiii')''-'''1 ._PPlP..__l._lV._llPV_F_. iii ........... ii -
(PC) 4-HSP))411:0Y
(PSW)<7:4> +[(SP)]<15:12>
.018 __..... 9. _ _ 10010111 97 (0)e0 ............... _1
CPL .. C ................ 101001.11 ........ ji'i'''"''j'e''ii-h''dije)' __"...........-"--.--.'.-'.''-..'..'.-' H1.
(4) ELIEIIIijféinjinjjiIIi11961919111IjjiéjsfjjiiI116101}?LijijiiijjiiijiijiiijjiiijiiiijijijjijijifijijijIli'jfjfiIIQI'IiLij'iililliijijlj
CPL F.9____.._._.__._V.19.910191. 95 (FOHNQTKEQ) _---------.-------- l -
:émiiiiia .................. 19.196101 """" 15-111; tC., __' A 1 TFV V .. '_'.].'.''.'.',''.'..'.''.].'.']'..''.]'..']'.."',.' l
CPL F1 10116161 ._- iii"'''''')'?'')''';'-)'))'''"'')" P-_'"'.-'''."."'"'''''"....''""'"''''''''''" '1"
NOV A , " 11111ppp F8+r (A)e(Rr') p--0-7 1
' (" l, 1
MW Anew ....... 1000000r 804% (A) trrT_rlfrr)ll . . .. P--0 l . . l,
iibVii" A,(§Am ' 10100011” ...... A3 ...... '('hriVoiid'r'iiii:V'1r."'ir'(jij'l' .V_V.l.lVFVlr.F_Pr_F_rrFPVl. 1 ......
>M0VPH3WAIIéA ............. 111000-11- ........ E3 ..... "(j()''"i-'riidr(ieje'r1b'kii'ijij'l ............ _ ..1V
(2) ..... Branch Instruction (3) ..... Subroutine Instruction 020989
(4) ..... Flag Instruction
MCU48-61
TOSHIBA TMP80C50A/4OA
List of TLCS-48 Machine Instruction (4/4)
ObjectCode
E Assembler (1st) Flag
ff (2nd) Function Cycle
- Mnemonic . C,AC
Bin Hex
" WY ....... 5.2.? ............... 9.1.9.9991? ........ 1r.......rl)rtrT..i1..). VIP-lt-tl-P-__'''.''''-..--.-.-
w MQY ....... LB 'FP'F.P.'P'.P'_ 9.1.1.9991? ........ l? ....... (IBIfif‘) mer------.--.---..-.---.----.
I' STRT T 01010101 55 Start Timer
O .................................................................................................................................................................................
U) STRT CNT 01000101 45 Start Counter 1
“é $1915...1.9.0111:991999.99........99lﬁjf.$99.9.IITﬁfiiiéikiéééIUibﬁéﬁIIIIIIII...]..II.II. ................ 1.9)....
: oE..N...........T.f.ir.o..T.J, ........... 99199191 - 29 ....... Ii.el.o..l.t...T..iItr:/,c..y/.nAtr....1..ryt..e..iy.y..p,.t. "''''''"''PPP'v'Fl. 1 .......
DIS TCNTI 00110101 35 Disable Timer/Counter Interrupt 1
Jill .......... I ..._tr..V-.__-_ I). 9.999.191 ........ pp ....... .E..n.i8.oltf.xAt:tti.1h.rr.1..t.?.r.Ty.Io_t. ......................................... 1 .......
.9!§.......I. .................... 99.9.1919} ........ Ir ....... 11s.H.b.1t.Ir1tryy.C1..r.l.t,.tr.y.y..p..t. ..P.PV.V..P_VPllPl.F-_ 1 .......
G .f..E1-....,...f.ty.l ............... 1.1.9.9919? ........ Iir._....(..fl.e.i.)t...,? ..FN.W._-l.l----.--.---------r-- 1 ......
t .SEP......B.B..1. ............... 1.1.9.1919? ........ 9.5 ....... (95.1%...1 .._F.'l..l-.__.F.-._._....V.P.FVF.PVt_._ ..1...
C 5?}. ....... If/l ............... 1.1.1.9919} ........ .E.!.l.......(p?.5rt/). __-.------------------ 1 .......
e .551........M.5..1. _''...'"'.'"'.. 1.1.1.1949}. ........ .F.1.._(p,irF.)..,t_1, F--------------.----- 1 .......
ENTQ ..... 'l-lt. ............... 9.1.1.1919} ........ Z5. - er.r.1i8olt.,ii.l..qf.1.py.t.,p.roCo..rCT..o. .................................... l .......
HALT 00000001 01 Halt 1
(5) NOP 00000000 00 no operation 1
(S) ..... Other 020989
MCU48-62
TOSHI BA TMP80C50A/4OA
4. ELECTRICALCHARACTERISTICS
4.1 Absolute Maximum ratings
TM P80C50AP/C40AP/C50AU
SYMBOL ITEM RATING
Vcc Vcc Supply Voltage (with respect to GND (Vss)) - 0.5V to + 7V
VINA Input Voltage (Except EA) -0.5V to VCC+0.5V
VINB Input Voltage (Only EA) -0.SV to 13V
Po Power Dissipation (Ta = 85°C) 250mW
TSOLDER Soldering Temperature (Soldering Timer 10 sec) 260°C
TSTG Storage Temperature - 65''C to 150°C
TopR Operating Temperature - 40°C to 85°C
4.2 DC Characteristics
TMP8OC50AP/C40AP/C50AU .
TOPR = - 40°C to 85°C, Vcc = + 5V i 10%, I/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
Input Low Voltage -
VIL (Except XTAL1, XTAL2, RESET) -0.5 J8 V
Input Low Voltage - -
VlLI (XTAL1, XEALZ, RESET) OE 0.6 V
Input Hig Voltage - -
VIH (Except fJAjo1it'fJ,y2"TE''Tv'-s) 2.2 Vcc V
Input Hig Voltage -- on x - .
VIH1 (XTAL1, XTALz, RESET, PS) Vcc Vcc V
Output Low Voltage - - -
VOL gxfepi ['g,27,)'a2g-eP27) IOL =1.6mA 045 v
u pu ow o tage = - - V
VOL1 g‘O'PWhPZCK/Ua IOL 1.2mA 0.45
utput 19 o age - - - -
VOHII (OEX’Eepi 'ig/N, leo-P27) IOH - 1.6mA V2.4 v
u pu lg otage - - cc- - -
VOH12 ExceptPurPw,P2o-P27) IOH - 400PA 0.8 v
Output High Voltage - - - -
VOH21 (/'y2ot7il'g,1'g), IOH - SOpA V2.4 V
utput lg O tage - - cc - - -
VOH22 [')1,ou-t''iga12tl',2,7e) lOH - 25PA 0.8 V
nput_ea u_rrent - -
ILI (TI, INT, EA,PS) VssSVlNSVcc $10 PA
Igput Leak Current - - _
ILH (SS, RESET) Vsssr VIN Ec, Vcc 50 PA
Input Leak Current Vss + 0.45VS VIN - - _
ILI2 (P10-P17. P204327) S. Vcc 500 PA
ILO Oqtpqt Leak Current(BUS,To) Vss+0.4SVSVlN - - :10 pA
iquh impedance condition) E-VCC
ICC1 Normal Vcc = SV, - - 10
Vcc Supply operation {XTAL = 6MHz mA
ICCH1 Current HALT Mode $355-0” - - 2.5
Normal Vcc = iii), - -
ICC2 Vcc Supply operation fXTAL =11MHz 15 mA
ICCH2 Current HALT Mode [llc-l/fi- 0.2V - - 4.0
MCU48-63
TOSHIBA
TM P80C 50A/40A
4.3 AC Charactristics
TMP80C50AP/C4OAP/C50AU
TopR = - 40°C to°85 C, VCC = + 5V i 10%, l/SS = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f(t) UNIT
MIN. MAX.
t Clock Period Note 2 1/xtalf 90.9 1000 ns
tLL ALE Pulse Width 3.5t- 170 150 - ns
tAL Address SetupTime (ALE) 2t- 110 70 - ns
tLA Address Hold Time(ALE) CL=20pF t-40 50 - ns
Control Pulse Width
t - -__ 7. -2 O 480 -
CC1 (RD, WR) 5t 0 ns
Control Pulse Width
tcc2 (m) 6t - 200 350 - ns
Data Setup Time
tow (VW) 6.5t - 200 390 - ns
Data Hold Time
---- = - 4 -
two (WR) CL 20pF t 50 0 ns
Data Hold Time
tDR (R-D,PSE7i) CL=20PF 1.5t-30 0 110 ns
tRD1 Dataiwput Read Time 5.5t- 120 - 375 ns
Data Input Read Time
IRD2 (§§ETU) 4t 120 240 ns
t Address Setup Time St- 150 300 _ ns
AW (OW)
tAm Addtss Setup Time 10t - 170 - 730 ns
Address Setup Time
t --- 7t - 170 - 4 0
A02 (PSEN) 6 ns
Address Float Time
- - = -4 -
tAFC1 (RD, WR) CL 20pF 2t 0 140 ns
Address Float Time
t - = F . -4 _
AFC2 (PSEN) CL 20p 0 5t 0 10 ns
ALE to Control Time
t - - - 7 _
LAFC1 (RD, WR) 3t 5 200 ns
ALE to Control Time
tLAFC2 (W) 1.5t - 75 6O - ns
Control to ALE Time
tCA1 (rit5,l/R, PROG) t-65 25 - ns
Control to ALE Time
tcag (PSEN) 4t - 70 290 - ns
MCU48-64
TOSHIBA TMP80C50AMOA
AC Charactrictics (Continue) .
TOpR = - 40°C t085°C, Vcc = + 5V i 10%, I/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITION f(t) UNIT
MIN. MAX.
Port Control SetupTime
1. -8 SO -
tcp (PROG) St 0 ns
Port Control Hold Time
- 2 1 -
tpc (PROG) 4t 60 00 ns
Port 2 Input Data Setup Time
. - 12 -
tpR (PROG) 8 5t 0 650 ns
Port 2 Input Data Hold Time
tpp (PROG) 1.5t 0 140 ns
Port 2 Output Data Setup Time -
top (PROG) 6t 290 250 ns
Port 2 Output Data Hold Time
t _ - -
PD (PROG) 1 St 90 40 ns
tpp PROG Pulse Width 10.5t - 250 700 - ns
Port 21/0 Data Setup Time
tpL (ALE) 4t 200 160 ns
Port 2 I/O Data Hold Time
t 0.5t - 3O 15 - ns
LP (ALE)
tpv PortOutput Delay Time (ALE) 4.5t+ 100 - 510 ns
topRR To Clock Period 3t 270 - ns
tcy Cycle Time . 15t 1.36 15.0 ns
Note : 1. Control Output CL = 80pF. BUS Output CL = 150pF.
2. The f(t) assumes 50% duty cycle on XTAL1 and XTAL2.
The Max. Clock frequency is llMHz. and the Min. Clock frequency is IMHz.
MCU48-65
TOSHIBA TMP80C50A/40A
4.4 Absolute Maximum Ratings
TMP80C50AP-6mV1 P80C40AP-6/TMP80C50AU-6
SYMBOL ITEM RATING
Vcc Vcc Supply Voltage (with respect to GND (N/ss)) - 0.5V to + 7V
VINA Input Voltage (Except EA) -0.5V to Vcc+0.5V
VINB InputVoltage(Only EA) -0.5V to 13V
PD Power Dissipation (Ta = 85°C) 250mW
TSOLDER Soldering Temperature (Soldering Timer 10 sec) 260°C
TSTG Storage Temperature - 65°C to 150°C
TOPR Operating Temperatu re - 40°C to 85°C
4.5 DC Characteristics (I)
TMp80C50AP-6/TMP80C40AP-6/TMP80C50AU-6 .
TOPR = - 40°C to 85°C, Vcc = + 5V i 10%, I/ss = 0V, unless otherwise noted
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
VIL Input Low Voltage -0.5 - 0.8 V
Input High Voltage - -
VIH (Except XTAL1, XTAL2, RESET, PS) 2.2 Vcc V
Input High Voltage - 0.7 x -
VIH1 (XTAL1, XTAL2, RESET, PS) Vcc Vcc V
Output Low Voltage - - - .
VOL (Exceptpw-P17, on-P27) lOL=1.6mA 0.45 V
Output Low Voltage _ - -
VOL1 (P104317, on-P27) IOL =I.2mA 0.45 V
Output High Voltage _ - - -
VOH11 (Except P10-P17, on-P27) IOH= 1.6mA 2.4 V
Output High Voltage - - Vcc - - -
VOH12 (P1o-P17, on-P27) IOH - 400PA 0.8 V
Output High Voltage - - - -
VOH21 (P109171 on-P27) IOH _ SOpA 2.4 v
Outpu'tHighVoItage - _ Vcc- - -
VOH22 (P10-P17, on-P27) IOH - 25PA 0.8 V
lnpu_t_Leak Cu_rrent < - -
ILI (Ts, INT, EA, PS) vssévm: Vcc t 10 pA
Injut Leak Current < - -
ILl1 (SS, RESET) Vsss V1N : Vcc - 50 pA
Input Leak Current Vss+0.45VENhN - - -
ILl2 (P104317, on-P27) "E Vcc 500 PA
Output Leak Current(BUS,T0) V53+0.45V§V1N - -
ILO (High impedance condition) S. Vcc t10 pA
Normal V = 5V - -
ICC1 . CC ' 1O
Vcc Supply operation fxTAL=6MHz mA
Current VlH=Vccj2V - -
ICCH1 HALTMode VIL=O_2V 2.5
MCU48-66
TOSHIBA
TMP80C50A/40A
4.6 DC Characteristics(|l)
TM P80C50AP-6rrMP80C40AP-6/TMP80C50AU-6 .
TOPR = - 40°C to 85''C, Vcc = + 5V t 20%, l/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
VIL Input Low Voltage -0.5 - 0 V
VIH Input High Voltage - os x - Vcc V
(Except XTAL1, XTAL2, RESET, PS) Vcc
VIH1 Input High Voltage - 0 x - Vcc V
(XTAL1, XTAL2, RESET, PS) Vcc
VOL Output Low Voltage IOL =1.6mA - - 0.45 v
(Except P1o-P17, on-P27)
VOL1 Output Low Voltage lOL=1.2mA - - 0.45 v
(P104317. on-P27)
VOH12 Output High oltage lOH= ~400pA Vcc - - V
(Except P1o-P17, on-P27) 0.8
. i V -
VOH22 Output High Vo tage IOH: -25PA cc - - V
(P1o-P17. on-P27) 0.8
Input Leak Current
H - s s - - i
lLl (T1,|NT,EA,PS) l/ss VIN Vcc IO pA
Input LeakCurrent -VCC
- - s E - - A
ILl1 (SS, RESET) Vss VIN Vcc 0.1 p
ILIZ Input LeakCurrent Vss+0.45VS-VIN - - -Vcc A
(P10'P17. on-P27) s Vcc 0.01 p
Out ut Leak Current BUS,T ) :S
ILO _'."', (H o Vsst0.45V VIN - - AIO PA
(High impedance condition) §Vcc
ICC1 N°"T' Vcc = SV, - - 10
Vcc Supply Current opra lon fXTAL = GMHz mA
ICCH1 HALT Mode 1/lH=Vcc-0.2V - - 2.5
VIL = 0.2V
MCU48-67
TOSHIBA TMP80C50A/40A
4.7 AC Characteristics
TMP80C50AP-6/TMP80C40AP-6/TMP80CSOAU-6 .
TOPR = - 40°C to 85°C, Vcc = + 5V t 20%, l/ss = 0V, unless otherwise noted.
SYMBOL P R METER TEST f 6MHz UNIT
CONDITION (t) MIN. MAX.
t Clock Period Note 2 1/xtal f 166.6 1000 ns
tLL ALE Pulse Width 3.5t- 170 410 - ns
tAL Address SetupTime (ALE) 2t-110 220 - ns
tLA Address Hold Time (ALE) CL=20pF t-40 120 - ns
Control Pulse Width
t - - 7. - 2 0 1 50 -
CCI (RD, WR) 5t 0 0 ns
Control Pulse Width
tcce (TSTuTi) 6t- 200 800 - ns
Data SetupTime
tow (WP) 6.5t 200 880 ns
Data Hold Time
- L = 20 F t - 50 120
two (WR) C p ns
Data Hold Time
.5 - = 2 F l. - 30
um (RD, PSEN) CL Op 5t 0 220 ns
tRD1 Datalnput Read Time 5.5t -120 - 800 ns
Data Input Read Time
4 -12 - 550
IRD2 (PSEN) t 0 ns
Address Setup Time
tAw (W?) St - 150 680 - ns
tAm ACME“ Setup Time 10t - 170 - 1500 ns
Address Setup Time
t W 7t - 170 - 1000
A02 (PSEN) ns
Address Float Time
tAFc1 (CD, m) CL=20PF ilt-40 290 - ns
Address Float Time
tAFC2 (W) CL - 20pF 0.5t - 40 40 - ns
ALE to Control Time
- - - 42 -
tLAFC! (RD, WR) 3t 75 0 ns
ALE to Control Time
tLAFCZ (PSEN) 1.5t-75 175 - ns
Control to ALE Time
tCA1 (W. W PROG) t- 65 100 - ns
Control to ALE Time
tCA2 (PSEN) 4t - 70 590 - ns
MCU48-68
TOSHIBA TMP80C50AMOA
AC S1eec/ppstthgie.rbt,ipe,.,.e). .
TOPR = -. 40''C to 8 ''C, Vcc = + 5V t 20%, l/ss = 0V, unless otherwise noted.
SYMBOL PARAMETER TEST f( ) 6MHz UNIT
CONDITION MIN. MAX.
tcp . Port Control Setup Time (PROG) 1.5t - 80 170 - ns
tpc Port Control Hold Time (PROG) 4t - 260 400 - ns
Port 2 Input Data Setup Time
. - - 129
tpR (PROG) 8 St 120 0 ns
Port 2 Input Data Hold Time
t . 0 250
PF (PROG) 1 5t ns
Port 2 Output Data Setup Time
- 0 71 -
tDp (PROG) 6t 29 0 ns
Port 2 Output Data Hold Time
. - 1 -
tpD (PROG) 1 St 90 60 ns
tpp PROG Pulse Width 10.5t - 250 1500 - ns
tpL Port 2 l/O Data Setup Time (ALE) 4t - 200 460 - ns
tLp Port 2 l/O Data Hold Time (ALE) 0.5t - 30 130 - ns
tpV Port Output Delay Time (ALE) 15t+ 100 - 850 ns
topRR To Clock Period 3t 500 - ns
tcy CycleTime 15t 2.5 15.0 ns
Note: 1. Control Output CL-- 80pF. BUS Output CL = 150pF.
2. The f(t) assumes 50% duty cycle on XTAL1 and XTAL2.
The Max. Clock frequency is 11MHz. and the Min.Clock frequency is lMHz.
MCU48-69
TOSHIBA TMP80CSOA/40A
4.8 Timing Waveform
A. Instruction Fetch from External Program Memory
- tcA2 '
B. Read from External Data Memory
- , M------- tcc; ---
tAFCI A------ tRD1 - ,
jr---------,
DBO-7 ///////////// ADDRESS /////////
INPUT DATA "ll,
MCU48-70
TOSHIBA TMP80C50A/40A
C. Write into External Data Memory
-----ir
tLAFC1 tcpl, -
- tow - - tWD
DBo-7 5:3 'j't,t,t,Y ///// OUTPUT DATA
D. Timing of Port 2 during Expander Instruction Execution
ALE / N /
- tpV - tCAI-- -
PORT 1, 2 PORT l, 2 DATA NEW PORT l, 2 DATA
H tLP -
- - PORT
PORT 20-23 POETAQB X PCH P0§A$g23 CONTROL OUT PUT DATA
- tDp --ce, £0
PORT 20-23 PORT 20-23 PORT INPUT 4
PORT 20-23 DATA y PCH X DATA " CONTROL DATA C
MCU48-71
TOSHIBA TMP80C50A/40A
4.9 Stand-By Function
4.9.1 Power Down Mode (I) ...... Data Hold Mode in RAM
The operation of oscillation circuit is suspended by setting pg terminal to low level
after m terminal has been set to low level. Consequently, all the data in RAM
area can be held in low power consumption.
The minimum hold voltage of Vcc in this mode is 2V.
pg terminal is set to high level to resume oscillation after Vcc has been reset to 5V,
and then ITfiTCET terminal is set to high level, thus, the normal mode is restarted from
the initialize operation (address O).
(1) DC Characteristics
TM P80C50AP/C40AP/C50AU
TM P80C50AP-6/C4OAP-6/C50AU-6 : TOPR = - 40°C to 85°C, VSS = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
VSB1 Standby Voltage (1) 2.0 - tro V
Vcc = 5V, VI H = Vcc -
ISB1 Standby Current(1) -0.2V,VIL=0.2V 0.5 10 pA
(2) AC Characteristics
TMP80C50AP/C4OAP/C50AU I Mcc = 5V t 10%, Mss = 0V
TMP80C50AP-6/C40AP-6/C50AU-6 : Vee = 5V i 20%, V55 = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
IPSHR Power Save Hold Time (RESET) 10 - - ps
IPSSR Power Save Setup Time (RESET) 1O - - ms
tVH Vcc Hold Time (PS) 5 - - ps
tvs Vcc Setup Time F9 5 - - ps
Note .' tcy =2.5ps (fxTAc--6MHz)
(3) Timing Waveform
----F -e-- tus
RESET --r - tVH /
- "-tPSHR
MCU48-72
TOSHIBA TMP80C50A/40A
4.9.2 Power Down Mode (ll) ...... ALL Data Hold Mode
The operation of oscillation circuit is suspended by setting PS terminal to low level
after gg terminal has been set to low level. Consequently, all data can be held in low
power consumption.
The minimum hold voltage ofVCC in this mode is 3V.
pg terminal is set to high level to resume oscillation after VCC has been reset to 5V,
and then gg terminal is set to high level, thus, the normal mode is restarted
continuously from the statejust before the power down mode (II).
(1) DC Characteristics
TMP80C50AP/C4OAP/C50AU
TMP80C50AP-6/C40AP-6/C50AU-6 2 TOPR = - 40°C to 85°C, VSS = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
VSB2 Standby Voltage (2) 3.0 - 6.0 V
VCC = 5V, VIH = VCC -
ISB2 Standby Current(2) -0.2V,VlL=0.2V 0.5 10 pA
(2) AC Characteristics
TMP80C50AP/C4OAP/CSOAU : VCC = 5v t 10%, Mss = OV
TM P80C50AP-6/C40AP-6/C50AU-6 : va = 5V t 20%, vii = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT
tpsHs Power Save Hold Time (33) 10 - - ps
tpggg Power Save Setup Time (irc) 10 - - ms
tVH Vcc Hold Time (PS) 5 - - ps
tvs Vcc Setup Time (Pg) 5 - - ps
Note : tCY = 2.5r1s(fxTAs, = 6MHz)
(3) Timing Waveform
- - - tvs
- l -e
------_
- - tPSHs
MCU48-73
TOSHIBA TMP80C50AM0A
4.9.3 HALT MODE
HALT INSTRUCTION
OP code is "01H". HALT INSTRUCTION is an additional instruction to the standard
8048/8049 instruction set.
Entry to HALT MODE
On the execution of HALT INSTRUCTION, TMP80C50A/TMP8OC40A enter HALT
Status in HALT MODE
The oscillator continues its operation, however, the internal clocks and internal logic
values just prior to the execution of HALT INSTRUCTION are maintained. Power
consumption in HALT MODE is less than 50% of normal operation. The status of each
pins are described in the following table.
Release from HALT MODE
HALT MODE is released by either of two signals (RESET, INT).
(4.1) RESET Release Mode : An active RESET input signal causes the normal reset
function. TMP80050A/TMP80C40A start the program
at address "OOO H''.
(4.2) I TRelease Mode : An active INT input signal causes the normal
operation.
0 In case of interrupt enable mode (EI MODE), TMP80C50A/TMP80C40A
execute the interrupt service routine, after the execution of one instruction which
is located at the next address after HALT INSTRUCTION.
o In case of interrupt disable mode (DI MODE), TMP80C50A/TMP80C40A
execute normal operation from the next address after HALT INSTRUCTION.
Supply Voltage Range in HALT MODE
The operating supply voltage range and the operating temperature range are same as
in normal operation.
TMP80050AP/C40AP/C50AU : Vcc = 5V i 10%
TMP80C50AP-6/C40AP-6/C50AU-6 .' Vcc = 5V i 20%
MCU48-74
TOSHIBA TMP80C50A/40A
4.9.4 Pin Status In Power Down Mode (I) (II)
PIN NAME STATUS
DBo--DB7
P ~P High impedance
10 17 lnputdisabled
P20-P27
To High Impedance, inputdisabled
T1 Inputdisabled
XTAL1 High impedance
XTALe Output "High" level
RESET, TT Input disabled when oscillator is stopped. Pull-up transistors turn off.
W, EA lnputdisabled when oscillatoris stopped.
E, WR, ALE . .
PROG, P-stN High impedance
4.9.5 Pin Status In HALT MODE
PIN NAME STATUS
DBo--DB7
PIO-ply Values prior to the execution of HALT INSTRUCTION are maintained.
P20--P27
To Status prior to the execution of HALT INSTRUCTION is maintained.
T1 ' lnputdisabled
XTAL1, XTAL2 Continue oscillation
(W9rT,WT Inputenabled
7 EA Inputdisabled
FrROG,FfETs) Output High level
ALE Output "Low" level
MCU48-75
TOSHIBA TMPT'2C50AM0A
5. OSCILLATOR
QUARTZ CRYSTAL
f=1MHzto4MHz :Cl=C2=30pF /
f=4MHzto11MHz : C1=C2=20pF XTAL, (
CI -L. l 2/
CERAMIC RESONATOR JT © i
f=1MHzto3MHz :C1=C2=100pF T 3 Y
f=3MHzto11MHz : C1=C2=3DPF /
c2 it- XTAL2
6. TYPICALCHARACTARISTICS
. Vcc = 5V, Ta = 25°C, unless otherwise noted.
5 10 15 fXTAL (MHZ)
VCc-fMAx_ TYPICAL CURVE
_ wer' '
5 10 15 fXTAL (MHz)
fXTAL-lcc TYPICAL CURVE
-150 -.---"
A" 040989
o 1 2 3 4 5
VouT-IOLTYPICALCURVE
VOUT (V)
1 2 3 4 5 VOUT(V)
-100 ",,A
N/our-lou TYPICAL CURVE
(PORT 1, 2)
MCU48-76
TOSHIBA
TMNi0C50A/40A
tRESET
(ms) 1 2 3 4 5 VOUT(V)
30 ",,,//'"
20 -10 r.,.,..,,-'''"
-15 e.....-----"
3 .-20
0.01 0.02 0.03 0.06 0.1 0.2 0.3 CRESET lore
(pF) (mA)
CREser-tREsErTYPlCAL CURVE VQUHOH TYPICAL CURVE
(DB, CONTROL) 040989
7. OUTLINE DRAWING
7.1 Outline Drawing For TM P80C50AP/-6, TMP80C4OAP/-6
(DIP: Dual Inline Package)
Dwhao..its00
Unit: mm
tOr-lr-I-lr-Tri-lr-Ir-Ter-Tr-trot-tr-Ir-Ir",
0w 15°
LLr1Lri-r1-JcJk-rt-Jt-rTcJL-gt-gcit-JcgLuuaL-rT-l;
13.4i0.
#25 _0 05
l 50.7 i 0.2 l
3.5:03
1.22TYP
0 51M|N 3.5102
il" ll" ‘94-
Note: 1. This dimension is measured at the center of bending point of leads.
2. Each lead pitch is 2.54mm, and all the leads are located within i0.25mm from their
theoritical positions with respect to No.1 and No.40 leads.
MCU48-77
TOSHIBA TMP80C50A/40A
7.2 Outline Drawing For TlVlP80C50AU/-6
(Micro Flat Package)
QFP44-P-1 010A
Unit .' mm
10 0:0 2
1308i0.3
HHHHHUUHUUH
E- co'
1. The above dimensions don't include the burr of package and the residue of tie-bar cut.
The burr ofpackage and the residue of tie-bar cut should be 0.15 mm (Max.).
2. Applied to the lead flat portion.
MCU48-78
TOSHIBA V TMP82C43P
CMOS iNPUT/OUTPUT EXPANDER (TLCS-48C)
TM P82C43P
l. GENERAL DESCRIPTION AND FEATURES
The TMP82C43P is an input/output expander designed specifically to provide a low
cost means of I/O expansion for the TLCS-48C family.
The UC) ports of the TMP82C43P serve as a direct extension of the resident I/O
facilities of the TLCS-4SC microcomputers and are accessed by their own MOVD, ANLD
and ORLD instructions.
F EATU RES
. CMOS LSI for low power dissipation
. Simple interface to TLCS-48C microcomputers
. Four 4-bit I/O ports
. Single 5V supply
0 High output drive
. PIN compatible with intel's 8243
. Extended operation temperature range -400C to 85°C
MCU48-79
TOSH I BA TMP82C43P
2. PIN CONNECTION AND PIN FUNCTIONS
2.1 Pin Connection (Top View)
P50 c: 1 U 24 Cl Vcc
P40 I: 2 23 Cl P51
P41 C 3 22 :1 P52
P42 C4 21 Cl P53
P43 C 5 20 C) P50
tTs" 1: 6 19 Cl P51
PROG 1: 7 18 Cl P62
P23 E 8 17 Cl P63
P22 1: 9 16 C] P73
P21 C 10 15 P72
P20 . 11 14 ii P71
Vss C 12 13 :1 P70
Figure 2.1 DIP Pin Connections
2.2 BLock Diagram
ADDRESS N LATCH PORT4
DECORDER cr" -y/
INPUTBUFFER
=) INSTRUCTION _ RT
DECORDER -l\ LATCH PO 5
PORT2 Git) MULTIPLEXER INPUTBUFFER
PORT 6
PROG - CONTROL =) AND/O
INPUTBUFFER
TEMPORARY , LATCH
REGISTER
LOGIC LATCH
RESET INPUT BUFFER
CIRCUIT
Figure 2.2 Block Diagram
MCU48-80
TOSHI BA TMP82C43P
2.3 Pin Names And Pin Description
PROG (Input)
Clock input. A high to low transistion on PROG signifies that address and
control are available on P20-23, and a low to high transition signifies that data is
available on P20-23.
cg (Input)
Chip Select Input. A high on w inhibits any change of output or internal status.
P20-23 (Input/Output, 3-state)
Four (4) bit bi-directional port contains the address and control bits on a high to
low transition of PROG. During a low to high transition it, contains the data for a
selected output port ifa write operation, or the data from a selected port before the
low to high transition if a read operation.
P40-43, 1350-53, P60-63, P70-73 (Input/Output, 3-state)
Four (4) bit bi-directional I/O ports. May be programmed to be input (during
read), low impedance latched output (after write) or a 3-state (after read). Data on
pins P20-23 may be directly written, ANDed or ORed with previous data.
Vcc (Power)
+ 5 volt supply
VSS (Power)
0 volt supply
MCU48-81
TOSHI BA TMP82C43P
FUNCTIONAL DESCRIPTION
General Operation
The TMP82043P contains four 4-bit I/O ports which serve as an extension of the on-
chip I/O and are addressed as ports 4-7. The following operations may be performed on
these ports.
. Transfer accumulator to port
. Transfer port to accumulator
0 AND accumulator to port
0 OR accumulator to port
All communication between the microcomputer (TMP80049A) and the TMP82C43P
occurs over Port 2 (P20-23) with timing provided by an output pulse on the PROG pin of
the processor. Each transfer consists of two 4-bit nibbles.
A high to low transition of the PROG line indicates that address is present while a
low to high transition indicates the presence of data. Additional TMP82C43P may be
added to the 4-bit bus and chip select signal using additional output lines from the
microcomputer.
Power On Initialization
Initial application of power to the device forces input/output ports 4, 5, 6, and 7 to the
tri-state and port 2 to the input mode. The PROG pin may be either high or low when
power is applied. The first high to low transition of PROG causes device to exit power on
mode. The power on sequence is initiated if Vcc drops below IV.
P21 P20 AEEEEESS P23 P22 INSTRUCTION CODE
0 0 PORT 4 0 0 Read
0 1 PORT 5 O 1 Write
1 O PORT6 1 0 ORLD
1 1 PORT7 1 1 ANLD
MCU48-82
TOSHIBA TMP82C43P
Write Modes
The device has three write modes. MOVD Pi, A directly writes new data into the
selected port and old data is lost. ORLD Pi, A takes new data, OR's it with the old data
and then writes it to the port. ANLD Pi, A takes new data AND's it with the old data
and then writes it to the port. Operation code and port address are latched from the
input port 2 on the high to low transition of the PROG pin. On the low to high transition
of PROG data on port 2 is transferred to the logic block of the specified output port.
After the logic manipulation is performed, the data is latched and outputed. The old
data remains latched until new valid outputs are entered.
Read Mode
The device has one read mode. The operation code and port address are latched from
the input port 2 on the high to low transition of the PROG pin. As soon as; the read
operation and port address are decoded, the appropriate outputs are 3-stated, and the
input buffers switched on. The read operation is terminated by a low to high transition
of the PROG pin. The port (4, 5, 6 or 7) that was selected is switched to the 3-stated mode
while port 2 is returned to the input mode.
Normally, a port will be in an output (write mode) or input (read mode).
If modes are changed during operation, the first read following a write should be
ignored ; all following reads are valid. This is to allow the external driver on the port to
settle after the first read instruction removes the low impedance drive from the
TMP82C43P output. A read of any port will leave that port in a high impedance state.
MCU48-83
TOSHIBA TMP82C43P
4. ELECTRICAL CHARACTERISTICS
4.1 Absolute Maximum Ratings
SYMBOL ITEM RATING
Vcc Vcc Supply Voltage with Respect to GND - 0.5V to + 7.0V
VIN Input Voltage with Respect to GND -0.5V to Vcc+0.5V
PD Power Disspation 250mW
TSOLDER Soldering Temperature (soldering Time 10 sec.) 260C
TSTG Storage Temperature - 65C to + 150C
Tope Operating Temperature - 40C to + 85"C
4.2 D.C. Characteristics (l)
TopR = - 40°C to 85°C, Vcc = 5V i 10% , I/ss = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNITS
" Input LowVoltage -0.5 - 0.8 V
" Input High Voltage 2.2 - Vcc V
V0L1 Output Low Voltage Ports 4-7 IoL=limA - - 0.45 V
VOL2 Output Low Voltage Port7 |0L=20mA - - 1.0 V
V0L3 Output Low Voltage Port2 |0L=0.8mA - - 0.45 V
VOHH Output High Voltage Ports 4-7 lou = --1.2mA 2.4 - - V
V0H21 Output High Voltage Port 2 IOH = - 0.6mA 2.4 - - V
V0H12 Output High Voltage Ports 4-7 IOH = - 0.6mA Vcc - 0.8 - - V
V0H22 Output High Voftage Port2 Iori-- .-0.3mA I/cc-ol, - - V
IIU Input Leakage Port 4-7 VSSEVINEVCC - - -+.10 pA
|IL2 Input Leakage Port 2,3, PROG VssrsNhNeEVcc - - t 10 pA
Vcc = 5V, " = 0.2V,
|cc1 PowerSupply Current(1) V1H=Vcc-0.2V, - - 2 mA
PROG PERIOD = 5115
Vcc = 5v, " = 0.2V,
lccz Power Supply Current (2) Ihr, = Vcc-0.2V, - - 10 pA
PROG =Vcc-0.2V,
IOL Sum of all IOL of 16 Outputs SmA Each pin - - 80 mA
MCU48-84
TOSHIBA TMP82C43P
4.3 DC. Characteristics (ll)
TOPR = - 40°C to 85°C, Vcc = 5V t 20%, I/ss = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNITS
" Input Low Voltage 4.0S VccS 4.5V -0.5 - 0.15Vcc V
VIH Input High Voltage 5.5S VccS 6.0V 0.5Vcc - Vcc V
VOL1 Output Low Voltage Ports 4-7 IOL = 4mA - - 0.45 V
VOL2 Output Low Voltage Port 7 IOL =15mA - - 1.0 V
VOL3 Output Low Voltage Port2 loL=0.6mA - - 0.45 V
VOH12 Output High Voltage Ports 4-7 IOH = - 200PA Vcc - 0.8 - - V
VOH22 OutputHighVoltage Port2 IOH: - 100PA Vcc-0.8 - - V
IQL Sum of all IOL of 16 outputs 4mA Each Pin - - 64 mA
4.4 A.C. characteristics
Tope = - 40°C to 80°C, Vcc = 5V , 20%, Vss = 0V
SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNITS
tA CodeValid Before PROG CL=80pF 100 - - ns
t3 CodeVaIid After PROG CL=20pF 60 - - ns
tc Data Valid Before PROG CL = 80pF 200 - - ns
1.3 Data Valid After PROG CL = 20pF 20 - - ns
tH Floating After PROG CL = 20PF 0 - 150 ns
tK PROG Negative Pulse Width 700 - - ns
tcs 6 Valid Before/After PROG 50 - - ns
tpo Ports 4-7 Valid After PROG CL =100pF - - 700 ns
tip Ports 4-7 Valid Before/After PROG 100 - - ns
tAcc Port 2 Valid After PROG CL = 80pF - - 650 ns
MCU48-85
TOSHIBA TMP82C43P
4.5 Timing Waveform
t t3 tc
«L, A------ -
PORT2 INSTRUCTION FLOAT DATA FLOAT
tAcc ,1 - tH -
PORT2 ji: OUTPUTVALID
pORT4--7 PREVIOUS OUTPUT VALID 0%?ng
M------
PORT4--7 x INPUTVALID
----F tcs - - tcs --
cs --,
MCU48-86
TOSHI BA TM P82C43P
5. OUTLINE DRAWINGS
DIP24t600
Unit:mm
24 13 f
C'TrOr-1r-trOr-nr-Tr-1r-Tr-nr-Tr-1 -; o
L-lk-ik-gk-uc.,';;.'...';.:..'.-., -
14.0:02
32.0202 _
F v-+I-r"-
JP Jrir
__A_ " M.
-----------i---o.
2.03TYP 1.4301 0510.1 _
- @0250? C9
Note : Each lead pitch is 2.54mm. All leads are located within 0.25mm of their true longitudinal
position with respect to No.1 and No.24 leads.
MCU48-87

www.ic-phoenix.com
.

Partno	Mfg	Dc	Qty	Available	Descript
80C35	NEC	N/a	6000	avai	CMOS 8-BIT SINGLE-CHIP MICROCOMPUTER (TLCS-48C)