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82C55 ,CMOS PROGRAMMABLE PERIPHERAL INTERFACE
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82C55
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
TOSHI BA TMP82C55A
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
TMP82C55AP-2/TMP82C55AM-2
TMP82C55AP-1 O/TIVIP82C55AM-1O
l. GENERAL DESCRIPTION AND FEATURES
The TMP82C55A (hereinafter referred to as PPI) is a CMOS high Speed
programmable input/output interface with three 8-bit I/O ports. 241/0 Ports are divided
into two groups (Port A and Port B) which are programmable independently by control
words provided by MPU. The PPI has three operation modes (Mode 0, l and 2) and is
copable of versatile interface between MPU and peripheral devices.
The TMP82055A is fabricated using 'Nshiba's CMOS Silicon Gate Technology.
High Speed Version (TRD = 100ns MAX: TMP82C55AP-10/AM-10)
Low power consumption
2mA Type.
10pA Max. (@SV, Stand-by)
5V i: 10% Single power supply
24 programmable I/O ports
Three operation modes (Mode 0, Mode 1, Mode 2)
Bit set/reset capability
Up to 8 output ports of port B and C are capable of driving a darlington transistor
(Min. - 1.0mA @VOH = 1.5V)
Extended operating temperature: --40 °C to + 85 T
Available 40pin Standard DIP and SOP
MPU85-133
TOSHIBA
TMP82C55A
PIN CONNECTION
BLOCK DIAG RAM
s (TOP VIEW)
PA3 1 V 40 JPA4
PA2C2 39 DPAs
PA1E3 38 DPAG
PAOC4 37 JPA7
Fit 5 36 om
6:: 6 35 JRESET
(GND)V55E 7 34 3Do
A1§8 33 3D1
Aot9 32 JD2
pthr 10 31 303
PC5E 11 30 304
PCsl: 12 29 305
PC4E 13 28 106
PCoE 14 27 307
PC1E15 26 JVcc(+SV)
PC2E16 25 3PB7
PC3E17 24 JPBs
PBoE 18 23 3935
P311119 22 JPB4
PB2C20 21 JPB3
TMP82C55Ap-2/AP-10
TMP82C55AM-2/AM-10
D7-rDo
BIDIRECTIONAL DATA
READ WRITE CONTROL LOGIC
----- DATA BUS BUFFER
GROUP A
CONTROL
INTERNAL 8-BIT BUS
GROUP B
CONTROL
GROUP A
GROUP B
PORTA I PORTC
PORTC IPORT B
:(it:iii:
PA7-- PAQ PCr- PC4
IIO IIO
PC3--PCo PB7--PBo
MPU85-134
TOSHIBA
TMP82C55A
4. PIN NAMES AND PIN FUNCTIONS
in t/O t t
Pin Name Numher pu U pu Function
of Pin 3-state
Tstate bidirectional 8-bit data bus. Used for data transfer with
Do-Dy 8 IIO S-state MPO. Also, used for transfer of control words to PPI and status
information from PPI.
3-state 8-bit I/O Port A.
pA0~pA7 8 I/O 3-state Operation mode and input/output configuration are defined by
software. Port A contains the output latch buffer and input latch.
3-state 8-bit l/O Port B.
PBo~PBy 8 1/0 3-state Operation mode and input/output configuration are defined by
software. Port B contains the output latch buffer and input latch.
3-state 8-bit l/O Port C.
Operation mode and input/output configuration are defined by
software. Port C can be divided into two 4-bit ports by the mode
PC ~PC 8 I/O 3-state .
0 7 control and also, used as the control signal for PortA and Part B. In
this case, 3 bits of PCo to PC2 are used for Port B and 5 bits of PC3 to
PC7 for PortA.
Chip selectinput.
E3 1 In ut When this terminal is at "L" level, data transfer PPI and MPU
p becomes possible. At "H" level, the data bus is placed in the high
impedance state and control from the processor is ignored.
- Read signal.
RD 1 Input When this terminal is at "L" level, data that is input into the port is
transferred to MPU.
Write signal.
WR l Input When this terminal is at "L" level, data or control word is written
into PPI from MPU.
A A 2 Input Used for selecting Port A, B, C and the control registers. Normally,
(), 1 this terminal is connected to low order 2 bits ofthe address bus.
When this terminals is at "H" level, all internal registers including
RESET 1 Input the control register are cleared. In addition, all ports (Port A, B, C)
are placed in the input mode (high impedance) of mode 0.
Vcc 1 Power Supply 5V
l/ss 1 Power Supply GND
MPU85-135
TOSHIBA TMP82C55A
FUNCTIONAL DESCRIPTION
The PPI is a programmable peripheral interface device with three 8-bit ports (Port A,
B and C) and two control registers. 24 1/0 ports are divided into 12-bit group A and
group B. Group A consists of Port A and high order 4 bits of Port C, while Group B
consists of Port B and low order 4 bits of Port C. Each group is independently
programmable by control words provided from MPU. There are three operation modes
available for the PPI. In mode o, two 8-bit I/O ports and two 4-bit I/O ports can be
programmed as input or output ports, respectively. In mode 1, 24 1/0 ports are divided
into Group A and Group B. 8 bits of each group are used as input or output port and of
the remaining 4 bits, 3 bits are used as handshaking and interrupt control signal. Mode
2 is applicable only to group A and the ports are used as a bidirectional 8-bit data bus
and 5-bit control signal. In case of Port C being used as the output, any bits of Port C can
be set/reset.
There are two control registers; one is used for mode setting and the other for bit
set/reset control. The control registers can only be written into. Further, when the reset
input (RESET) becomes "I", the control registers are reset and all I/O ports are placed in
input mode (high impedance status).
Table 5.1 Basic Operation of TMP82C55A
A1 A0 CT; W 7R Function
0 o 0 o 1 Data bus _ Port A
O 1 O 0 1 Data bus - Port B
1 o 0 0 1 Data bus _ Port C
0 0 0 1 0 Port A - Data bus
0 1 0 1 0 Port B - Data bus
1 o o 1 0 Port C - Data bus
1 1 0 1 0 Control register _ Data bus
X M 1 x X Data bus = 3-state
x x 0 1 1 Data bus = 3-state
1 1 0 O 1 inhibition of combination
MODE SELECTION
There are three basic modes of operation that can be selected by control words.
Mode O-Basic I/O (Group A, Group B)
Mode I-Strobe input/Strobe output (Group A, Group B)
Mode 2-Tw0-way bus (Port A only)
Operation modes for Group A and Group B can be independently defined by the
control word form the MPU. If D7 is set to "I" in writing a control word into the PPI,
operation mode is selected, while of D7 = "O", the set/reset function for Port C is selected.
MPU85-136
TOSHIBA
5.1.1 Control word to define operation mode
TMP82C55A
Figure 5.1 shows the control words to define operation mode of the TMP82C55A.
Control word
1 GroupAControl Group BControI
D7 D5 I Ds l D4 l D3 D2 1 D1 1 Do
L Input/output selection of low
order 4 bits of Port C
'0' = Output
'I'--lnput
lnput/output selection of Port B
'0'=Output
'I' = Input
Mode selection of Group B
'o' = Mode 0
'I' = Mode 1
Input/output selection of high
order 4 bits of Port C
'0'=Output
'1'=Input
Input/output selection of Port A
'o = Output
'I' = Input
1= Designation of mode set flag
Mode Selection Group A
'o' = Mode 0
0 O = Mode 0
0 1 = Mode 1
1 x = Mode 2
x: Don't care
Figure 5.1 Control Word for Mode Selection
MPU85-137
TOSHIBA TMP82C55A
5.1.2 Port C bit set/reset control word
Any bit of 8 bits of Port C can be set/reset by Port C bit set/reset control word. Fig. 5.2
shows the Port C bit set/reset control word.
ControlWord
(o7lD6)DssiD4iD3irs2lo1iool
l L Bit set/reset selection
Don't care "0" = Reset
"1 " = Set
5:21:55: g o o o PCo
O 0 1 PC1
0 1 0 PC2
0 1 1 PC3 Bit selection
1 0 0 PC:
1 0 1 PCs
1 1 0 PCs
1 1 1 PC7
Figure 5.2 Control Word for Bit Set/Reset
5.2 OPERATION MODES
5.2.1 Mode0(Basic1/O)
This functional configuration is used for simple input or output operations. No
'handshaking' is required and data is simply written to or read from a specified part.
Output data to the ports from MPU are latched out but input data from the ports are not
latched.
In Mode 0, 24 1/0 terminals are divided into four groups of Port A (8 bits), Port B (8
bits), high order 4 bits of Port C and low order 4 bits of Port C. Each port can be
programmed to be input or output. The configuration of each port are determined
according to the contents of Bit 4 (D4), 3 (D3), 1 (D1) and 0 (D0) of the control word for
mode selection.
The 1/0 configuration ofeach port in Mode 0 are shown in Table 5.2.
MPU85-138
TOSHI BA TMP82C55A
Mode Setting Control Word Port C Port C
PortA PortB
D4 D3 D, Do (PC7~PC4) (PC3--PC0)
O O 0 0 Out Out Out Out
0 0 O 1 Out Out Out In
0 0 1 0 Out Out In Out
0 O 1 1 Out Out In In
0 1 O 0 Out In Out Out
0 1 0 1 Out In Out In
0 1 1 0 Out In In Out
0 1 1 1 Out In In In
1 0 0 0 In Out Out Out
1 0 0 1 In Out Out In
1 0 1 0 In Out In Out
1 0 1 1 In Out In In
1 1 0 0 In In Out Out
1 1 0 1 In In Out In
1 1 1 0 In In In Out
1 1 1 1 In In In In
Figure 5.3 Port Definition in Mode 0
5.2.2 Mode 1 (Strobe I/O)
In Mode l, input/output of port data is performed in conjunction with the strobe
signals or 'handshaking' signals. Port C is used to control Port A or Port B.
The basic operatings in Mode 1 are as follows:
0 Mode 1 can be set for two groups of Group A and Group B.
0 Each group consist of 8-bit data port and 4-bit control/data port.
q The 8-bit data port can be set as input or output port.
0 The control/data port is used as control or status of the 8-bit data port.
(1) When used as the input port in Mode 1:
0 BIN (Strobe Input)
At "O", input data is loaded in the internal input latch in the port.
In this case, a control signal from MPU is not concerned and data is input from
the port any time. This data is not read out on the data bus unless MPU executes
an input instruction.
q IBF (Input Buffer Full F/F Output)
When data is loaded in the internal input latch from the port, this output is set
to "I''. IBF is set CI'') by STE input being reset and is reset ("0") by the rising edge
ofm input.
MPU85-139
TOSHIBA TMP82C55A
. INTR (Interrupt Request Output)
Used for the interrupt process of data loaded in the internal input latch. When
Bnrg input is at "o" if INTE (INTE flag) in the PPI is in the enabled state CI") , IBF
is set to "I''. INTR is set to "I" immediately after the rising edge of this CTT, input
and reset to "o" by the falling edge ofm input.
The INTE flag of Group A and Group B are controlled as follows:
INTEA-Control by bit set/reset of P04
INTEB-Control by bit set/reset of PC2
(2) When used as the output port in Model:
D OBF (Output Buffer Full F/F Output)
This is a flag which shows that MPU has written data into a specified port. OBF
is set to becomes "o" at the rising edge ofWTt signal and is set to "I'' at the falling
edge of ACK (Acknowledge input) signal.
0 ACK (Acknowledge Input)
ACK signal is sent to the PPI as a response from a peripheral device taht
received data from the port.
0 INTR (Interrupt Request Output)
When a peripheral device received data from MPU, INTR is set to "I" and the
interrupt is requested to MPU. Hm signal is received when INTE flag is in the
enable state, CTBT? is set to "I" and INTR signal becomes "I" immediately after the
rising edge ofAC_K signal. Further, INTR is reset at the falling edge ofw-R signal
when data is written into the PPI by MPU.
The INTE flags of Group A and Group B are controlled as follows:
INTEA-Control by bit set/reset of pa,
INTEB-Control by bit set/reset of PC2
MPU85-140
TOSHIBA TMP82C55A
MODE 1 (PORT A)
CONTROL WORD PA,- PAa ӣ3
Dr Ds Ds 04 D3 D2 D, Do yii,iri PC, -ST-Bh-
_1Tir77raFTx-F- L.. L-d PCs - IBFA m
PCs, PC7 - PCs - INTRA
o = OUTPUT RD-o-c IBF
1= INPUT PC5~PC7 sal/O /"""'
MODE1 (PORT B) INTR l
CONTROLWORD P87-- P80 «+8 RD
D, D5 D5 Da 03 D2 D, Do [ith-i'', PCe -STRB I l
unma- L-B-J P(h--ilBFS $851 x3 \1
-INTRB Dr-Do -------- =y -
RD -c Co
Figure 5.4 Example of Strobe Input in Mode1
MODE 1 (PORT A)
CONTROLWORD PA7--PA0 74,3
D7 Ds Ds Do D3 Dr, D1 Do PC) - OBFA
-ACKA -
WR T/u-fr---"-".""-
PtU, PCS --.- INTRA 03;
0 = OUTPUT WR-o-c 2 1
1: INPUT PCs-PCs -rr_l/ty
MODE1(PORTB) LL,...d "
CONTROLWORD PBy~ P30 8 INTR
D7 Dis Ds Ch: D3 D2 01 Do r____1 PC OBFB
IIIIIInI :ng J: PC m PORT
-.... OUTPUT X
- INTRB
WR----
Figuire 5.5 Example of Strobe Output in Mode1
MPU85-141
TOSHIBA
TMP82C55A
CONTROL WORD
D7 D5 Ds D4 D3 D2 01 Do
LTIilt)_li"/_irlrrrj_T,
OUTPUT -
INPUT RD “3
PA7 _ PAO
PC4 ' PCs
P87 _ P80
-ai7ii
-rcRYT
- INTRA
<3» IIO
---TiiTiT
- IBFB
- INTRB
PORT A (STROBE OUTPUT)
PORT B (STROBE INPUT)
Figure 5.6
Example of Port A Output,
Port B Input in Model
5.2.3 Mode 2 (Strobed Bidirectional Bus IIO)
PAr-- PAO 2,
iiTo---ic PCa em
CONTROLWORD PCs - IBFA
D, De Ds Da D3 ch, DI Do PCs --» lNTRA
Pc6~Pc7
uo
-Trol1IlL1_lr/0ril(TyT 2
PC6, PC; PB7-PBo 7*
0 = OUTPUT _ W.
1 = iNPUT WR---: PC} -OBF8
PC; -ACKB
PCO - INTRB
PORT A (STROBE INPUT)
PORT B (STROBE OUTPUT)
Figure 5.7 Example of Port A Input,
Port B Output in Model
In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a
peripheral device. This mode is applicable only to Group A, which consists of an 8-bit
bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits of Port C). The
bidirectional bus (Port A) has both the internal input and output registers. When group
A is set in Mode 2, Group B can be set independently. There are 5 control signals as
follows when Group A is used in Mode 2.
o UBF (Output buffer Full F/F Output)
When MPU writes data into of Port A, OBF is set to "O'' to inform a peripheral
device that the PPI is ready to output data. However, Port A is kept in the floating
(high impedance) state until ACK input signal is received.
0 ACK (Acknowledge Input)
When ACK signal is set to "O", the data of the 3-state output buffer of Port A is
send out. HACK signal is at "I", Port A is in the high impedance state.
It STB (Strobe Input)
When STB input is set to "o", the data from peripheral devices are held in the
input latch. When the active RT signal is input into the PPI, the latched input
data are output on the system data bus (D7-D0).
MPU85-142
TOSHIBA TMP82C55A
0 IBF (Input Buffer Full F/F Output)
When data from peripheral devices are held in the input latch, IBF' is set to "I''.
0 INTR (Interrupt Request Output)
INTR is the output to request the interrupt to MPU and its function is the same
as that in Mode 1. There are two interrupt enable flip-flop (INTE), INTEl
corresponds to INTEA in Mode 1 output and INTE2 to INTEA in Mode 1 input.
INTE 1-Used to generate INTR signal in conjunction with OBF and ACR
signals, and is controlled by PC6 bit set/reset.
INTE 2-Used to generate INTR signal in conjunction with IBF and STB signals,
and is controlled by PC4 bit set/reset.
Fig. 5.8 shows the operating example and the timing diagram in Mode 2.
INTRA -
INTR ) A
OBFA L,..-,..;.;
ACKA ACK
l-if-dt
STBA L I
IBFA \f
RH PcchOI/ow» PORTA .t.--.--.--- -EEEiEiyEEiErEry ---
iTh- l f'
Figure 5.8 Operating Example in Mode 2
MPU85-143
TOSHIBA
TMP82C55A
Control Word in Mode 2
Dy D6 D5 D4
1 l x l x
x=Don't care
D3 De D1 Do
Lx l 1/0 1 1/0 I 1/0J
PC2--PCo
L_-__., Group B Mode
0=Output
1=lnput
0=Output
1: Input
0 = Mode 0
1=M0de1
Figure 5.9 Control Word and Configuration in Mode 2
Control Words
D4 D3 D2 DI Do
[ol1luoj
PC2--PCo A---------
0 Output
1 Input
D7 D6 D5
(1lolxl
PA7~PA0
PC2-PCo
PB7~PBo
--v INTRA
--v OBFA
-----Ec-Ka
----rtl7
--e IBFA
<+>IIO
Port A- Mode 2 I/O
Port B - Mode 0
Control Words
PA7--PA0
PB7~PBO
- [NTRA
---- OB-FA-
---- Tit77
--STi7
---- IBFA
- t5Tw7
-----TttB
--e INTRB
Port A- Mode 2
Port B - Mode O
Figure 5.10 Examples in Combination with Mode 2 and Other Mode
MPU85-144
TOSHIBA
TMP82C55A
5.2.4 Precautions for use in mode 1 and 2
When used in Mode 1 and 2, bits which are not used as control or status in Port C can
be used as follow.
Ifprogrammed as the input, they are accessed by normal Port C read.
If programmed as the output, high order bits of Port C (PC7-PC4) are accessed using
the bit set/reset function. As to low order bits of Port C (PC3-PC0), in additions to access
by the bit set/reset function, only 3 bits can be accessed by normal writing.
5.3 READING PORT C STATUS
When Port C is used as the control port, that is, when Port C is used in Mode 1 or
Mode 2, the status information of the control word can be read out by a normal read
operation of Port C.
Table 5.2 Status Word Format of Port C
Mode D7 De Ds D4 D3 D2 D1 D0
Mode1lnput l/O l/O IBFA INTEA INTRA INTEB IBFB lNTRB
Mode 1 Output OBFA INTEA 1/0 l/O INTRA INTEB OBFB INTRB
Mode 2 OBFA INTE1 IBFA INTEZ INTRA By Group B Mode
MPU85-145
TOSHIBA TMP82C55A
6. ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
Symbol Item Rating Unit
Vcc Supply Voltage -0.5 to 7.0 V
VIN InputVoltage --0.5to Vcc+0.5 V
PD Power Dissipation 250 mW
TSOLDER Soldering Temperature (10 sec) 260 'C
TSTG Sto rage Temperature - 65 to +150 'C
TOPR Operating Temperature - 40 to + 85 'C
6.2 DC ELECTRICAL CHARACTERISTICS
TA= --40''C to + 85''C, I/cc = 5V i 10%, vss = 0V
SYMBOL ITEM TEST CONDITION MIN, TYP. MAX. UNIT
" Input Low Voltage -0E - 0.8 V
" InputHigh Voltage 2.2 - Vcc+0.5 V
VOL Output Low Voltage l0L=2.5mA - - 0.45 V
VOHI Output High Voltage lou = -400PA 2.4 - - V
VOH2 Output High Voltage lor, = -100pA Vcc-0.8 - - V
In Input Leak Current o:v.~:vcc - - :10 pA
Output Leak Current < <
- __ V - - t A
ILO (High Impedance State) 0 VOUT CC 10 ll
(Note) Darlington Drive VEXT=1.SV
- 1. - - .
IDAR Current REXT= 1.1kQ 0 S 0 mA
lccl Operating Supply l/Ocycle Time - 2.0 5.0 mA
Current lysec
- c; : Vcc-0.2V
ICC; 2:22”? Supply VIH 2 Vcc-0.21/ - - 10 pA
Viris 0.2V
Note: Applied for optional 8 I/O terminals in Port B and Port C.
MPU85-146
TOSHIBA TMP82C55A
6.3 AC ELECTRICAL CHARACTREISTICS
TA = -40''C to + 85'C ' Vcc = 5V 110%, vss = 0V
SYMBOL PARAMETER AP-2/AM-2 AP-IO/AM-IO UNIT
MIN. MAX. MIN. MAX,
tAR Address set-uptime forA15fail 0 - 0 - ns
tRA Address hold time forATjrise O - O - ns
mm AT5 pulse width 160 - 150 - ns
tRD Delay fromR75fiwto decided data output - 140 - 100 ns
tDF Time from W rise to data bus floating 0 40 O 40 ns
th Time fromlTr5orWmrise to nextAt5orW/Afal) 200 - 150 - ns
tAw Add ress set-up time for WR fall 0 - 0 - ns
tWA Address holding time forVWrise 0 - 0 - ns
tww WA pulse width 120 - 120 - ns
tow Busdata set-uptime forWCRrise 100 - 100 - ns
tWD Busdata holdingtimeforihmrise 0 - O - ns
tws Delay from i7R" rise to decided data output - 350 - 350 ns
tm Portdata set-up time forrtTDfall 0 - O - ns
tHR Portdata holding time forkl5rise O - 0 - ns
tAK A_C? pulse width 300 - 300 - ns
tsr Ttk" pulse width 350 - 350 - ns
tps Portdata set-uptimeforfmfrise O - 0 - ns
tpH Portdata holding time for9mrise 150 - 150 - ns
tAD Delay from mfall to decided data output - 300 - 300 ns
tKD 'fF‘iCZerrgom 7itTk' rise up to port (Port A in Mode 2) 25 250 20 250 ns
twog Delay fromWTtrise tot5lTtiall - 300 - 300 ns
tAog Delay from/TtTdfiw tomrise - 350 - 350 ns
tws Delay from sTéfan to IBF rise - 300 - 300 ns
tmg Delay fromMfall tomrise - 300 - 300 ns
' tan Delay from Kr5fall to INTR fall - 400 - 400 ns
tSIT Delay from TCK- rise to INTR rise - 300 - 300 ns
tAlT Delay from -/TtT4 rise to INTR rise - 350 - 350 ns
tWIT Delay from Vrm rise to INTR - 450 - 450 ns
Note 2 1. When the power supply is burned ON, reset pulse duration must be active for at least 500
ns or more.
2. AC Measuring Point Input Voltage VIH--- 2.4V,Vu, = 0.45V
Output Voltage Vou = 2.2V, VOL = 0.8V
CL = 150pF.
MPU85-147
TOSHIBA TMP82C55A
6.4 CAPACITANCE
TA = 25''C , Vcc = I/ss = 0V
SYMBOL ITEM TEST CONDITION MIN. TYP. MAX. UNIT
CIN Input Capacitance fc=1MHz - - 10 pF
COUT Output Capacitance (*) - - 20 pF
(*) : All terminals except that to be measured should be earthed.
MPU85-148
TOSHIBA TMP82C55A
7. TIMING DIAGRAM
INPUT OPERATION
Ts, A1, A0
Dr-Do --------------
OUTPUT OPERATION
Tis, A1, A0
OUTPUT
OPE RATION
tPS - tPH '
IN PUT PORT "
---tSIT
+tRITj
a 4H tRR
RD , f
Figure 7.1 Timing Diagram
MPU85-149
TOSHIBA
TMP82C55A
OUTPUT
PORT DATA
OUTPUT OPERATION
--tww -
--twoB-
PERIPHERAL
MODE 2
BIDIRECTION
OPERATION
tww ---F
-.-.le...-.l.l.-_.--..c-t-
- tAos
Figure 7.2 Timing Diagram
tac tKD
MPU85-150
TOSHIBA
TMP82C55A
8. PACKAGE DIMENSION
8.1 PLASTIC PACKGE
DlP40-P-600
Unit : mm
r-hr-Ir-ni-Or-it-Tr-Ir-Orchestre),-,).-?")
Luc.Jk-gL-Ji-lu.ucJclt-lC-lt-JcJcJuu=dLut-lcJt-3cr
0v~15°
13 4:0.2
50.7 $0.2
L22TYP
Note: Each lead pitch is 2.54mm, and all the leads are located witchin -+c0.25rnrn from their
theoretical positions with respect to No.1 and No.4 leads.
MPU85-151
TOSHIBA
8.2 40PIN SMALL OUTLINE PACKAGE
SSOP40-P-450
'ii)yaajiiiijjpa2i
iiyv)'tii,i,?ee''_
03510.1 1.1STYP
Lty_sd QDJSM)
1.15TYP
I 27.5102
o.19:o.1|!2.4
0.8t0.2
(450mi I)
TMP82C55A
Unit : mm
MPU85-152
TOSHIBA
TMP8255A
PROGRAMMABLE PERIPHERAL INTERFACE
TMP8255AP-5
1. GENERAL DESCRIPTION AND FEATURES
The TMP8255A (hereinafter referred to as PPI) is a high Speed programmable
24 I/O ports are divided into two
groups (Port A and Port B) which are programmable independently by control words
provided by MPU. The PPI has three operation modes (Mode 0, 1 and 2) and is capable of
versatile interface between MPU and peripheral devices.
input/output interface with three 8-bit I/O ports.
(1) 5V d: 5% Single power supply
(2) 24 programmable I/O ports
(3) Three operation modes (Mode o, Mode 1, Mode 2)
(4) Bit set/reset capability
2. PIN CONNECTIONS (TOP VIEW)
(GND)Vsst
”\lo‘thN—I
JRESET
JVcc(+5V)
TMP8255AP-5
MPU85-153
TOSHIBA TMP8255A
3. BLOCK DIAGRAM
BIDIRECTIONAL DATA
READ WRITE CONTROL LOGIC
DATA BUS BUFFER
GROUPA GROUP B
CONTROL CONTROL
INTERNAL 8-BIT BUS
At-----
RESET -----
GROUPA GROUPB
PORTAIPORTC PORTCIPORTB
1/0 l/O l/O i/O
PA7~PAO PC7~PC4 PC3~PCO PB7~PBO 050489
MPU85-154
TOSHIBA TMP8255A
4. PIN NAMES AND PIN FUNCTIONS
Number Input/Output
. Function
of Pin 3-state
Pin Name
I/O 3-state bidirectional 8-bit data bus.
Do-D; 8 Used for data transfer with MPU. Also, used for transfer of control
3-STATE . '
words to PPI and status information from PPI.
" 3-state 8-bit 1/0 PortA.
PA7--PA0 8 3-STATE Operation mode and input/output configuration are defined by
software. PortA contains the output latch buffer and input latch.
JO 3-State 8-bit JO Port B.
PB7~PBo 8 Operation mode and input/output configuration are defined by
3-STATE . .
software. Port B contains the output latch buffer and Input latch.
3-state 8-bit " Port C.
Operation mode and input/output configuration are defined by
1/0 software. Port C can be divided into two 4-bit ports by the mode
P ~PC 8 .
C7 0 3-STATE control and also, used as the control signal for Port A and Port B. In
this case, 3 bits of PCo to PC2 are used for Port B and 5 bits of PC3 to
PC7 for Port A.
Chip select input.
tS 1 Input When this terminal is at "L" level, data transfer PPI and MPU
becomes possible. At "H" level, the data bus is placed in the high
impedance state and control from the processor is ignored.
Read signal.
W 1 Input When this terminal is at "L'' level, data that is input into the port is
transferred to MPU.
Write signal.
FNTt 1 Input When this terminal is at "L" level, data or control word is written
into PPI from MPU.
A0, A1 2 Input Used for selecting Port A, B, C and the control registers. Nurmally,
this terminal is connected to low order 2 bits ofthe address bus.
When thisterminal isat "H" level, all internal registers including the
RESET 1 Input control register are cleared. in addition, all ports (Port A, B, C) are
placed in the input mode (high impedance) of mode 0.
Vcc 1 Supply 5V
V55 1 Supply GND
MPU85-155
TOSHIBA TMP8255A
FUNCTIONAL DESCRIPTION
The PPI is a programmable peripheral interface with three 8-bit ports (Port A, B and
C) and two control registers. 24 I/O ports are divided into 12-bit group A and group B.
Group A consists of Port A and high order 4 bits of Port C, while Group B consists of Port
B and low order 4 bits of Port C. Each group is independently programmable by control
words provided from MPU. There are three operation modes available for the PPI. In
mode 0, two 8-bit I/O ports and two 4-bit I/O ports can be programmed as input or output
ports, respectively. In mode 1, 241/0 ports are divided into Group A and Group B. 8 bits
ofeach group are used as input or output port; and of the remaining 4 bits, 3 bits are used
as handshaking and interrupt control signal. Mode 2 is applicable only to group A and
the ports are used as a bidirectional 8-bit data bus and 5-bit control signal. In case of
Port C being used as the output, any bits of Port C can be set/reset.
There are two control registers; one is used for mode setting and the other for bit
set/reset control. The control registers can only be written into. Further, when the reset
input (RESET) becomes "1", the control registers are reset and all I/C) ports are placed in
input mode(high impedance status) .
Table 5.1 Basic Operation of TMP8255A
A1 A0 cs W m Function
0 0 O 0 1 Data bus 6-- Port A
0 1 0 0 1 Data bus _ PortB
1 0 O 0 1 Data bus E-- PortC
0 0 o 1 0 Port A F- Data bus
0 1 O 1 0 Port B k- Data bus
1 O 0 1 0 PortC _ Data bus
1 1 0 1 0 Control register e- Data bus
x x 1 x x Data bus = 3-state
X x 0 1 1 Data bus = 3-state
1 1 o 0 1 inhibition of combination
0 50489
MODE SELECTION
There are three basic modes of operation that can be selected by control words.
Mode O-Basie I/O (Group A, Group B)
Mode 1-Strobe input/Strobe output (Group A, Group B)
Mode 2-Two-way bus (Port A only)
Operation modes for Group A and Group B can be independently defined by the
control word from the MPU. If D7 is set to "1" in writing a control word into the PPI, on
operation mode is selected, while of D7 = "0", the set/reset function for Port C is selected.
MPU85-156
TOSHIBA
TMP8255A
5.1.1 Control word to define operation mode
Figure 5.1 shows the control words to define operation mode of the TMP8255A.
Control Word
Group A Condtol
Group B Control
D5[D5|Da[Dg
D2 l D1 I
1: Designation of mode set flag
Input/output selection of low
order 4 bits of Port C
'0' =Output
'1' = lnput
In put/output selection of
Port B
'0' = Output
'1' = lnput
Mode selection of Group B
'0' = Mode 0
'1' = Model
In put/output selection of high
order 4 bits of Port C
'O' = Output
'1' = Input
Input/output selection of
'0' = Output
'1' = Input
Mode Selection Group A
'0' =Mode 0
00=Mode0
01=Mode1
1x=Mode2
x: Don'tcare
Figure 5.1 Control Word for Mode Selection
MPU85-157
TOSHIBA TMP8255A
5.1.2 Port C bit set/reset control word
Any bit of8 bits of Port C can be set/reset by Port C bit set/reset control word.
Figure 5.2 shows the Port C bit set/reset control word.
Control [Word
FiDs)DsiD4iD3-lro2lD1TDpi
L Bit set/reset selection
Don't care "0" = Reset
"1" = Set
1511822233369 0 o 0 PCo
O O 1 PC}
0 1 O PC2
O 1 1 PC3 Bit selection
l O 0 PCs
1 0 1 PCs
1 1 0 PCs
1 1 1 PC?
Figure 5.2 Control Word for Bit Set/Reset
5.2 OPERATION MODES
5.2.1 Mode 0 (Basic i/O)
This functional configuration is used for simple input or output operations. No
'handshaking' is required and data is simply written to or read from a specified part.
Output data to the ports from MPU are latched out but input data from the ports are not
latched.
In Mode 0,241/0 ports are divided into four groups of Port A (8 BITS), Port B (8 bits),
high order 4 bits of Port C and low order 4 bits of Port C. Each port can be programmed
to be input or output. The configuration of each port are determined according to the
contents of Bit 4 (D4), 3 (D3), 1 (D1) and 0 (D0) of the control word for mode selection.
The 1/0 configuration of each port in Mode 0 are shown in Table 5.2.
MPU85-158
TOSH I BA TMP8255A
Node Setting ControIWord PortA PartC Port B PortC
D4 03 D1 Do (PC7~PC4I (PC3-PCo)
0 0 O 0 Out Out Out Out
0 O 0 1 Out Out Out In
0 0 1 0 Out Out In Out
0 0 1 1 Out Out In In
0 1 O 0 Out In Out Out
0 1 O 1 Out In Out In
0 1 1 0 Out In In Out
0 l 1 1 Out In In In
1 O O 0 In Out Out Out
1 O 0 1 In Out Out In
1 0 l 0 In Out In Out
1 0 1 1 In Out In In
1 1 O 0 In In Out Out
1 1 O 1 In In Out In
1 1 1 0 In In In Out
1 1 1 1 In In In In
Figure 5.3 Port definition in Mode 0
5.2.2 Mode1(StrobeI/O)
In Mode 1, input/output of port data is performed in conjunction with the strobe
signals or 'handshaking' signals. Port C is used to control Port A or Port B,
The basic operatings in Mode 1 are as follows:
0 Mode 1 can be set for two groups of Group A and Group B.
0 Each group consist of 8-bit data port and 4-bit control/data port.
. The 8-bit data port can be set as input or output port.
0 The control/data port is used as control or status of the 8-bit data port.
(1) When used as the input port in Model:
0 ST? (Strobe Input)
At "0", input data is loaded in the internal input latch in the port.
In this case, a control signal from MPU is not concerned and data is input from the
port any time. This data is not read out on the data bus unless MPU executes an
input instruction.
It IBF (Input Buffer Full F/F Output)
When data is loaded in the internal input latch from the port, this output is set
to "1". IBF is set ("1") by STB input being reset and is reset ("0") by the rising edge
ofrI5 input.
MPU85-159
TOSHIBA TMP8255A
. INTR (Interrupt Request Output)
Used for the interrupt process of data loaded in the internal input latch. When
Silt input is at "0" ifINTE (INTE flag) in the PPI is in the enabled state ("1") ,IBF
is set; to "1". INTR is set to "1" immediately after the rising edge of this gTfB input
and reset to "0" by the falling edge offt-D input.
The INTE flags of Group A and Group B are controlled as follows:
INTEA-Control by bit set/reset of PC4
INTEB-Control by bit set/reset of P02
(2) When used as the output port in Mode 1:
ct OBF (Output Buffer Full F/F' Output)
This is a flag which shows that MPU has written data into a specified port. OBF
is set to becomes "0" at the rising edge ofWR signal and is set to "1" at the falling
edge of ACK (Acknowledge input) signal.
0 ACK (Acknowledge Input)
ACK signal is sent to the PPI as a response from a peripheral device that
received data from the port.
0 INTR (Interrupt Request Output)
When a peripheral device received data from MPU, INTR is set to "1" and the
interrupt is requested to MPU. IfECft' signal is received when INTE flag is in the
enable state, tfrfl? is set to "1" and INTR signal becomes "1" immediately after the
rising edge ofm signal. Further, INTR is reset at the falling edge oCWTt signal
when data is written into the PPI by MPU.
The INTE flags of Group A and Group B are controlled as follows:
INTEA-Control by bit set/reset of PCS
INTEB-Control by bit set/reset of PC2
MPU85-160
TOSHIBA
TM P8255A
MODE 1(PORTA)
CONTROLWORD PA7~PAO <+8
D, Dis Ds Da D3 D2 D; Do {INEE'} pca --ffrgyN
L.., --u PCs - EFA
PCs, PC7 -_ PC, - INTRA
0 = OUTPUT RD --FG 2
1: INPUT PC5~PC7 -l/O
MODE 1 (PORT B)
CONTROLWORD pB7~pBO #8
D7 D6 D5 Do De D2 D1 DO Pi,ii] PCs -STR8
IIIIIIIII L“ --u PC; am
_ - PC - iNTRB
RD-s-c 0
S B -1,-..,/"T'-"""""'""-i'
INTR l /"""""
m /‘ (,
KEEN X1 _,
or-oo--------'::)'. ------
Figure 5.4 Example of Strobe Input in Mode1
MODE 1 (PORT A)
CONTROLWORD PAr-- PAg +3
D, D5 Ds D4 D3 Dz D1 Do PC, -OBFA
---ACKA H.
PCs, PCs - - INTRA W
0 = OUTPUT WR-c: 2 l
1 = INPUT PCa-PCs -l/O
MODE 1 (PORT B) Id-l l
CONTROLWORD P87~PBO #8 INTR
D7 05 Ds Da D3 D2 D, Do PC1 - OBFB
II-IIIIII! - Mr/cg PORT
OUTPUT X
- - INTRB
WR--ic:
Figure 5.5 Example of Strobe Output in Mode1
MPU85-161
TOSHIBA TMP8255A
PA,~ PA0 J, PA, ' PAO -,,gt
mac PC; ----t5iTF7 R7060 PCa -STBA
CONTROLWORD PCs -ACKA CONTROLWORD PCS - IBFA
D7 De Ds D4 D; D2 D, Do PCa -iNTRA D, De Ds DA D3 D2 D, Do ch a INTRA
F_ljFlT1/I0l]j_ljjryr. 2 IIEIII-I-"l 2
pc4~Pc5wuo Pc5~Pc7v>uo
PCa, PCs PBr-- PBa - PC6, PC7 P87 - P80 _
0 = OUTPUT - (J o = OUTPUT -
I = INPUT RD-- PC2 f-STBB 1 = INPUT WR----c PC, -OBFB
PC, - KBFB PC; --A k8
PCo _ INTRB PCo - INTRB
PORTA(STROBE OUTPUT) PORTA(STROBE INPUT)
PORTB (STROBE INPUT) PORTE (STROBE OUTPUT)
Figure 5.6 Example of PortAoutput, Figure 5.7 Example of PortAlnput,
Port B Input in Model Port B Output in Model
5.2.3 Mode 2 (Strobed Bidirectional Bus l/O)
In this mode, Port A is used as 8 bits bidirectional bus for data transfer with a
peripheral device. This mode is applicable only to Group A, which consists of an 8..bit
bidirectional bus (Port A 8-bit) and 5-bit control signals (high order 5 bits ofPort C). The
bidirectional bus (Port A) has both the internal input and output registers. When group
A is set in Mode 2, Group B can be set independently. These are 5 control signals as
follows when Group A is used in Mode 2.
0 OBF (Output buffer Full P/F Output)
When MPU writes data into of Port A, (TITI? is set to "0" to inform a peripheral
device that the PPI is ready to output data. However, Port A is dept in the floating
(high impedance) state until ACK input signal is received.
. ECE (Acknowledge Input)
When ACK signal is set to "0", the data of the 3-state output buffer of Port A is
send out. If ACK signal is at "1", Port A is in the high impedance state.
0 STB (Strobe Input)
When STB input is set to "0", the data from peripheral devices are held in the
input latch. When the active RD signal is input into the PPI, the latched input
data are output on the system data bus (D7-D0) .
MPU85-162
TOSHIBA
TMP8255A
tt IBF (Input Buffer Full F/F Output)
When data from peripheral devices are held in the input latch, IBF is set to "1".
It INTR (Interrupt Request Output)
INTR is the output to request the interrupt to MPU and its function is the same
as that in Mode 1.
There are two interrupt enable flip-flop (INTE), INTEl
corresponds to INTEA in Mode 1 output and INTE2 to INTEA in Mode 1 input.
INTE l-Used to generate INTR signal in conjunction with OBF and ACK
signals, and is controlled by PCS bit set/reset.
INTE 2-Used to generate INTR signal in conjunction with IBF and CN
signals, and is controlled by PC4 bit set/reset.
Figure 5.8 shows the operating example and the timing diagram in Mode 2.
W PCs IBFA "y l
R---o IBF
RD----t? PC2-PCo - I/O PORTA -.-..H.. -(EEoE)-EEEiElr-. -
Figure 5.8 Operating example in Mode 2
MPU85-163
TOSHIBA TMP8255A
Control Word in Mode 2
D7 D5 Ds D4 D3 D2 D, Do
L1|1Lx TX I M [1/0J1/OI1/0}
PC2--PCo O = Output
x =Don't care 1=Input
PortB 0=Output
1=lnput
GroupBmode O=Mode0
1=Mode1
Figure 5.9 Control Word and Configuration in Mode 2
ControIWords PC3 T INTRA
PA _ -
D7 D6 Ds Ch; D3 D2 Di DO 7 PAO
PC - OBFA
i1i1rx)xlxl0l1-lo/0_l 7
PC6 _9---- ACKA
PCv-PCo ------ PC4 - STBA
0 = Output PCs - IBFA
1 = Input
E PC2-PCo 'i' HO
T/V7 ----- PB7--PBo -
PortA-Mode 2 I/O
Port B - Mode 0 Input
Control Words PC3 ----- INTRA
PA7~PAO<+>
PC7-OBFA
l1r1lx1xlxj1loli Pcebm
pcu--T'tT7
PCs-IBF/k
ms7--sm--,ll-
----- Pa----?:)]?"
._. PC2----7ic-kg
PCo - INTRB
Port A - Mode 2 I/O
Port B - Mode10utput
Figure 5.10 Example in Combination with Mode 2 and Other Mode
MPU85-164
TOSHIBA TMP8255A
5.2.4 Pecautions for use in Mode 1 and 2
When used in Mode 1 and 2, bits which are not used as control or status in Port C can
be used as follows.
Ifprogrammed as the input, they are accessed by normal Port C read.
If Programmed as the output, high order bits of Port C (PCrPC4) are accessed using
the bit set/reset function. As to low order bits of Port C (PC3-PC0), in additions ot access
by the bit set/reset function, 3 bits only can be accessed by normal writing.
5.3 READING PORT C STATUS
When Port C is used as the control port, that is, when Port C is used in Mode 1 or
Mode 2, the status information of the control word can be read out by a normal read
operation ofPort C.
Table 5.2 StatusWord Format of Port C
Data Mode D7 06 Ds D4 03 D2 D1 Do
Mode 1 Input 1/0 HQ IBFA INTEA INTRA INTEB IBFB INTRB
Mode 1 Output 687? INTEA HO l/O INTRA INTEB tTB% INTRB
Mode 2 6m INTE1 IBFA INTE2 INTRA By Group B Mode
MPU85-165
TOSHIBA TMP8255A
6. ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS
Symbol Item Rating Unit
Vcc Supply Voltage -0.5to 7.0 V
VIN Input Voltage -0.5to Vcc +7.0 V
PD Power Dissipation 1 W
TSOLDER Soldering Temperature (10sec) 260 "C
TSTG Strobe Temperature _ 65 to +150 'C
TopR Operating Temperature 0 to + 70 'C
6.2 DC ELECTRICAL CHARACTERISTICS
TA = 0°C to 700C, Vcc = 5V t 5%, I/ss = 0V
SYMBOL ITEM TEST CONDITION MIN. TYP. MAX. UNIT
" Input LowVoltage -0.5 - 0.8 V
" input High Voltage 2.2 - Vcc V
V Output Low Voltage (DB) l0L=2.SmA - - 0.45 V
OL (PER) lol. =1.7mA - - 0.45 v
V Output High Voltage (DB) ' = -400PA 2.4 - - V
OH (PER) 10H: -200PA 2.4 - - v
IIL Input LeakCurrent Oélegvcc - - t10 pA
Output Leak Current
I E V s V - - t A
OFL (High Impedance State) 0 OUT CC 10 p
d,rttel) Darlington Drive Current 1t,TC)g1 - 1.0 - - 4.0 mA
lcc Operating Supply Current 322:de Timel - - 120 mA
Note : Applied for option al 8 I/O terminals in Port B and Port C.
MPU85-166
TOSHI BA TMP8255A
6.4 AC ELECTRICAL CHARACTREISTICS
TA = 0°C to 70°C, VCC = 5V l 5%, VSS = 0V
SYMBOL PARAMETER TMP8255AP-5 UNIT
MIN. MAX.
tAR Address set-uptimeforCDfail 0 - ns
tRA Address hold time form rise 0 - ns
tRR W pulse width 300 - ns
tRD Delay fromR-Dfall to decided data output - 200 ns
tDF Time from AT5 rise to data bus floating 10 100 ns
th Time fromrit5orlRrise to nextlTt5csrWAfiw 850 - ns
taw Address set-uptime forW_Rfa|1 0 - ns
tWA Address holding time formrise 20 - ns
tww Mpulse width 300 - ns
tDW Busdata set-uptime forihmrise 100 - ns
two Busdata holding time formrise 30 - ns
twe Delay frommrise to decided data output - 350 ns
th Portdata set-uptimeforMfail O - ns
tHe Portdata holding time forR-Drise 0 - ns
tAK TCK pulse width 300 - ns
tST W pulse width 500 - ns
tes Portdata set-uptime (or5tTrise 0 - ns
tpH Portdata holding time forCTgrise 180 - ns
tAD Delay fromTCKfallto decided data output - 300 ns
tKD Time from TCR rise up to port (Port A in Mode2) floating 20 250 ns
twoe Delay frommrise tonall - 650 ns
tAog Delay fromTtRfalito0Tprise - 350 ns
tsis Delay fromWgfai} toWPrise - 300 ns
1mg Delay fromR-Dfall toWrise - 300 ns
tan Delay frtomA15fiwto INTR fall - 400 ns
ISIT Delay from A-ci?: rise to INTR rise - 300 ns
INT Delay frommrise to INTR rise - 350 ns
twn Delay from W rise to lNTR fall - 450 ns
Note: 1. When the power supply is turned ON, reset pulse duration must be active for at
2. AC Measuring Point Input Voltage
least 500 ns or more.
CL= 150pF.
V111: 2.0V, VIL =0.8V
OutputVoltage Von---2.0V,VoL--0.8V
MPU85-167
TOSHI BA TMP8255A
6.4 CAPACITANCE
TA = 25''C, Vcc = vss = 0V
SYMBOL ITEM TEST CONDITION MIN. TYP. MAX, UNIT
CIN lnputCapacitance fc=1MHz - - 10 pF
cuo " Capacitance (') - - 20 pF
* : All terminals except that to be measured should be earthed.
MPU85-168
69t'58ndw
weJfieyp Bugwgi L‘l. BJHBH
68VOSO
2131 ‘,
.LlH}—>|
( t HLNI
.LlS}—>
t :iEH
SIS; ‘—
<—iSl—>
8181—»
H J K._ 8—5
iHOd inle
<— Hdl
5‘” NOLLVHEidO 1.0le
.LfldlflO
0V 'lv 3—)
NOIiVHBdO lfldiflO
0 EIGOW
______________ 00.10
0V ’lV ’2
NOLLVEEIdO J_flclNI
0 300W
INVHDVIC! DNIWLL 'L
VSSZBdWl VHIHSUJ.
TOSHIBA
TMP8255A
OUTPUT
PORT DATA
MODE 1
OUTPUT OPERATION
-tww ---F
PERIPHERAL
tVVlT -twog--- "Tir-------
tWB JI
c-g----
g tAK r'"""--'""'-
MODE 2
BIDIRECTION OPERATION
tww - u tt _tt
(7 -Jr " u
twn tsq
‘r-S% "f,
twoa - t A03 "fs
-------1ii1e) f----------
f, th-y "l-o------------
ms tpH AD KD
___________ -.---. F---------
-----------i 4( tt
tSIB u It
fl“; tRIB
jr " J
Figure 7.2 Timing diagram
MPU85-170
TOSHIBA TMP8255A
8. PACKAGE DIMENSION
8.1 PLASTIC PACKGE
DlP40-P-600
Unit : mm
C-Tr-Tr-lr-nr-nr-ar-II-aI-II-II-lt-Tr-li-Tr-Tr-Ir-of-tr-IC-I
0v-15”
L-Judr1-rt-iu...2l3C.,Jr-lLLuucJL-lurL2rk-gk-Jllt-lt-lL-l
13.4:t0_2
\*jé:9.25
1.22TYP
OSIMIN 35:02
Note: Each lead pitch is 2.54mm, and all the leads are located within d:0.25mm from their
theoretical positions with respect to No.1 and No.40 leads.
MPU85-171
www.ic-phoenix.com
.
