DM74LS245SJX , Octal 3-STATE Bus TransceiverDM74LS245 3-STATE Octal Bus TransceiverAugust 1986Revised March 2000DM74LS2453-STATE Octal Bus Tran ..
DM74LS245WM ,3-STATE Octal Bus TransceiverFeatures YAlternate Military/Aerospace device (54LS245) is avail-YBi-Directional bus transceiver in ..
DM74LS245WMX , Octal 3-STATE Bus TransceiverFeaturesThese octal bus transceivers are designed for asynchro- ■ Bi-Directional bus transceiver in ..
DM74LS247N ,V(cc): 4.75 to 5.25V; BCD to 7-segment decoder/driver with open collector outputsGeneral Description
The 'LS247 has active LOW open-collector outputs guaran-
teed to sink 24 mA ..
DM74LS253N ,TRI-STATE Data Selectors/Multiplexers54LS253/DM54LS253/DM74LS253TRI-STATEDataSelectors/MultiplexersJune198954LS253/DM54LS253/DM74LS253TR ..
DM74LS253N ,TRI-STATE Data Selectors/MultiplexersFeaturesEach of these Schottky-clamped data selectors/multiplex- ■ 3-STATE version of DM74LS153 wit ..
DS21Q554N ,Quad E1 Transceiver (5V/3.3V)Applications • 256–lead MCM BGA package (27mm X 27mm) • Low Power 5V CMOS or Low Power 3.3V CMOS wi ..
DS21Q55DK ,Quad T1/E1/J1 Transceiver Design Kit Daughter CardFEATURES The DS21Q55DK is an easy-to-use evaluation board Demonstrates Key Functions of DS21Q55 Q ..
DS21Q55N ,Quad T1/E1/J1 Transceiverapplications) and can be placed in either transmit or receive data paths. An additional feature of ..
DS21Q55N ,Quad T1/E1/J1 Transceiverapplications § Interleaving PCM bus operation § 8-bit parallel control port, multiplexed or nonm ..
DS21Q58L ,E1 Quad TransceiverAPPLICATIONS Receive Side DSLAMs Interleaving PCM Bus Operation Up to 16.384MHz Routers Conf ..
DS21Q58L+ ,E1 Quad TransceiverAPPLICATIONS Receive Side DSLAMs Interleaving PCM Bus Operation Up to 16.384MHz Routers Conf ..
DM74LS245SJX-DM74LS245WMX
Octal 3-STATE Bus Transceiver
DM74LS245 3-STATE Octal Bus Transceiver August 1986 Revised March 2000 DM74LS245 3-STATE Octal Bus Transceiver General Description Features These octal bus transceivers are designed for asynchro- � Bi-Directional bus transceiver in a high-density 20-pin nous two-way communication between data buses. The package control function implementation minimizes external timing � 3-STATE outputs drive bus lines directly requirements. � PNP inputs reduce DC loading on bus lines The device allows data transmission from the A Bus to the � Hysteresis at bus inputs improve noise margins B Bus or from the B Bus to the A Bus depending upon the � Typical propagation delay times, port-to-port 8 ns logic level at the direction control (DIR) input. The enable input (G) can be used to disable the device so that the � Typical enable/disable times 17 ns buses are effectively isolated. � I (sink current) OL 24 mA � I (source current) OH −15 mA Ordering Code: Order Number Package Number Package Description DM74LS245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Enable Direction Operation G Control DIR L L B Data to A Bus L H A Data to B Bus HX Isolation H = HIGH Level L = LOW Level X = Irrelevant © 2000 DS006413
