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DS33Z44+ ,Quad Ethernet MapperTABLE OF CONTENTS 1 DESCRIPTION........8 2 FEATURE HIGHLIGHTS .9 2.1 GENERAL ........9 2.2 SERIAL I ..
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DS33Z44+
Quad Ethernet Mapper
GENERAL DESCRIPTION The DS33Z44 extends four 10/100 Ethernet LAN
segments by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over four PDH/TDM
data streams. The serial links support bidirectional
synchronous interconnect up to 52Mbps over xDSL,
T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or
SONET/SDH Tributary.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) controllers
provide fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33Z44 can
operate with an inexpensive external processor,
EEPROM or in a stand-alone hardware mode.
APPLICATIONS Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3,
OC-1/EC-1, G.SHDSL, or HDSL2/4
FUNCTIONAL DIAGRAM
FEATURES Four 10/100 IEEE 802.3 Ethernet MACs (MII
and RMII) Half/Full-Duplex with Automatic Flow
Control Four 52Mbps Synchronous TDM Serial Ports
with Independent Transmit and Receive Timing HDLC/LAPS Encapsulation with Programmable
FCS and Interframe Fill Committed Information Rate Controllers Provide
Fractional Allocations in 512kbps Increments Programmable BERT for Serial (TDM)
Interfaces External 16MB, 100MHz SDRAM Buffering Parallel Microprocessor Interface SPI Interface and Hardware Mode for Operation
Without a Host Processor 1.8V Operation with 3.3V Tolerant I/O IEEE 1149.1 JTAG Support
Features Continued on Page 9.
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS33Z44 -40°C to +85°C 256 CSBGA
Go to /telecom for a complete list of
Telecommunications data sheets, evaluation kits, application notes,
and software downloads.
DS33Z44
Quad Ethernet Mapper
4 10/100
MACs
SDRAM
4 MII/RMII
PROM
OR μC
CONFIG.
LOADER
DS33Z44 4 10/100
ETHERNET
PHYs
4 SERIAL
PORTS
TRANSCEIVERS/
SERIAL DRIVERS
BERT
HDLC/X.86
MAPPER
DS33Z44 Quad Ethernet Mapper
TABLE OF CONTENTS DESCRIPTION....................................................................................................................8 FEATURE HIGHLIGHTS....................................................................................................9 2.1 GENERAL......................................................................................................................................9
2.2 SERIAL INTERFACES......................................................................................................................9
2.3 HDLC...........................................................................................................................................9
2.4 COMMITTED INFORMATION RATE (CIR) CONTROLLERS...................................................................9
2.5 X.86 SUPPORT..............................................................................................................................9
2.6 SDRAM INTERFACE....................................................................................................................10
2.7 MAC INTERFACES.......................................................................................................................10
2.8 MICROPROCESSOR INTERFACE....................................................................................................10
2.9 SERIAL SPI INTERFACE—MASTER MODE ONLY............................................................................10
2.10 DEFAULT CONFIGURATIONS.........................................................................................................10
2.11 TEST AND DIAGNOSTICS..............................................................................................................10
2.12 SPECIFICATIONS COMPLIANCE.....................................................................................................11
APPLICATIONS................................................................................................................12 ACRONYMS AND GLOSSARY........................................................................................15 MAJOR OPERATING MODES.........................................................................................16 BLOCK DIAGRAMS.........................................................................................................17 PIN DESCRIPTIONS.........................................................................................................18 7.1 PIN FUNCTIONAL DESCRIPTION....................................................................................................18
FUNCTIONAL DESCRIPTION..........................................................................................29 8.1 PROCESSOR INTERFACE..............................................................................................................29
8.1.1 Read-Write/Data Strobe Modes..........................................................................................................30
8.1.2 Clear On Read....................................................................................................................................30
8.1.3 Interrupt and Pin Modes.....................................................................................................................30
8.2 SPI SERIAL EEPROM INTERFACE...............................................................................................30
8.3 CLOCK STRUCTURE.....................................................................................................................31
8.3.1 Serial Interface Clock Modes..............................................................................................................33
8.3.2 Ethernet Interface Clock Modes.........................................................................................................33
8.4 RESETS AND LOW-POWER MODES...............................................................................................34
8.5 INITIALIZATION AND CONFIGURATION.................................................................................35
8.6 GLOBAL RESOURCES..................................................................................................................35
8.7 PER-PORT RESOURCES..............................................................................................................35
8.8 DEVICE INTERRUPTS...................................................................................................................36
8.9 SERIAL INTERFACES....................................................................................................................38
8.10 CONNECTIONS AND QUEUES........................................................................................................38
8.11 ARBITER.....................................................................................................................................40
8.12 FLOW CONTROL..........................................................................................................................41
8.12.1 Full-Duplex Flow Control....................................................................................................................42
8.12.2 Half-Duplex Flow Control....................................................................................................................43
8.12.3 Host-Managed Flow Control...............................................................................................................43
8.13 ETHERNET INTERFACES...............................................................................................................44
8.13.1 DTE and DCE Mode...........................................................................................................................46
8.14 ETHERNET MAC..........................................................................................................................47
8.14.1 MII Mode Options................................................................................................................................49
8.14.2 RMII Mode..........................................................................................................................................50
8.14.3 PHY MII Management Block and MDIO Interface..............................................................................51
DS33Z44 Quad Ethernet Mapper
8.15.2 Receive Data Interface.......................................................................................................................52
8.15.3 Repetitive Pattern Synchronization....................................................................................................53
8.15.4 Pattern Monitoring...............................................................................................................................54
8.15.5 Pattern Generation..............................................................................................................................54
8.16 SERIAL INTERFACES....................................................................................................................55
8.17 TRANSMIT PACKET PROCESSOR..................................................................................................55
8.18 RECEIVE PACKET PROCESSOR....................................................................................................56
8.19 X.86 ENCODING AND DECODING..................................................................................................58
8.20 COMMITTED INFORMATION RATE CONTROLLER............................................................................61
8.21 HARDWARE MODE.......................................................................................................................63
DEVICE REGISTERS.......................................................................................................67 9.1 REGISTER BIT MAPS....................................................................................................................68
9.1.1 Global Register Bit Map......................................................................................................................68
9.1.2 Arbiter Register Bit Map......................................................................................................................69
9.1.3 BERT Register Bit Map.......................................................................................................................69
9.1.4 Serial Interface Register Bit Map........................................................................................................70
9.1.5 Ethernet Interface Register Bit Map....................................................................................................72
9.1.6 MAC Register Bit Map........................................................................................................................73
9.2 GLOBAL REGISTER DEFINITIONS..................................................................................................75
9.3 ARBITER REGISTERS...................................................................................................................91
9.3.1 Arbiter Register Bit Descriptions.........................................................................................................91
9.4 BERT REGISTERS.......................................................................................................................94
9.5 SERIAL INTERFACE REGISTERS..................................................................................................101
9.5.1 Serial Interface Transmit and Common Registers............................................................................101
9.5.2 Serial Interface Transmit Register Bit Descriptions..........................................................................101
9.5.3 Transmit HDLC Processor Registers...............................................................................................102
9.5.4 X.86 Registers..................................................................................................................................108
9.5.5 Receive Serial Interface....................................................................................................................110
9.6 ETHERNET INTERFACE REGISTERS............................................................................................123
9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................123
9.6.2 MAC Registers..................................................................................................................................135
10 FUNCTIONAL TIMING....................................................................................................152 10.1 FUNCTIONAL SERIAL I/O TIMING.................................................................................................152
10.2 MII AND RMII INTERFACES.........................................................................................................153
10.3 SPI INTERFACE MODE AND EEPROM PROGRAM SEQUENCE.....................................................155
11 OPERATING PARAMETERS.........................................................................................158 11.1 THERMAL CHARACTERISTICS.....................................................................................................160
11.2 MII INTERFACE..........................................................................................................................161
11.3 RMII INTERFACE.......................................................................................................................163
11.4 MDIO INTERFACE......................................................................................................................165
11.5 TRANSMIT WAN INTERFACE......................................................................................................166
11.6 RECEIVE WAN INTERFACE........................................................................................................167
11.7 SDRAM TIMING........................................................................................................................168
11.8 MICROPROCESSOR BUS AC CHARACTERISTICS.........................................................................170
11.9 EEPROM INTERFACE TIMING....................................................................................................173
11.10 JTAG INTERFACE TIMING..........................................................................................................174
12 JTAG INFORMATION.....................................................................................................175 12.1 JTAG/TAP CONTROLLER STATE MACHINE DESCRIPTION...........................................................176
12.2 TAP CONTROLLER STATE MACHINE...........................................................................................176
12.2.1 Test-Logic-Reset...............................................................................................................................176
12.2.2 Run-Test-Idle....................................................................................................................................176
DS33Z44 Quad Ethernet Mapper
12.2.5 Shift-DR............................................................................................................................................176
12.2.6 Exit1-DR............................................................................................................................................176
12.2.7 Pause-DR.........................................................................................................................................176
12.2.8 Exit2-DR............................................................................................................................................176
12.2.9 Update-DR........................................................................................................................................177
12.2.10 Select-IR-Scan..................................................................................................................................177
12.2.11 Capture-IR........................................................................................................................................177
12.2.12 Shift-IR..............................................................................................................................................177
12.2.13 Exit1-IR.............................................................................................................................................177
12.2.14 Pause-IR...........................................................................................................................................177
12.2.15 Exit2-IR.............................................................................................................................................177
12.2.16 Update-IR..........................................................................................................................................177
12.3 INSTRUCTION REGISTER............................................................................................................178
12.3.1 SAMPLE:PRELOAD.........................................................................................................................179
12.3.2 BYPASS............................................................................................................................................179
12.3.3 EXTEST............................................................................................................................................179
12.3.4 CLAMP..............................................................................................................................................179
12.3.5 HIGHZ...............................................................................................................................................179
12.3.6 IDCODE............................................................................................................................................179
12.4 JTAG ID CODES.......................................................................................................................180
12.5 TEST REGISTERS......................................................................................................................180
12.5.1 Boundary Scan Register...................................................................................................................180
12.5.2 Bypass Register................................................................................................................................180
12.5.3 Identification Register.......................................................................................................................180
12.6 JTAG FUNCTIONAL TIMING........................................................................................................181
13 PACKAGE INFORMATION............................................................................................182 13.1 256-CSBGA (17MM X 17MM) (56-G6017-001)..........................................................................182
14 REVISION HISTORY......................................................................................................183
DS33Z44 Quad Ethernet Mapper
LIST OF FIGURES Figure 3-1. Ethernet-to-WAN Extension (No Framing)...........................................................................................12
Figure 3-2. Ethernet-to-WAN Extension (T1/E1 Framing and LIU).........................................................................13
Figure 3-3. Ethernet-to-WAN Extension with T3/E3 Framing.................................................................................13
Figure 3-4. Ethernet Over DSL................................................................................................................................14
Figure 3-5. Copper-to-Fiber Connection.................................................................................................................14
Figure 6-1. Detailed Block Diagram........................................................................................................................17
Figure 7-1. 256-Ball CSBGA Pinout........................................................................................................................28
Figure 8-1. Clocking for the DS33Z44.....................................................................................................................32
Figure 8-2. Device Interrupt Information Flow Diagram..........................................................................................37
Figure 8-3. Transmit Connection Diagram..............................................................................................................39
Figure 8-4. Receive Connection Diagram...............................................................................................................40
Figure 8-5. Flow Control Using Pause Control Frame............................................................................................43
Figure 8-6. IEEE 802.3 Ethernet Frame..................................................................................................................44
Figure 8-7. Configured as DTE Connected to an Ethernet PHY in MII Mode.........................................................46
Figure 8-8. DS33Z44 Configured as a DCE in MII Mode........................................................................................47
Figure 8-9. RMII Interface........................................................................................................................................50
Figure 8-10. MII Management Frame......................................................................................................................51
Figure 8-11. PRBS Synchronization State Diagram...............................................................................................53
Figure 8-12. Repetitive Pattern Synchronization State Diagram............................................................................54
Figure 8-13. LAPS Encoding of MAC Frames Concept..........................................................................................58
Figure 8-14. X.86 Encapsulation of the MAC Field.................................................................................................59
Figure 8-15. CIR in the WAN Transmit Path...........................................................................................................62
Figure 10-1. Tx Serial Interface Functional Timing...............................................................................................152
Figure 10-2. Rx Serial Interface Functional Timing...............................................................................................152
Figure 10-3. Transmit Byte Sync Functional timing..............................................................................................153
Figure 10-4. Receive Byte Sync Functional Timing..............................................................................................153
Figure 10-5. MII Transmit Functional Timing.........................................................................................................154
Figure 10-6. MII Transmit Half-Duplex with a Collision Functional Timing...........................................................154
Figure 10-7. MII Receive Functional Timing..........................................................................................................154
Figure 10-8. RMII Transmit Interface Functional Timing.......................................................................................154
Figure 10-9. RMII Receive Interface Functional Timing........................................................................................155
Figure 10-10. SPI Master Functional Timing.........................................................................................................155
Figure 11-1. Transmit MII Interface Timing...........................................................................................................161
Figure 11-2. Receive MII Interface Timing............................................................................................................162
Figure 11-3. Transmit RMII Interface....................................................................................................................163
Figure 11-4. Receive RMII Interface Timing..........................................................................................................164
Figure 11-5. MDIO Interface Timing......................................................................................................................165
Figure 11-6. Transmit WAN Interface Timing........................................................................................................166
Figure 11-7. Receive WAN Interface Timing.........................................................................................................167
Figure 11-8. SDRAM Interface Timing..................................................................................................................169
Figure 11-9. Intel Bus Read Timing (HWMODE = 0, MODEC = 00)....................................................................171
