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ESDA14V2L-ESDA25L-ESDA5V3L-ESDA6V1L Fast Delivery,Good Price
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ESDA14V2LSTN/a120000avaiDUAL TRANSIL ARRAY FOR ESD PROTECTION
ESDA25LSTN/a1060avaiDUAL TRANSIL ARRAY FOR ESD PROTECTION
ESDA5V3LSTMN/a3300avaiDUAL TRANSIL ARRAY FOR ESD PROTECTION
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ESDA14V2L-ESDA25L-ESDA5V3L-ESDA6V1L
DUAL TRANSIL ARRAY FOR ESD PROTECTION
ESDAxxL
DUAL TRANSIL ARRAY
FOR ESD PROTECTION
Where transient overvoltage protectionin ESD
sensitive equipmentis required, suchas: COMPUTERS PRINTERS COMMUNICATION SYSTEMSis particulary recommended for the RS232 I/O
port protection where the line interface withstands
only with 2kV ESD surges.
APPLICATIONS

Application Specific Discretes
A.S.D.
FUNCTIONAL DIAGRAM
2 UNIDIRECTIONAL TRANSIL FUNCTIONS. LOW LEAKAGE CURRENT:IR max.< 20μAat
VBR. 300W PEAK PULSE POWER (8/20μs)
FEATURES
DESCRIPTION

The ESDAxxL isa dual monolithic voltage
suppressor designedto protect components which
are connectedto data and transmission lines
against ESD. clamps the voltage just above the logic level
supplyfor positive transients, andtoa diode drop
below ground for negative transients. can also work as bidirectionnal suppressor by
connecting only pin1 and2.
BENEFITS

High ESD protection level:upto25 kV.
High integration.
Suitablefor high density boards.
IEC61000-4-2 level4
MIL STD 883C-Method 3015-6: class3.
(human body model)
COMPLIES WITHTHE FOLLOWINGSTANDARDS:
ESDAxxL
ELECTRICAL CHARACTERISTICS
(Tamb= 25°C)
note1:
Evolutionof functional parametersis givenby curves.
ABSOLUTE MAXIMUM RATINGS
(Tamb= 25°C)
note1: Square pulseIpp =15A, tp=2.5μs.
note2
:Δ VBR=αT* (Tamb -25°C)* VBR (25°C)
ESDAxxL
The ESDA family has been designedto clamp fast
spikes like ESD. Generally the PCB designers
needto calculate easily the clamping voltage VCL.
Thisis why we give the dynamic resistancein
additionto the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL =VBR +RdIPP
Where Ippis thepeak current through theESDA cell.
DYNAMIC RESISTANCE MEASUREMENT

The short durationof the ESD has ledusto prefer more adapted test wave,as below defined,to the
classical 8/20μs and 10/1000μs surges.
2.5μs duration measurement wave. the valueof the dynamic resistance remains
stable fora surge duration lower than 20μs, the
2.5μs rectangular surge is well adapted. In
addition both rise and fall times are optimizedto
avoid any parasitic phenomenon during the
measurementof Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
ESDAxxL 50 75 100 1251
IR[Tj] / IR[Tj=25°C]
Fig.5: Relative variationof leakage current versus
junction temperature (typical values).
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.00.01
IFM(A)
Fig.6: Peak forward voltage drop versus peak for-
ward current (typical values).5 1015202530354045505560657075800.1
Ipp(A)
Fig. 3: Clamping voltage versus peak pulse cur-
rent(Tj initial=25 °C).
Rectangular waveformtp= 2.5 μs. 5 10 20 5010
C(pF)
Fig.4: Capacitance versus reverse applied volt-
age (typical values). 25 50 75 100 125 1500.0
Ppp[Tj initial]/Ppp[Tj initial=25°C]
Fig.1: Peak power dissipation versus initial junc-
tion temperature. 10 10010
Ppp(W)
Fig. 2: Peak pulse power versus exponential
pulse duration(Tj initial=25 °C).
ESDAxxL ESD protection by the ESDAxxL
Electrostatic discharge (ESD)isa major causeof
failurein electronic systems.
Transient Voltage Suppressors (TVS) arean ideal
choice for ESD protection. They are capableof
clamping the incoming transienttoa low enough
level such that damage to the protected
semiconductoris prevented.
Surface mount TVS arrays offer the best choicefor
minimal lead inductance.
They serve as parallel protection elements,
connected between the signal lineto ground. As
the transient rises above the operating voltageof
the device, the TVS array becomesa low
impedance path diverting the transient currentto
ground.
The ESDAxxL arrayis the ideal board level
protection of ESD sensitive semiconductor
components.
The tiny SOT23 package allows design flexibilityin
the designof high density boards where the space
savingisata premium. This enablesto shorten the
routing and contributesto hardening againt ESD. Circuit Board Layout
Circuit board layoutisa critical design stepin the
suppression of ESD induced transients. The
following guidelines are recommended: The ESDAxxL shouldbe placedas closeas pos-
sibleto the input terminalsor connectors. The path length between the ESD suppressor
and the protected line shouldbe minimized All conductive loops, including power and
ground loops shouldbe minimized The ESD transient return pathto ground should keptas shortas possible. Ground planes shouldbe used whenever possi-
ble.
ESDAxxL
Packaging: Standard packagingis tape and reel.
MARKING

Information furnishedis believedtobe accurateandreliable.However,STMicroelectronicsassumesno responsibilityforthe consequencesof
useof suchinformation norfor anyinfringementof patentsorother rightsof third parties whichmayresult fromits use.Nolicenseisgrantedby
implicationor otherwise underany patentor patent rightsof STMicroelectronics. Specifications mentionedinthis publicationare subjectto
change without notice. This publicationsupersedes andreplacesall information previously supplied.
STMicroelectronics productsarenot authorizedforuseas critical componentsinlife support devicesor systems without express writtenap-
provalof STMicroelectronics.
TheST logoisa registered trademarkof STMicroelectronics 2000 STMicroelectronics- Printedin Italy-All rights reserved.
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PACKAGE MECHANICAL DATA

SOT23 (Plastic)
FOOT PRINT
(in millimeters)
ORDER CODE
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