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ICE3AS02-ICE3BS02-ICE3BS02 .
Pulse Wide Modulation (PWM) control IC for fixed frequent (FF) operation mode
F3
ICE3AS02 / ICE3BS02
ICE3AS02G / ICE3BS02G
Off-Line SMPS Current Mode
Controller with integrated 500V
Startup Cell
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com
F3
Revision History: 2004-05-21
Datasheet
Previous Version:
Version 1.1 3 21 May 2004
F3
ICE3AS02 / ICE3BS02
ICE3AS02G / ICE3BS02G
Off-Line SMPS Current Mode Controller
with integrated 500V Startup Cell
Product HighlightsLeadfree DIP packageActive Burst Mode to reach the lowest Standby Power
Requirements < 100mWProtection features (Auto Restart Mode) to increase
robustness and safety of the systemAdjustable Blanking Window for high load jumps to
increase system reliability
Features
Active Burst Mode for lowest Standby Power
@ light load controlled by Feedback SignalFast load jump response in Active Burst Mode500V Startup Cell switched off after Start Up100/67kHz internally fixed switching frequencyAuto Restart Mode for Overtemperature DetectionAuto Restart Mode for VCC Overvoltage DetectionAuto Restart Mode for Overload and Open LoopAuto Restart Mode for VCC UndervoltageBlanking Window for short duration high currentUser defined Soft Start Minimum of external components requiredMax Duty Cycle 72% Overall tolerance of Current Limiting < ±5%Internal PWM Leading Edge BlankingSoft switching for low EMI
Description

The F3 Controller provides Active Burst Mode to reach the
lowest Standby Power Requirements <100mW at no load.
As the controller is always active during Active Burst
Mode, there is an immediate response on load jumps
without any black out in the SMPS. In Active Burst Mode
the ripple of the output voltage can be reduced <1%.
Furthermore, to increase the robustness and safety of the
system, the device enters into Auto Restart Mode in the
cases of Overtemperature, VCC Overvoltage, Output
Open Loop or Overload and VCC Undervoltage. By
means of the internal precise peak current limitation, the
dimension of the transformer and the secondary diode can
be lowered which leads to more cost efficiency. An
adjustable blanking window prevents the IC from entering
Auto Restart Mode or Active Burst Mode unintentionally in
case of high load jumps.
Table of ContentsPage
Version 1.1 4 21 May 2004Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2Pin Configuration with P-DSO-8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.2PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.3Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5.1Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5.2Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.1Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.2Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.1Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.2Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.3Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.3Protection Mode(Auto Restart Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . .14Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.1Supply Section 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.2Supply Section 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.3Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.4PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.5Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.6Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.3.7Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Version 1.1 5 21 May 2004Pin Configuration and Functionality
1.1Pin Configuration with PG-DIP-8-6

Figure 1Pin Configuration PG-DIP-8-6(top view)
Note:Pin 4 and 5 are shorted within the DIP
package.
1.2Pin Configuration with P-DSO-8-8

Figure 2Pin Configuration P-DSO-8-8(top view)
Version 1.1 6 21 May 2004
1.3Pin Functionality
SoftS (Soft Start & Auto Restart Control)

The SoftS pin combines the functions of Soft Start
during Start Up and error detection for Auto Restart
Mode. These functions are implemented and can be
adjusted by means of an external capacitor at SoftS to
ground. This capacitor also provides an adjustable
blanking window for high load jumps, before the IC
enters into Auto Restart Mode.
FB (Feedback)

The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FB-
Signal controls in case of light load the Active Burst
Mode of the controller.
CS (Current Sense)

The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
external PowerMOS. If CS reaches the internal
threshold of the Current Limit Comparator, the Driver
output is immediately switched off. Furthermore the
current information is provided for the PWM-
Comparator to realize the Current Mode.
Gate

The Gate pin is the output of the internal driver stage
connected to the Gate of an external PowerMOS.
HV (High Voltage)

The HV pin is connected to the rectified DC input
voltage. It is the input for the integrated 500V Startup
Cell.
VCC (Power supply)

The VCC pin is the positive supply of the IC. The
operating range is between 8.5V and 21V.
GND (Ground)

The GND pin is the ground of the controller.
Version 1.1 7 21 May 2004Representative Blockdiagram
Figure 3Representative Blockdiagram
Version 1.1 8 21 May 2004Functional Description
All values which are used in the functional description
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
3.1Introduction

The F3 is the further development of the F2 to meet the
requirements for the lowest Standby Power at
minimum load and no load conditions. A new fully
integrated Standby Power concept is implemented into
the IC in order to keep the application design easy.
Compared to F2 no further external parts are needed to
achieve the lowest Standby Power. An intelligent
Active Burst Mode is used for this Standby Mode. After
entering this mode there is still a full control of the
power conversion by the secondary side via the same
optocoupler that is used for the normal PWM control.
The response on load jumps is optimized. The voltage
ripple on Vout is minimized. Vout is further on well
controlled in this mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Furthermore a high voltage startup cell is integrated
into the IC which is switched off once the Undervoltage
Lockout on-threshold of 15V is exceeded. The external
startup resistor is no longer necessary. Power losses
are therefore reduced. This increases the efficiency
under light load conditions drastically.
The Soft-Start capacitor is also used for providing an
adjustable blanking window for high load jumps. During
this time window the overload detection is disabled.
With this concept no further external components are
necessary to adjust the blanking window.
An Auto Restart Mode is implemented in the IC to
reduce the average power conversion in the event of
malfunction or unsafe operating condition in the SMPS
system. This feature increases the system’s
robustness and safety which would otherwise lead to a
destruction of the SMPS. Once the malfunction is
removed, normal operation is automatically initiated
after the next Start Up Phase.
The internal precise peak current limitation reduces the
costs for the transformer and the secondary diode. The
influence of the change in the input voltage on the
power limitation can be avoided together with the
integrated Propagation Delay Compensation.
Therefore the maximum power is nearly independent
on the input voltage which is required for wide range
SMPS. There is no need for an extra over-sizing of the
SMPS, e.g. the transformer or PowerMOS.
3.2Power Management

Figure 4Power Management
The Undervoltage Lockout monitors the external
supply voltage VVCC. When the SMPS is plugged to the
main line the internal Startup Cell is biased and starts
to charge the external capacitor CVCC which is
connected to the VCC pin. This VCC charge current
which is provided by the Startup Cell from the HV pin is
1.05mA. When VVCC exceeds the on-threshold
VCCon=15V the internal voltage reference and bias
circuit are switched on. Then the Startup Cell is
switched off by the Undervoltage Lockout and therefore
no power losses present due to the connection of the
Startup Cell to the bus voltage (HV). To avoid
uncontrolled ringing at switch-on a hysteresis is
implemented. The switch-off of the controller can only
take place after Active Mode was entered and VVCC
falls below 8.5V.
The maximum current consumption before the
controller is activated is about 160µA.
When VVCC falls below the off-threshold VCCoff=8.5V the
internal reference is switched off and the Power Down
reset let T1 discharging the soft-start capacitor CSoftS at
pin SoftS. Thus it is ensured that at every startup cycle
the voltage ramp at pin SoftS starts at zero.
The internal Voltage Reference is switched off if Auto
Restart Mode is entered. The current consumption is
then reduced to 300µA.
Version 1.1 9 21 May 2004
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require disconnecting the SMPS from
the AC line.
When Active Burst Mode is entered, the internal Bias is
switched off in order to reduce the current consumption
to below 1.05mA while keeping the Voltage Reference
active as this is necessary in this mode.
3.3Startup Phase

Figure 5Soft Start
At the beginning of the Startup Phase, the IC provides
a Soft Start duration whereby it controls the maximum
primary current by means of a duty cycle limitation. A
signal VSoftS which is generated by the external
capacitor CSofts in combination with the internal pull up
resistor RSoftS, determines the duty cycle until VSoftS
exceeds 4V.
When the Soft Start begins, CSoftS is immediately
charged up to approx. 1V by T2. Therefore the Soft
Start Phase takes place between 1V and 4V. Above
VSoftsS = 4V there is no longer duty cycle limitation
DCmax which is controlled by comparator C7 since
comparator C2 blocks the gate G7 (see Figure 5). The
maximum charge current in the very first stage when
VSoftS is below 1V, is limited to 1.32mA.
Figure 6Startup Phase
By means of this extra charge stage, there is no delay
in the beginning of the Startup Phase when there is still
no switching. Furthermore Soft Start is finished at 4V to
have faster the maximum power capability. The duty
cycles DC1 and DC2 are depending on the mains and
the primary inductance of the transformer. The
limitation of the primary current by DC2 is related to
VSoftS = 4V. But DC1 is related to a maximum primary
current which is limited by the internal Current Limiting
with CS = 1V. Therefore the maximum Startup Phase
is divided into a Soft Start Phase until t1 and a phase
from t1 until t2 where maximum power is provided if
demanded by the FB signal.
Version 1.1 10 21 May 2004
3.4PWM Section

Figure 7PWM Section
3.4.1Oscillator

The oscillator generates a fixed frequency. The
switching frequency for ICE3AS02/G is fOSC = 100kHz
and for ICE3BS02/G fOSC = 67kHz. A resistor, a
capacitor and a current source and current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.72.
3.4.2PWM-Latch FF1

The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the external Power Switch
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator or
the Current-Limit comparator. In case of resetting, the
driver is shut down immediately.
3.4.3Gate Driver

The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents and which
is equipped with a zener diode Z1 (see Figure 8) in
order to improve the control of the Gate attached power
transistors as well as to protect them against
undesirable gate overvoltages.
The Gate Driver is active low at voltages below the
undervoltage lockout threshold VVCCoff.
Figure 8Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external
Power Switch threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 9).
Figure 9Gate Rising Slope
Thus the leading switch on spike is minimized. When
the external Power Switch is switched off, the falling
shape of the driver is slowed down when reaching 2V
to prevent an overshoot below ground. Furthermore the
driver circuit is designed to eliminate cross conduction
of the output stage. During powerup when VCC is
below the undervoltage lockout threshold VVCCoff, the
output of the Gate Driver is low to disable power
transfer to the seconding side.
VCC
PWM-Latch
Version 1.1 11 21 May 2004
3.5Current Limiting

Figure 10Current Limiting Block
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
external Power Switch is sensed via an external sense
resistor RSense . By means of RSense the source current
is transformed to a sense voltage VSense which is fed
into the pin CS. If the voltage VSense exceeds the
internal threshold voltage Vcsth the comparator C10
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the Power Switch in case of Current Limiting.
The influence of the AC input voltage on the maximum
output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
3.5.1Leading Edge Blanking

Figure 11Leading Edge Blanking
Each time when the external Power Switch is switched
on, a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. This spike can cause the gate
drive to switch off unintentionally. To avoid a premature
termination of the switching pulse, this spike is blanked
out with a time constant of tLEB = 220ns. During this
time, the gate drive will not be switched off.
3.5.2Propagation Delay Compensation

In case of overcurrent detection, the switch-off of the
external Power Switch is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current Ipeak which depends on
the ratio of dI/dt of the peak current (see Figure 12).
Figure 12Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
the overshoot dependency on dI/dt of the rising primary
current. That means the propagation delay time
between exceeding the current sense threshold Vcsth
and the switch off of the external Power Switch is
compensated over temperature within a wide range.
Version 1.1 12 21 May 2004
Current Limiting is now possible in a very accurate way.
E.g. Ipeak = 0.5A with RSense = 2. Without Propagation
Delay Compensation the current sense threshold is set
to a static voltage level Vcsth=1V. A current ramp of
dI/dt = 0.4A/µs, that means dVSense/dt = 0.8V/µs, and a propagation delay time of i.e. tPropagation Delay =180ns
leads then to an Ipeak overshoot of 12%. By means of
propagation delay compensation the overshoot is only
about 2% (see Figure 13).
Figure 13Overcurrent Shutdown
The Propagation Delay Compensation is realized by
means of a dynamic threshold voltage Vcsth (see Figure
14). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
Figure 14Dynamic Voltage Threshold Vcsth
3.6Control Unit

The Control Unit contains the functions for Active Burst
Mode and Auto Restart Mode. The Active Burst Mode
and the Auto Restart Mode are combined with an
Adjustable Blanking Window which is depending on the
external Soft Start capacitor. By means of this
Adjustable Blanking Window, the IC avoids entering
into these two modes accidentally. Furthermore it also
provides a certain time whereby the overload detection
is delayed. This delay is useful for applications which
normally works with a low current and occasionally
require a short duration of high current.
3.6.1Adjustable Blanking Window

Figure 15Adjustable Blanking Window
VSoftS is clamped at 4.4V by the closed switch S1 after
the SMPS is settled. If overload occurs VFB is
exceeding 4.8V. Auto Restart Mode can’t be entered as
the gate G5 is still blocked by the comparator C3. But
after VFB has exceeded 4.8V the switch S1 is opened
via the gate G2. The external Soft Start capacitor can
SoftS
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