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INS2651NNSN/a45avai6 V, programmable communication unterface


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INS2651N
6 V, programmable communication unterface
National October 1980
DIS2651 Programmable Communications Interface
General Description
The INS2651 is a programmable Universal Synchronous/ ll Synchronous Mode Capabilities
Asynchronous Receiver/Transmitter (USART) chip - Selectable 5- to 8-Bit Characters
contained in a standard 28-pin duaI-in-line package. The - Selectable 1 or 2 SYNC Characters
chip, which is fabricated using N-channel silicon gate _ Transparent or Non-Transparent Mode
MOS technology, functions as a serial data input/output _ Automatic SYNC or DLE-SYNC insertion
interface tn a bus structtjred system. The functional _ SYNC orDLE Stripping
configuration of INS2651 IS programmed by the system . . .
software for maximum flexibility, thereby allowing the II Asynchronous Mode Cepabllltles
system to receive and transmit virtually any serial data - Selectable ' to 8-Bit Characters
communications signal presently in use. - 3 Selectable Clock Rates (lx, 16x, or 64x the
Baud Rate)
The INS2651 can be programmed to receive and transmit _ Line Break Detection and Generation
, either synchronous or. asynchronous serial data. The _ l-, 1h-, or 2-Stop Bit Detection and Generation
INS2651 performs serial-to-parallel conversion on data . .
. . . w False Start Bit Detection
characters received from an input/output device or a
MODEM, and parallel-to-serial conversion on data char- II Baud Rates
acters received from the CPU. The CPU can read the - DC to 0.8M Baud (Synchronous)
complete status of the INS2651 at any time during the - DC to 0.8 M Baud (1x, Asynchronous)
functional operation. Status information reported - DC to 50 k Baud (16x, Asynchronous)
includes the type and the condition of the transfer _ DC to 12.5k Baud (64x,Asynchronous)
:r'',1r1t,tls,itt,'inns9dae2".":v'f,rbuv,,,tr' (,'li',,'?/n1'l' as well as " Internal or External Baud RateClack
p y. ' g ' - 16 Internal Rates (50 to 19,200 Baud)
II Double Buffering of Data
Features I! TTL Compatible
ll Synchronous and Asynchronous Full Duplex or Half II No System Clock Required
Duplex Operations II Direct Plug-ln Replacement for Signetics 2651
INS2651 General System Configuration
PsnwusnAL
INTERFACE
© 1980 National Semiconductor Corp.
ADDRESS <3
COMLEOL
a SERIAL
SYSTEM
PROEESSOR OUT -
SERIAL bs',
CONTROL
ruucnous
MEMORY l
1P6 LL20Mt0tt “nmr‘d tfl Cl S A
eoeyawI suoneogunwtuoo qqewwmfimd ngzsm
(\JSQ,
F— 39369
Absolute Maximum Ratings
Operating Ambient Temperature fc to +70°C
Storage Temperature -65°C to +150°C
All Voltages with Respect to Ground -0.5 V to +6.0 V
Note: Maximum ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is not
intended and should be limited to those conditions specified under
DC Electrical Characteristics.
DC Electrical Characteristics
TA = 0°C to +70°C; VCC = +5.0v , 5%, GND = OV
Symbol Parameter Min Typ Max Unit Test Conditions
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage 0.25 0.45 V IOL = 1.6 mA
VOH Output High Voltage 2.4 2.8 V IOH = -100PA
ltL Input Load Current 10 PA VIN = 0V to 5.5V
ILD Data Bus Leakage Current 10 PA VOUT = 4.0V
ILO Open Drain Leakage Current 10 PA VOUT = 4.0V
ICC Power Supply Current 65 150 mA
Capacitance
TA = +25°c; VCC = GND = 0V
Symbol Parameter Min Typ Max Unit Test Conditions
CIN Input Capacitance 20 pF ft: = 1 MHz
COUT Output Capacitance 20 pF Unmeasu red pins
Cl/O I/O Capacitance 20 pF to ground
AC Electrical Characteristics
TA = 0°C to +70°c; VCC = +5.0v , 5%, GND = ov
Symbol i Parameter I Min l Typ I Max I Unit I Test Conditions
BUS PARAMETERS
tce Chip Enable Pulse Width 300 ns
Us Address Setup Time 20 ns
tAH Address Hold Time 20 ns
tcs 'iw Control Setup Time 20 ns
tCH A/VY Control Hold Time 20 ns
trys Data Setup Time for Write 225 ns
mm Data Hold Time for Write 50 ns
190 Data Delay Time for Read 250 ns Cu = 100pF
to; Data Bus Floating Time for Read 150 ns CL = 100pF
OTHER TIMINGS
IRES RESET Pulse Width 1000 ns
fans Baud Rate Generator Input Clock 1.0 5.0688 5.073 MHz
Frequency
tBRH Baud Rate Clock High State 70 ns
IBRL Baud Rate Clock Low State 70 ns
fan 'Tx-tc or n-de" Input Clock Frequency DC 0.769 MHz
tR/TH Tic or m Clock High State 650 ns
tR/TL = or m Clock Low State 650 ns
tno TxD Delay from Falling Edge otY1T 650 ns CL = 100pF
trcs Skew Between T_x_D_Changing and 0 0 ns CL = 100pF
Falling Edge of TxC Output
tnxs Rx Data Setup Time 300 ns
tam Rx Data Hold Time 300 ns
Timing Waveforms
--tREs
RESET TIMING
I In: I
N - DO
(WRITE)
(32$ nus nommcx nor wmu X nan VALID 1 X BUS FLOATING
l-- tnr .|
READ AND WRITE TIMING
tittttt IBM.
4 tR/tH tR/TL
JHILLK. /''"'''"sc_.._,,...y N
" C, ch /
IlFam;
I/FR/T
CLOCK TIMING
iBIT TIME
(1,16, OR " CLOCK PERIODS)
(INPUT)
(e tTXD " 'rc,
u.---------------.--..--'
ruuwur) y' N
TRANSM l TIMI NG
I Inxs lnxu
m (IX) N L N
RECEIVE TIMING
-"''"''""''--""'""t '"""
-------it----c., --_------ 'rr-------')
Timing Waveforms (cont'd.)
m (la)
I'1113|‘151‘I1131‘151‘12I31‘L5I‘I213I‘I5I'12IJHI5I
TxD I DATA1 I mun I DATA: I svm I BATA4 I
l l l I
um I l I I
T.nov _ '
0W3 LC EU ly ly
DATAI DATA 2 DATA 3 DATA A
____‘J
SYNCH RONOUS MODE
oy--"--,'')'").'"," C A11|213|A|51E C AI1I2r3r4t5t B C-0--Atli2
I DATA? I I I DATAZ I I I DATA? I 11ATA4
UEMT / J /
tTE FOR If
DATA] DATA t DATA 3 DATA4
ASYNCHRONOUS MODE
I'lzl3l‘15t1|2|31‘I51112131‘151‘12I31‘151‘I1131‘15I‘12131‘I5I‘
nxn I sun I DATA1 I DATA? I DAIAJ I DATAA I onus "
I F--roimeo---1
MN __I
SVNDET I
STATUS I ,
f5 FOR I I
ma U W 'HI l.
READ READ READ READ READ READ
STATUS STATUS RHR RHR RHR RHR
(DATA 1) (DAYA 2) (DATA 3) (UATA 1)
SYNCHRONOUS MODE
+D>A|11213141513 c A.1.21314.sla C-O----),!,?,''':',?, c A11|2|3|
orrtt) I I OATA1 I I I DATA2 I I I DATAJ I I I DATAd
min_I I l
RxRDV I
DVERRUN \
STAIUS
m I, / 's,
READ W "-ly
HEAD READ
RHR NHR
(DATA 1) (DATA 3)
ASVNCHRONOUS MODE
mw, WTIMING (SHOWN Fort E-BIT CHARACTERS, N0 PARITV, Z-SIOP HITS " SVNCHRONUUS MODE).
WTIMING (SHOWN FOR 5-BIT CHARACTERS, NO PARITV, TSTOP BITS (IN ASVNCHRONOUS).
NOTE l: A - START BIT4 B - STOP BIT t. ll - STOP BIT 1,
D - TxD MARKING CONDITION
INS2651 Block Diagram
DATA nus
DATA nus
m-na <=> Burma
(8, 7, 5, 5, t
l. zuti j
“ES” (21) onunnu CONTROL
All (12) mm: nsmsrsnt
Al " moo: REGISTER 2
EM f13I I comma REGISTER
c1 (ll) a status REGISTER
INTERNAI
DATA BUS
SVN/DLE CDNTRIIL
SYN] REGISTER
SVNZ RIGISTER
BRCLK -
(9) nun RATE
rTc - "Tit'"
I25) CLOCK common.
FIIC -
- (22)
n a -'='eei
- (11)
CTS MODEM
EDMTRDL
----- (18)
TxEMT/DSCHG --o
me REGISTER
mnnmmm t 5) nnnv
mmsmr DATA
uowme REGISTER
TMNSMIT (19)
SHIFT REl91STER - 7x0
nscswzn mm
RECEIVE DATA
Hotumc ntmsnn
RECEIVE (1)
SHIFT REGISTER --- mo
sumv (4)
NOTE: APPLICABLE FiN00T NUMHERS ARE
INCLUDED WITHIN PARENTNESES.
INS2651 Functional Pin Definitions
The following describes the function of all the INS2651
input/output pins. Some of these descriptions reference
internal circuits.
INPUT SIGNALS
Reset (RESET), Pin 21: When high, performs a master
reset on the INS2651. This signal asynchronously
terminates any device activity and clears the Mode,
Command, and Status Regsiters. The device assumes the
idle state and remains in this mode until initialized with
the appropriate control words.
Address Lines (AI-AO), Pins 10,12: Address lines used
to select internal Mode and Command registers.
Read/Write(§/W),Pin 13: Controls the direction of
data bus transfers. A high input allows data from the
CPU to be loaded into the addressed register. A low
input causes the contents of the addressed register to be
present on the data bus.
Chip Enable (6E), Pin It: When low, indicates that
control and data lines to the device are valid and that the
specified operation should be performed. When high,
places the device in the TR M;TATE© condition.
Baud Rate Generator Clock (BRCLK), Pin 20: 5.0688
MHz clock input to the internal Baud Rate Generator.
Not required if external receiver and transmitter (m
and 'TiiQ clocks are used.
Receiver Data (RxD), Pin 3: Serial data input to the
receiver.
Data Set Ready (W), Pin 22: GeneraI-purpose input
which, when low, indicates either the Data Set Ready or
Ring condition. Its complement is stored as Status
Register bit 7. A change in state of this input causes a
low output on TXEM i ?DSCHG.
Data Carrier Detect il5trD), Pin16: When low, enables
the receiver to operate. The complement of this input is
stored as Status Register bit 6, and an input change in
state causes a low output on TXEMT?D§CF|G.
Clear to Send (CTS), Pin 17: When low, enables the
transmitter to operate. When high, holds the I x5
output in MARK condition.
Vcc, Pin 26: +5-volt supply.
Ground, Pin 4: O-volt reference.
OUTPUT SIGNALS
Transmitter Ready (m), Pin15: A low on this
output, which is open-drain, indicates that Transmit
Holding Register (THR) is ready to accept a data char-
acter from the CPU. This output, which is the comple-
ment of Status Register bit 0, goes high when the data
character is loaded and is valid only when the transmitter
is enabled. The TXREV output can be used as an inter-
rupt to the system.
Receiver Ready (RxRDY), Pin 14: A low on this output,
which is open-drain, indicates that the Receive Holding
Register (RHR) has a character ready for input to the
CPU. This output, which is the complement of Status
Register bit 1, goes high either when the Receiver
Holding Register is read by the CPU or when the receiver
is disabled. The RxRDV output can be used as an
interrupt to the system.
Transmitter Empty or Data Set Change (TxEMT/DSCHG),
Pin 18: A low on this output, which is open-drain,
indicates that either the transmitter has completed
serialization of the last character loaded by the CPU or
that a change of state of the DSR or m inputs has
occurred. If the TxEMT condition does not exist, this
output goes high when the Status Register is read by the
CPU. Otherwise, the Transmit Holding Register must be
loaded by the CPU for this line to go high. The TxEMT/
DSCHG outputcan be used as an interrupt to the system.
This output is the complement of Status Register bit
Transmitter Data (VD), Pin 19: Composite serial data
output to a MODEM or input/output device. The TxD
output is held in the marking state (logic 1) when the
transmitter is disabled.
Pin Configuration
Data Terminal Ready (W), Pin 24: General-purpose
output normally used to indicate Data Terminal Ready.
The DTR output is the complement of Command
Register bit 1.
Request to Send (RTS), Pin 23: General-purpose output
normally used to indicate Request to Send. The RT§
output is the complement of Command Register bit 5.
INPUT/OUTPUT SIGNALS
Data (D7-D0) Bus, Pins 28, 27, 8, 7, 6, 5, 2,1: This bus
comprises eight TRl-STATE input/output lines. The bus
provides bidirectional communications between the
INS2651 and the CPU. Data, control words, and status
information are transferred via the Data Bus.
Receiver Clock (m, Pin 25: If external receiver clock
is programmed, this input controls the rate at which a
data character is received. The frequency of the HE
input is a multiple (1x, 16x, or 64x) of the Baud Rate.
Data is sampled on the rising edge of the clock. It
internal receiver clock is programmed, this pin becomes
an output at 1x the programmed Baud Rate.
Transmitter Clock (WC), Pin 9: If external transmitter
clock is programmed, this input controls the rate at
which a data character is transmitted. The frequency of
the Tra input is a multiple (1x, 16x, or 64x) of the
Baud Rate. Transmitter Data is clocked out of the
INS2651 on the falling edge of the TxC input. If
internal transmitter clock is programmed, this pin
becomes an output at 1x the programmed Baud Rate.
n2 - 1 U 28 - BI
M - 2 27 - itil
Km - l " - Vcc
mun - 4 25 - m
M - 5 " - m
D5 - s 23 - W
DE - 7 22 - DSR
m - a mszsst 21 - RESET
ra- s 20 - uncut
A1 - 10 " - nu
cr- 11 18 -..-r_titttu:
A0 - l? 17 - m
AM-. 13 1s - Mtl
xRDV - 14 15 - WV
IN82651 Programming
The system software determines the operative conditions
(mode selection, clock selection, data format, and so
forth) of the INS2651 via internal Mode Registers 1 and
2, and the Command Register. Prior to initiating data
communications, the INS2651 operational mode must
be programmed by performing write operations to these
8-bit registers via the Data Bus. The device can be repro-
grammed at any time during program execution. How.
ever, the receiver and transmitter should be disabled if
the change has an effect on the reception or transmission
of a character.
The internal registers ouhe_lNS2651 are accessed by
applying signals to the CE, R/W, A1, and A0 inputs as
specified in table 1.
Table 1. Guess My Name
E A1 A0 RAN Function
1 X X X TRI-STATE Data Bus
0 0 0 0 Read Receive Holding Register
0 0 0 1 Write Transmit Holding Register
0 0 1 0 Read Status Register
0 0 1 1 Write SYN1/SYN2/DLE Registers
0 1 0 0 Read Mode Registers 1 and 2
0 1 O 1 Write Mode Registers 1 and 2
0 1 1 0 Read Command Register F
O 1 1 1 Write Command Register
In the case of multiple registers (SYN1/SYN2/DLE
Registers and Mode Registers 1 and 2), successive read
or write operations will access the next higher register.
For example, if A1 equals 0, A2 equals 1, and WW
equals 1, the first write operation loads SYN1 Register.
The next write operation loads SYN2 Register, and the
third loads the DLE Register. Read and write operations
are performed on the Mode Registers in asirnilar manner.
If more than the required number of accesses is made,
the internal register pointer returns to the first register.
The pointers are reset to the first registers either by a
RESET input or by performing a "Read Command
Register" operation, but are unaffected by any other
read or write operation.
INITII RESET
MODE REGISTER 1
MODE REGISTER l
so" REGISTER
SVNZ REGISYE R
DLE REGISTER
CDMHAMD REGISTER
____'1
1‘_""_1
I man: I
DISABLE
RCV H AND X MTR
I TRA0PARENT
BOTE: MODE REGIS'IEFI I MUST EEWRITI’EN
BEFORE MODE REEISTEH l CAN "
WRITTEN. MODE REGISTER I NEED
NOT " PROGRAMMED IF EXTERNAL
CLDCKS ARE USED.
NOTE: SVII REGISTER MUST BEWRITTEN
BEFORE SYN! REGISTER CAN "
WRITTEN, AND "" IEFURE DIE
CAN " WRITTEN.
Figure 1. Initialization Flowchart
MODE REGISTER 1 FORMAT
MT NUMBERS
14131-3 Mttt-6 MRI-5 M1114 MRI-T 11111-2 MRI-t MRH)
svnc: SYNC; mun TYftE PARITV CONTROL CHARACTER 121111111 man: AND BAUO RATE Fatmmt
NO. or Sm mmsmnmcv 11- con 11 . DISABLED no= 5 ms M . svucuaouuus tx RATE
J1t,'n1W's',,, COTR’xAl 1= EVEN 1= ENABLED ill = 6 ms M= nsvncnnouous 1. RATE
“8 n: o A ENT 10=7 arrs "t--AiWHCHR0it0lJSuix RATE
INGLE SYN I TRANS? R " = l BITS 11 = ASVNCHHUNDUS Mx RATE
ASYNC:
STOP 1111 LENGTH
no " INVALID
111 =1 STOP an
111 =Ph smv BITS
tt _ 2 STOP ms
MODE REGISTER 2 FORMAT
anuumasns
MM-7 MRI-B 11112-5 MR2-4 MR2-3 MR2-t Mitt-t MRZ-IJ
NOT usm TRANSMITTER RECEIVER aAun RATE SELECTION
CLOCK CLOCK
1) ' EXTERNAL u = EXTERNAL noon = 511 nun 11111 = 1101: mm 1101) I unn BAUD
1- INTERNAL 1- INTERNAL Mitt I " IAUD 1l111 = 12011 Blum lit" " 721m BAUIJ
uo1n=11uaAuo 1oun=1wnaAun 111l1--98illliuul0
11n11:134.5 EAUD Ttlot-- znun BAUD 1111 = 1921111 BAUD
o1ou=1so BAUD 1n1n=zaun nun
111111: 3119 nun 11111: 351111 nun
COMMAND REGISTER FORMAT
tur NUMBERS
CR-7 CR-ii CR-5 CR-4 cm CR-t 1:114 cn-o
tWERATlNG MODE asuuzsr T0 RESET ERROR 115111112: RECEWE DATA TERMINAL mmsmn
M-- NORMAL ovznmou ?Tancss m il = NORMAL FORCE BREAK iii',',',',')" 3:311:55 m 1101112111111;
111: 11311111: AUTOMATIC * 1= MSET ERROR ll = NORMAL _ 7 .
mm on: OUTPUT 1111;11FLAG," sums ls FORCE 8flEAK " 0mm! oo""!!!.!? tw- ENABLE
sync. syn MO/OR 1: FORCES m g5ligh"L'i':""'""""1' ENABLE 1- FORCES um
IJLE iirhWidi MODE OUTPUT LOW PE/DL SYNC: OUTPUT Low
W/iq SEND DLE
tit-- LOCAL too BACK
11 . REMOTE LOOP BACK " = NORMAL
1= SEND nu
STATUS REGISTER FORMAT
m muuams
53-1 58-5 sn-s 8114 SR-3 $114 SR-l SR-ll
DATA SET mm unmm rslsvu ontcr ovsaauu PE/DLE DEYECT rxsm/oscns many nnnv
53% ' 3‘70“” ASYN: tl . NORMAL Asvuc: o = no RMAL It = I'/i9/d ll . J/l/Irie?
n=n m UT = CDINPUT 1 - . = 11 t
Is Hliut IS HIGH ir-- NORMAL l-- 2‘53?" “_ 1ttMWAL 1 1ihfghh 1m REGISTER namsrm
1- 6511mm” 1: BCD INPUT 1: FRAMING ERROR t= Many ERROR TRAHSMtT sary Eufrry ausv
1s Law IS LOW 31/1112: 51/1110: nemsrsn Is 1 = RECEIVE l-- nuuswm
o-- MRMAL tl . NORMAL MPTY :23???" 11111111111:
I-- SYN CHARACTER la mun ERROR HAS DAM 25%;?"
BETttTt0 on DLE
CHARACTER
RECEIVED
MOI: BAUD RATE FACTOR IN ASVNCHRONOUS MODE APPLIES ONLV IF
ERNAL CLOCK ISSELECTED FACr0Rls1lixtF INTERNAL
klill IS SELECTED.
Table 2. Baud Rate Generator Characteristics (Crystal Frequency = 5.0688 MHz)
Theoretical Actual
Frequency Frequency Duty
Baud 16x Clock 16x Clock Percent Cycle
Rate (kHz) (kHz) Error (%) Divisor
50 0.8 0.8 - 50/50 6336
75 1.2 1.2 - 50/50 4224
110 1.76 1.76 - 50/50 2880
134.5 2.152 2.1523 0.016 50/50 2355
150 2.4 2.4 - 50/50 2112
300 4.8 4.8 - 50/50 1056
600 9.6 9.6 - 50/50 528
1200 19.2 19.2 - 50/50 264
1800 28.8 28.8 - 50/50 176
2000 32.0 32.081 0.253 50/50 158
2400 38.4 38.4 - 50/50 132
3600 57.6 57.6 - 50/50 88
4800 76.8 76.8 _ 50/50 66
7200 115.2 115.2 - 50/50 44
9600 153.6 153.6 - 48/52 33
19200 307.2 316.8 3.125 50/50 16
Note.. 16x clock is used in asynchronous mode. In synchronous mode. clock multiplier is 1x and duty cycle is 50%/50% for any baud
ra te.
INS2651 Operation
GENERAL
The transmitter section of the INS2651 performs
parallel-to-serial conversion of data supplied to it from
the system data bus.
The receiver section of the INS2651 performs serial-to-
parallel conversion of data received from the MODEM or
input/output device. Both the transmitter and receiver
are double buffered, allowing a full character time in
which to service Transmit Ready (TYRE?) and Receive
Ready (Rx RDY) interrupts.
The character size (5, 6, 7, or 8 bits) is program select-
able. Parity check/generation and the baud rate may also
be defined by the program. Note that the character size
is exclusive of the start/stop and parity bits.
SYNCHRONOUS MODE
The transmitter starts transmitting a continuous bit
stream once the transmitter is enabled and the Clear to
Send (m) input is low. If the system is late in supplying
a character to the transmitter, then the transmitter will
send the SYN character (or SYN1, two characters if in
double SYNC mode) as an idle fill in the Non-Transparent
mode, or the DLE-SYNl character pair as an idle fill in
the Transparent mode. If this condition occurs, the
Tx EMT/DSCHG output goes low.
The receiver enters a character synchronization mode as
soon as the receiver is enabled and the Data Carrier
Detect itetf) input goes low. Either one or two con-
secutive SYN characters must be recognized by the
receiver. The number of SYN characters is program
selectable, and data is sent to the processor only after
synchronization. The SYN character(s) in the Transparent
mode (or DLE-SYN1 characters in the Non-Transparent
mode) are stripped off the data stream after synchron-
ization. This feature is program selectable.
An overrun error will occur if the processor is late in
servicing the received character. When this condition
occurs, the character in the receiver buffer is written
over by the character causing the overrun, and the
overrun status bit is set.
ASYNCHRONOUS MODE
Once transmission is initiated, the transmitter supplies
the start bit, odd, even, or no parity bit, and the proper
number of stop bits as specified by the program. If the
next character is presented to the transmitter, it is sent
immediately after transmission of the stop bit of the
present character. Otherwise the Mark (logic high)
condition is sent. The transmitter can be programmed to
send a Space (logic low) condition instead of the Mark
condition.
Once the receiver is enabled, reception of a character is
initiated by recognition of the start bit. The Start/Stop
and Parity bits are stripped off while assembling the
serial input into a parallel character. If a break condition
is detected then the receiver sends a character of all zero
bits and a Framing Error status bit to the processor.
Succeeding all-zero or break characters are not assembled
and presented to the system. The Receive Data (RxD)
input must return to a marking condition before
character assembly is resumed. The overrun condition is
checked in the same manner as in the Synchronous
|N62651 Programmable Communications Interface
Physical Dimensions
I MO M
(tr us)
mo-ro-nit-sir-ny-slr-tOrr-tlit-nrt-no-error-sl!
-Ts ml
MAX GLIN
W,r3s;
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cuss ussams um-uasn
SEALAM -t, -.- *nmmzn
, fl - "N-BIN
T las"-crm
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(11.15! “m” 0E0 mo c,-],,,,,, un -unz ‘31.“
" 51445.1" um mm mm "BSll$)
ZBvLaad Ceramic DuaI-lnvLina Package [Car Dip (u)]
0rd" Number IN52651J
-.------l3t23W--- - - - fl
" m in a 1:! P, El m " m m " m
(I'm: _ nssu nma
(11m -u 111)
mm " I""""--,
bdLtlLrittJLsJLslLrJL'fLrJUlyJLtJb?lrel
(mm) le, 0.1m
unniuzn mx (15m m. A-- nun 1mm
r,,"“ mr _ I t 1w J 11.1nz‘mn
ll 525 mm W 'L"
CC_"_" am; nms L .I am (l,., um um am 1'5”)
" m l",',,') (W n m) _ a sol I mm Mm m.
mm m “m
28-Lead Plastic DuaI-ln-Lina Package (N)
Order Number INS2651 N
Naunml Sumicmductor
Mrptotlort
2900 semicmtguiyor Dnve
Santa Clara. Calnuvma 95051 wesl Germany
Tel (408) T3r50tm Tal 089/9 15027
TWX (910) 339-9260 Telex: 05-22772
8000 Munchen 21
Nathan! Somltandumr Snub"
ElstmMirnerstrasse Gill!
" Inurmtlom‘ Inc.. Jun annml Slmlconmmr " Ehumnln 00 Ill!“
Mlyake Building (Mung KII'II) Lid, Avda Engadelru Fana Lima 844
1-9 Votsuya. Shimuku-ku 160 am Floor, t 11 Annar Cunjunln 1104
TOKYO. Janan
Tel,. 10313553711
TWy 212-2015 NSCJ~J
Cheung Kong Electronic Bldg
1 H1119 Yup Street
Kwun Tong
Kowloan. Hung Kong
Tel. 3-411241‘3
Telex: 43866 NSEHK "
Came, NATSEMI
Jardsm Paulnslano
Sao Paulo, Erasnl
Titles
1121008 CABME SAO PAULO
" Emronlu Ftr, Ltd,
Cnr, Slud Rd & Min Highway
Bayswater, Victona 3153
Auslralla
Tel 017206333
Telex: 32098
Nalmnal noes nttt assume any responsvbuny lot use N any Circuitry described. no mrcuwl palenl Ucanses are implied, and Mammal reserves the nghl at any lime wllnouI ounce. lo change said mrcumy
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This file is the datasheet for the following electronic components:
INS2651 N - product/in32651n?HQS=T|-nu|I-null-dscatalog-df-pf-null-wwe
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