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IP2002IRN/a5331avaiSynchronous Buck Multiphase Optimized BGA Power Block.
IP2002TRIORN/a2000avaiSynchronous Buck Multiphase Optimized BGA Power Block.


IP2002 ,Synchronous Buck Multiphase Optimized BGA Power Block.Block DiagramV VIN INPR PRD DY YE ENAB NABL LE EMO MOS SF FE ET TD Dr ri iv ve er r w with ithV VPW ..
IP2002TR ,Synchronous Buck Multiphase Optimized BGA Power Block.Features:• Output current 30A continuous with no derating up toT = 90°C and T = 90°CPCB CASE• Oper ..
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IP2002-IP2002TR
Synchronous Buck Multiphase Optimized BGA Power Block.
International PD-94568A
TOR Rectifier iP2002
tPa/Wi"' Synchronous Buck
mnnmom Multiphase Optimized BGA Power Block
Features: Integrated Power Semiconductors, Drivers & Passives
. Output current 30A continuous with no derating up to
T, = 90°C and TCASE = 90°C
. Operating frequency up to 1MHz
. Dual sided heatsink capable
. Very small 11mm x 11mm x 2.6mm profile
. iP2001 footprint compatible
. Internal features minimize layout sensitivity *
. Optimized for very low power losses iP2002 Power Block
Description
The iP2002 is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.6mm
BGA power block. The only additional components required for a complete multiphase converter are a PWM
IC, the external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component
integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized
internally for layout, heat transfer and component selection.
iP2002 Internal Block Diagram
PRDY o-,'-
ENABLE o-i- MOSFET
WM : I Driverwith
P I dead time
VDD CIT control
SGND o-i-T e b
' All of the difficut PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR Block. There are no concerns about double
pulsing, unwanted shutdown, or other malfunctions which often occur in switching power supplies. The iPOWIR Block will function normally without any
additional input power supply bypass capacitors. However, for reliable long term operation it is recommended that at least four 10uF ceramic input
decoupling capacitors are provided to the VIN pin of each power block. No additional bypassing is required on the VDD pin.
03/20/03 1
International
. TOR Rectifier
I P2 002 All specifications @ 25°C (unless otherwise specified)
Absolute Maximum Ratings :
Parameter Min Typ Max Units Conditions
VIN to PGND - - 16 V
Va, to SGND - - 6.0 V
PWM to SGND -0.3 - VDD+0.3 V nottoexased 6.0V
Enable to SGND -0.3 - VDD+O'3 V nottoexaeed6.0V
Output RMS Current - - 30 A
Block Temperature -40 - 125 °C
Recommended Operating Conditions :
Parameter Symbol Min Typ Max Units Conditions
Supply Voltage VDD 4.6 5.0 5.5 V
Input Voltage Range VIN 3.0 - 13.2 V see Figs. 2 & 3
Output Voltage Range VOUT 0.9 - 3.3 V see Figs. 2,4&8
Output Current Range |OUT - - 30 A see Fig. 2
Operating Frequency fsw 150 - 1000 kHz see Figs. 2 & 5
Operating Duty Cycle D - - 85 %
Electrical Specifications © VDD = 5V (unless otherwise specified) :
Parameter Symbol Min Typ Max Units Conditions
Block Power Loss (O PBLK - 7.2 8.9 W 1(N=12MN/our=12N/,
Turn On Delay Q) I, - 63 - ns low: 30A, fsw: 1MHz
Turn Off Delay © tam - 26 -
VIN Quiescent Current low - - 1.0 mA Enable=0Vh(N=12V
Va, Quiescent Current lav,r, - - 1 0 HA Enable = OV, T,,,-- 5V
Under-Voltage Lockout UVLO
Start Threshold VSTART 4.2 4.4 4.5 V
Hysteresis VHWUVLO - .05 -
Enable Enable
Input Voltage High VIH 2.0 - - V
Input Voltage Low V|L - - 0.8
Power Ready PRDY
Logic Level High VOH 4.5 4.6 - V vDD=4.sv, 1W: 10mA
Logic Level Low VOL - 0.1 0.2 vDD< UVLO Threshold, 1L0“: 1mA
PWM Input PWM
Logic Level High VOH 2.0 - - V
Logic Level Low V - - 0.8
co Measurement were made using four 10uF (TDK C3225X7R1C106M or equiv.) capacitors across the input (see
Fig. 8).
C) Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).

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