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IP3048CX5NXPN/a2900avaiIntegrated dual channel passive LC-filter network with ESD protection to IEC61000-4-2 level 4


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IP3048CX5
Integrated dual channel passive LC-filter network with ESD protection to IEC61000-4-2 level 4
1. Product profile
1.1 General description

The IP3048CX5 is a low-ohmic, dual channel LC low-pass filter array which is designed to
provide filtering of undesired RF signals. In addition, IP3048CX5 incorporates diodes to
provide protection to downstream components from ElectroStatic Discharge (ESD)
voltages as high as ±15 kV contact discharge according the IEC 61000-4-2 model, far
exceeding standard level 4.
The device is fabricated using monolithic silicon technology and integrates two inductors
and four pairs of back-to-back diodes in a 0.5 mm pitch Wafer-Level Chip-Scale Package
(WLCSP). These features make the IP3048CX5 ideal for use in applications requiring the
utmost in miniaturization such as mobile phone handsets, cordless telephones and other
portable electronic devices.
1.2 Features and benefits
Pb-free, RoHS compliant and free of halogen and antimony (Dark Green compliant) Integrated dual channel π-type LC-filter network 0.25 Ω series resistance per channel; 190 pF channel capacitance Integrated ESD protection withstanding ±15 kV contact discharge, far exceeding
IEC 61000-4-2 level 4 WLCSP with 0.5 mm pitch
1.3 Applications

Audio line ElectroMagnetic Interference (EMI) filtering and ESD protection in e.g. Cellular and Personal Communication System (PCS) mobile handsets DECT Portable media player
IP3048CX5
Integrated dual channel passive LC-filter network with ESD
protection to IEC 61000-4-2 level 4
Rev. 3 — 10 February 2011 Product data sheet
NXP Semiconductors IP3048CX5
Integrated dual channel passive LC-filter network with ESD protection
2. Pinning information
2.1 Pinning

2.2 Pin description

3. Ordering information

Table 1. Pinning
channel 1 channel 2 ground channel 1 channel 2
Table 2. Ordering information

IP3048CX5 WLCSP5 wafer level chip-size package; 5 bumps (2-1-2) IP3048CX5
NXP Semiconductors IP3048CX5
Integrated dual channel passive LC-filter network with ESD protection
4. Functional diagram

5. Limiting values

[1] Device is qualified with 1 000 pulses of ±15 kV contact discharges each, according to the IEC 61000-4-2 model and far exceeds the
specified level 4 (8 kV contact discharge).
[2] A special robust test is performed stressing the devices with ≥ 1 000 contact discharges according to the IEC 61000-4-2 model and far
exceeds the specified level 4 (8 kV contact discharge).
Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).
VRWM reverse standoff voltage - 5 V
Ich channel current (DC) - 625 mA
VESD electrostatic discharge voltage all pins to ground
contact discharge [1][2] −15 +15 kV
air discharge −15 +15 kV
IEC 61000-4-2 level 4; all pins
to ground
contact discharge −8 +8 kV
air discharge −15 +15 kV
Pch channel power dissipation continuous; Tamb = 85 °C - 135 mW
Ptot total power dissipation continuous; Tamb = 85 °C - 270 mW
PPP peak pulse power Tamb = 85 °C; maximum peak
power dissipation < 120 s; δ < 50 % 270 mW
Tstg storage temperature −65 +150 °C
Treflow(peak) peak reflow temperature 10 s maximum - 260 °C
Tamb ambient temperature −40 +85 °C
NXP Semiconductors IP3048CX5
Integrated dual channel passive LC-filter network with ESD protection
6. Characteristics

[1] Guaranteed by design.
Table 4. Channel characteristics

Tamb = 25 °C; unless otherwise specified.
Rs(ch) channel series resistance - 0.25 0.35 Ω
Ls(ch) channel series inductance - 3 - nH
Cch channel capacitance Vbias(DC) = 2.5 V;
f = 100 kHz
[1] 150 190 225 pF
VBR breakdown voltage positive clamp;
Itest = 1 mA - 10 V
negative clamp;
Itest = −1 mA −10 - −6 V
ILR reverse leakage current per channel; VI = 3 V - - 1 μA
per channel; VI = −3 V −1 - - μA
Table 5. Frequency characteristics

Tamb = 25 °C; unless otherwise specified.
αil insertion loss Rgen = 50 Ω;
800 MHz < fi < 2 GHz
RL = 50 Ω - 35 - dB
RL = 4 Ω - 40 - dB
NXP Semiconductors IP3048CX5
Integrated dual channel passive LC-filter network with ESD protection
7. Application information

The setup for measuring insertion loss in a 50 Ω system is shown in Figure 3.
The insertion loss in a 50 Ω system for the two channels of the IP3048CX5 is shown in
Figure 4. The insertion loss is measured directly on the wafer with coplanar probes.
Unused pins are connected to ground with 50 Ω.
NXP Semiconductors IP3048CX5
Integrated dual channel passive LC-filter network with ESD protection
8. Package outline

Fig 5. Package outline IP3048CX5 (WLCSP5)
Table 6. Dimensions for Figure 5
0.61 0.65 0.69 mm 0.22 0.24 0.26 mm 0.39 0.41 0.43 mm 0.27 0.32 0.37 mm 1.09 1.14 1.19 mm 1.46 1.51 1.56 mm - 0.5 - mm - 0.435 - mm - 0.87 - mm
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