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IR2153STRPBFIRN/a120000avaiHalf Bridge Driver, LO In Phase with RT, Programmable Oscillating Frequency, 1.2us Deadtime in a 8-lead SOIC package


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IR2153STRPBF
Half Bridge Driver, LO In Phase with RT, Programmable Oscillating Frequency, 1.2us Deadtime in a 8-lead SOIC package
. Data Sheet No. PD60062 revO
I n Te i" n CD h 0 n C) l (NOTE:For new designs, we recommend
IR's new product IRS2153D)
19R Rectifier lR2153(D)(S)&(PbF)
SELF-OSCILLATING HALF-BRIDGE DRIVER
Features Product Summary
0 Integrated 600V half-bridge gate driver
lt 15.6V zener clamp on Vcc VOFFSET 600V max.
0 True micropower start up
0 Tighterinitial deadtime control Duty Cycle 50%
o Low temperature coefficient deadtime
o Shutdown feature (1/6th Vcc) on CT pin Tr/Tp 80/40ns
0 Increased undervoltage lockout Hysteresis (1V) V 15 6V
lt Lower power level-shifting circuit clamp .
o Constant LO, HO pulse widths at startup Deadtime (typ ) 1 2 HS
0 Lower di/dt gate driver for better noise immunity
o Low side output in phase with RT
lt Internal 50nsec (typ.) bootstrap diode (IR2153D) Packages
0 Excellent latch immunity on all inputs and outputs
o ESD protection on all leads
0 Also available LEAD-FREE
Description
The IR2153D(S) are an improved version of the 8Lead PDIP
popular IR2155 and IR2151 gate driver le, and incor-
porates a high voltage half-bridge gate driver with a front end oscillator similar to the industry standard CMOS
555 timer. The IR2153 provides more functionality and is easier to use than previous ICs. A shutdown feature
has been designed into the CT pin, so that both gate driver outputs can be disabled using a low voltage control
signal. In addition, the gate driver output pulse widths are the same once the rising undervoltage lockout
threshold on VCC has been reached, resulting in a more stable profile of frequency vs time at startup.
Noise immunity has been improved significantly, both by lowering the peak di/dt of the gate drivers, and by
increasing the undervoltage lockout hysteresis to 1V. Finally, special attention has been payed to maximizing
the latch immunity of the device, and providing comprehensive ESD protection on all pins.
Typical Connections
IR2153(S) IR2153D
l A/N/V 3):; A/VV 32;
- vcc VB —_[ - vcc VB -Cl
(N _ LT,
F--, HO -NNN- (n Fr, HO :1
RT VS l l RT vs l l
LT, i 57‘ i
J- CT LO " J- GT LO (n
Shutdowll COM shutdovvcl COM
'udr 1 'UCI- l
1

IR2153(D)(S)& (PbF)
NOTE:For new designs, we recommend
IR's new product IRS2153D
Absolute Maximum Ratings
International
TOR Rectifier
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and
power dissipation ratings are measured under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VB High side floating supply voltage -0.3 625
Vs High side floating supply offset voltage VB - 25 VB + 0.3
VH0 High side floating output voltage Vs - 0.3 VB + 0.3
VLO Low side output voltage -0.3 VCC + 0.3 V
VRT RT pin voltage -0.3 VCC + 0.3
VCT CT pin voltage -0.3 VCC + 0.3
ICC Supply current (note 1) - 25 mA
IRT RT pin current -5 5
dl/s/dt Allowable offset voltage slew rate -50 50 V/ns
PD Maximum power dissipation @ TA f +25°C (8 Lead DIP) - 1.0 W
(8 Lead SOIC) - 0.625
RthJA Thermal resistance, junction to ambient (8 Lead DIP) - 125 °C/W
(8 Lead SOIC) - 200
TJ Junction temperature -55 150
Ts Storage temperature -55 150 °C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol Definition Min. Max. Units
VBs High side floating supply voltage VCC - 0.7 VCLAMp
Vs Steady state high side floating supply offset voltage -3.0 (note 2) 600 V
Vcc Supply voltage 10 VCLAMP
ICC Supply current (note 3) 5 mA
TJ Junction temperature -40 125 °C
Note 1: This IC contains a zener clamp structure between the chip Vcc and COM which has a nominal breakdown
voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source
greater than the VCLAMP specified in the Electrical Characteristics section.
Note 2:
more than 5V.
Note 3:
voltage at this pin.

Care should be taken to avoid output switching conditions where the Vs node flies inductively below ground by
Enough current should be supplied to the Vcc pin of the 10 to keep the internal 15.6V zener diode clamping the

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