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IRL1004STRLPBF
40V Single N-Channel HEXFET Power MOSFET in a TO-262 package
HEXFET® Power MOSFET
Fifth Generation HEXFET® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer with
an extremely efficient and reliable device for use in a wide
variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL1004L) is available for low-
profile application.
VDSS = 40VDS(on) = 0.0065Ω
ID = 130AAdvanced Process TechnologyUltra Low On-ResistanceDynamic dv/dt Rating175°C Operating TemperatureFast SwitchingFully Avalanche RatedLead-Free
Description1
2Pak
IRL1004S
TO-262
IRL1004L
ParameterTyp.Max.UnitsRθJCJunction-to-Case–––0.75
RθJAJunction-to-Ambient ( PCB Mounted,steady-state)*–––40
Thermal Resistance°C/W
ParameterMax.UnitsID @ TC = 25°CContinuous Drain Current, VGS @ 10V 130
ID @ TC = 100°CContinuous Drain Current, VGS @ 10V 92 A
IDMPulsed Drain Current 520
PD @TA = 25°CPower Dissipation3.8W
PD @TC = 25°CPower Dissipation200W
Linear Derating Factor1.3W/°C
VGSGate-to-Source Voltage ± 16V
EASSingle Pulse Avalanche Energy700mJ
IARAvalanche Current78A
EARRepetitive Avalanche Energy20mJ
dv/dtPeak Diode Recovery dv/dt 5.0V/nsOperating Junction and-55 to + 175
TSTGStorage Temperature Range
Soldering Temperature, for 10 seconds300 (1.6mm from case)
Absolute Maximum RatingsLogic-Level Gate Drive
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)ISD ≤ 78A, di/dt ≤ 370A/μs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Starting TJ = 25°C, L = 0.23mH
RG = 25Ω, IAS = 78A. (See Figure 12)
Pulse width ≤ 300μs; duty cycle ≤ 2%.
ParameterMin.Typ.Max.Units ConditionsContinuous Source CurrentMOSFET symbol
(Body Diode)––––––showing the
ISMPulsed Source Currentintegral reverse
(Body Diode) ––––––p-n junction diode.
VSDDiode Forward Voltage––––––1.3VTJ = 25°C, IS = 78A, VGS = 0V
trrReverse Recovery Time–––78120nsTJ = 25°C, IF = 78A
QrrReverse RecoveryCharge–––180270nCdi/dt = 100A/μs
tonForward Turn-On TimeIntrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
130
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handing of the
package refer to Design Tip # 93-4
When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Uses IRL1004 data and test conditions
Source-Drain Ratings and Characteristics
ParameterMin.Typ.Max.Units Conditions
V(BR)DSSDrain-to-Source Breakdown Voltage40––––––VVGS = 0V, ID = 250A
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient–––0.04–––VCReference to 25C, ID = 1mA
0.0065VGS = 10V, ID = 78A
0.009ΩVGS = 4.5V, ID = 65A
VGS(th)Gate Threshold Voltage1.0–––VVDS = VGS, ID = 250A
gfsForward Transconductance63SVDS = 25V, ID = 78A
25VDS = 40V, VGS = 0V
––––––250VDS = 32V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage––––––100VGS = 16V
Gate-to-Source Reverse Leakage––––––-100nAVGS = -16VTotal Gate Charge––––––100ID = 78A
QgsGate-to-Source Charge––––––32nCVDS = 32V
QgdGate-to-Drain ("Miller") Charge––––––43VGS = 4.5V, See Fig. 6 and 13
td(on)Turn-On Delay Time–––16–––VDD = 20V,Rise Time–––210–––ID = 78A,
td(off)Turn-Off Delay Time–––25–––nsRG = 2.5Ω,Fall Time–––14–––RD = 0.18Ω, See Fig. 10
Between lead,––––––and center of die contact
CissInput Capacitance–––5330–––VGS = 0V
CossOutput Capacitance–––1480–––pFVDS = 25V
CrssReverse Transfer Capacitance–––320–––ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)RDS(on)Static Drain-to-Source On-Resistance
IDSSDrain-to-Source Leakage Current
3
Fig 4. Normalized On-ResistanceVs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics 10
100
1000
10000
0.1 1 10 100
20μs PULSE WIDTH
T = 25CJ°
TOP
BOTTOM
VGS
15V10V
7.0V
5.5V
4.5V4.0V
3.5V
2.7V
V , Drain-to-Source Voltage (V)
I , D
rre
t (A2.7V
10
100
1000
0.1 1 10 100
20μs PULSE WIDTH
T = 175CJ°
TOP
BOTTOM
VGS
15V
10V
7.0V5.5V
4.5V
4.0V3.5V
2.7V
V , Drain-to-Source Voltage (V)
I , D
-to
rce
rre
(A
2.7V
10
100
1000
V = 50V
20μs PULSE WIDTH
V , Gate-to-Source Voltage (V)
I , D
rre
t (A
T = 25 CJ°
T = 175 CJ°
T , Junction Temperature( C)
, D
-to
sista
ed)
on)==
10V
130A
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.Drain-to-Source Voltage
Fig 7. Typical Source-Drain DiodeForward Voltage 10 100
V , Drain-to-Source Voltage (V)
C, Capacitance (pF)C=
0V,C
f = 1MHz+ C
+ C
C SHORTEDGS
issgsgd ,ds
rssgd
ossdsgd
Ciss
Coss
Crss306090120150180
Q , Total Gate Charge (nC)
V , Gate-to-Source Vol
age (V)
FOR TEST CIRCUIT
SEE FIGURE =D
78 A= 20VDS= 32VDS
10
100
1000
V ,Source-to-Drain Voltage (V)
I ,
verse D
n C
rrent
(A)
V = 0 V GS
T = 25 CJ°
T = 175 CJ°
10
100
1000
10000 10 100
OPERATION IN THIS AREA LIMITEDBY RDS(on)
Single Pulse
= 175 C
= 25 C°J
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
10us
100us
1ms
10ms
5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.Case Temperature
Fig 10a. Switching Time Test CircuitVDS
90%
10%
VGS
td(on)trtd(off)tf
Fig 10b. Switching Time Waveforms ≤ 1
≤ 0.1 %
-5075100125150175
T , Case Temperature( C)
,
n C
entC
LIMITED BY PACKAGE
0.000010.00010.0010.010.1 1
Notes:
1. Duty factor D =t / t
2. Peak T=Px Z+ T2DMthJCC
t , Rectangular Pulse Duration (sec)
Ther
l R
sponse
)
D = 0.50
SINGLE PULSE(THERMAL RESPONSE)
D.U.T.VDSIG
3mA
VGS
.3µF
50KΩ
.2µF12V
CurrentRegulator
SameTypeasD.U.T.
CurrentSamplingResistors
Fig 13b. Gate Charge Test Circuit
Fig 12c. Maximum Avalanche EnergyVs. Drain Current5075100125150175
Starting T , Junction Temperature( C)
E ,
Si
ngl
e Pul
e Av
anc
e EnerD
TOP
BOTTOM
32A
55A
78A
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive WaveformsVDS
D.U.T.
VDD
IAS0.01Ω+p
VDS
IAS
VDD
V(BR)DSS
4.5 VGSQGD
Charge
Fig 13a. Basic Gate Charge Waveform4.5 V
