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JM38510/34102BEA |JM3851034102BEANSN/a282avaiDual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop
JM38510/34102BEA |JM3851034102BEANSC ?N/a10avaiDual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop
JM38510/34102BEA |JM3851034102BEANSCN/a46avaiDual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop


JM38510/34102BEA ,Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESETSDFS047A – MAR ..
JM38510/34102BEA ,Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-FlopGeneral DescriptionClear and Set are independent of clockThe ’F109 consists of two high-speed, comp ..
JM38510/34102BEA ,Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-FlopFeaturesAsynchronous Inputs:n Guaranteed 4000V minimum ESD protection.LOW input to S sets Q to HIGH ..
JM38510/34102BEA ,Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop54F/74F10954F/74F109 Dual JK Positive Edge-Triggered Flip-FlopNovember 199454F/74F109Dual JK Positi ..
JM38510/34102BFA ,Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flopelectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
JM38510/34104BEA ,Quad D Flip-FlopMILITARY DATA SHEETOriginal Creation Date: 05/17/96MN54F175-X REV 1A0Last Update Date: 07/30/96Last ..
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JM38510/34102BEA
Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description

The ’F109 consistsoftwo high-speed, completely indepen-
dent transition clockedJK flip-flops. The clocking operation independentofriseandfall timesofthe clock waveform.
TheJK design allows operationasaD flip-flop (referto ’F74
data sheet)by connectingtheJandK inputs.
Asynchronous Inputs:
LOW inputtoSD setsQto HIGH level
LOW inputtoCD setsQto LOW level
ClearandSetare independentof clock
Simultaneous LOWonCDandSD makes bothQandQ
HIGH
Features
Guaranteed 4000V minimum ESD protection.
Ordering Code:
See Section0
Commercial Military Package Package Description
Number

74F109PC N16E 16-Lead (0.300" Wide) Molded Dual-in-Line
54F109DM (Note2) J16A 16-Lead Ceramic Dual-in-Line
74F109SC (Note1) M16A 16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
74F109SJ (Note1) M16D 16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
54F109FM (Note2) W16A 16-Lead Cerpack
54F109LM (Note2) E20A 16-Lead Ceramic Leadless Chip Carrier, TypeC
Note1:
Devicesalso availablein13"reel.Use suffix= SCXandSJX.
Note2:
Military gradedevicewith environmentaland burn-in processing. Usesuffix= DMQB, FMQBand LMQB.
Logic Symbols

FAST®and TRI-STATE® areregistered trademarksof National SemiconductorCorporation.
DS009471-3 DS009471-4
IEEE/IEC

DS009471-6
November 1994
54F/74F109
Dual
Positive
Edge-T
riggered
Flip-Flop
54F/74F109
1997NationalSemiconductor Corporation DS009471 1
DSXXX
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