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L6393DSTN/a482avaiSmartDRIVE HV Half Bridge driver with Comparator


L6393D ,SmartDRIVE HV Half Bridge driver with ComparatorFeatures ■ High voltage rail up to 600 V ■ dV/dt immunity ± 50 V/nsec in full temperature range ■ D ..
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L6393D
SmartDRIVE HV Half Bridge driver with Comparator
August 2010 Doc ID 14497 Rev 4 1/19
L6393

Half-bridge gate driver
Features
High voltage rail up to 600 V dV/dt immunity ± 50 V/nsec in full temperature
range Driver current capability: 290 mA source, 430 mA sink Switching times 75/35 nsec rise/fall with 1 nF
load 3.3 V, 5 V CMOS/TTL inputs comparators with
hysteresis Integrated bootstrap diode Uncommitted comparator Adjustable dead-time Compact and simplified layout Bill of material reduction Flexible, easy and fast design
Application
Motor driver for home appliances Factory automation Industrial drives and fans HID ballasts Power supply units
Description

The L6393 is a high-voltage device manufactured
with the BCD “OFF-LINE” technology. It is a single
chip half-bridge gate driver for N-channel power
MOSFET or IGBT.
The high side (floating) section is designed to
stand a voltage rail up to 600 V.
The logic inputs are CMOS/TTL compatible down
to 3.3 V for easy interfacing microcontroller/DSP.
The IC embeds an uncommitted comparator
available for protections against overcurrent,
overtemperature, etc.
Table 1. Device summary
Contents L6393
2/19 Doc ID 14497 Rev 4
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
L6393 Block diagram
Doc ID 14497 Rev 4 3/19
1 Block diagram
Figure 1. Block diagram
Pin connection L6393
4/19 Doc ID 14497 Rev 4
2 Pin connection
Figure 2. Pin connection (top view)

Table 2. Pin description The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
L6393 Truth table
Doc ID 14497 Rev 4 5/19
3 Truth table

Note: X: don’t care
In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and
the resulting signal is in phase with the high side output HVG and in opposition of phase with
the low side output LVG. This means that if BRAKE is kept to high level, the PHASE signal
drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG
output. If BRAKE is set to low level the low side output LVG is always ON and the high side
output HVG is always OFF , whatever the PHASE signal. This kind of logic interface provides
the possibility to control the power stages using the PHASE signal to select the current
direction in the bridge and the BRAKE signal to perform current slow decay on the low sides.
From the point of view of the logic operations the two signals PHASE and BRAKE are
completely equivalent, that means the two signals can be exchanged without any change in
the behavior on the resulting output signals (see the Figure 1 on page 3).
Note: The dead time between the turn OFF of one power switch and the turn ON of the other
power switch is defined by the resistor connected between DT pin and the ground.
Table 3. Truth table
Electrical data L6393
6/19 Doc ID 14497 Rev 4
4 Electrical data
4.1 Absolute maximum ratings

Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (human body model)
4.2 Thermal data
Table 4. Absolute maximum ratings
Table 5. Thermal data
L6393 Electrical data
Doc ID 14497 Rev 4 7/19
4.3 Recommended operating conditions
Table 6. Recommended operating conditions
VBO = Vboot - Vout LVG off. VCC = 10 V. Logic is operational if Vboot > 5 V, refer to AN2785 for more details. At least one of the comparator's input must be lower than 2.5V to guarantee proper operation.
Electrical characteristics L6393
8/19 Doc ID 14497 Rev 4
5 Electrical characteristics
5.1 AC operation

VCC = 15 V , TJ = +25 °C
Table 7. AC operation electrical characteristics
See Figure 4 on page9 MDT = I DTLH - DTHL I see Figure 5 on page12
L6393 Electrical characteristics
Doc ID 14497 Rev 4 9/19
Figure 3. Timing
Figure 4. Typical dead time vs. DT resistor value
Electrical characteristics L6393
10/19 Doc ID 14497 Rev 4
5.2 DC operation

VCC = 15 V; TJ = +25 °C
Table 8. DC operation electrical characteristics
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