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PAL10016P8JC-PAL1016P8JC
-4.5 V, 100 K, ECL programmable array logic
National
Semiconductor
PAL10/10016P8
ECL Programmable Array Logic
General Description
The PAL1016P8/10016P8 is the first member of an ECL
programmable logic device family possessing common
electrical characteristics, utilizing an easily accommodated
programming procedure, and produced with National Semi-
conductor’s advanced oxide-isolated process. This family
includes combinatorial, and registered output devices.
These devices are fabricated using National's proven Ti-W
(Titanium-Tungsten) fuse technology to allow fast, officient,
and reliable programming.
This family allows the designer to quickly implement the de-
fined logic function by removing the fuses required to prop-
erly configure the internal gates and/or registers. Product
terms with all fuses removed assume a logical high state. All
devices in this series are provided with an output polarity
fuse that, if removed, will permit any output to independently
provide a logic low when the equation is satisfied. When
these fuses are intact the outputs provide a logic true (most
positive voltage level) in response to the input conditions
defined by the applicable equation. All input and l/O pins
have on-chip 50 kn pull-down resistors.
Fuse symbols have been omitted from the logic diagrams to
allow the designer use of the diagrams to create fuse maps
representing the programmed device.
All devices in this family can be programmed using conven-
tional programmers. After the device has been programmed
and verified, an additional fuse may be removed to inhibit
further verification or programming. This "security" feature
can provide a proprietary circuit which cannot easily be du-
plicated.
Features
tpD = 6 ns max
Eight combinatorial outputs with programmable polarity
Programmable replacement for conventional ECL logic
Both 10KH and 100K vo compatible versions
Simplifies prototyping and board layout
24-pin thin DIP packages.
Programmed on conventional TTL PLD programmers
D Security fuse to prevent direct copying
n Reliable titanium-tungsten fuses
Ordering Information
Programmable Array Logic
Family
ECL I/O Compatibility
10 = 10KH
100 = 100K
Number of Array Inputs
OutputType
P = Programmable Polarity
Number of Outputs
Package
J = 24-PinCeramic DIP
Temperature Range
C = Commercial:
0°C to + 75°C for 10KH
0''C to + 85°C for 100K
8d9l00l/0l'lVd 103
ECL PAL10/10016P8
Absolute Maximum Ratings
" Military/Aerospace specified devlces are required, Lead Temperature (Soldering, 10 seconds) 300''C
please contact the National Semiconductor Sales ESD Tolerance 1000V
Office/Dlstrlbutors for availability and specimtatiorts. CZAP = 100 pp
Temperature Under Bias (Ambient) -55'C to + 125''C FIZAp = 1500 n
Storage Temperature Range -65'C to + 150'C Test alPthe.d: tluma/.1, Botty Model
VEE R el ativ e t o Vcc _ 7V to + 0.5V Test Specification: NSC SOP-5-028
Any Input Relative to Vcc VEE to + 0.5V
Recommended Operating Conditions
Symbol Parameter Min Typ Max Units
VEE Supply Voltage 10 KH - 5.46 - 5.2 - 4.94 V
100k --4.73 -4.5 -4.27
Ri. Standard 10 kH/100k Load 50 n
CL Standard 10 kH/100k Load 5 pF
TA Operating Ambient Temperature 10 kH 0 + 75 "C
1 00k 0 + 85
Electrical Characteristics Over Recommended Operating Conditions.Output Load = 500 to -2.0V.
Symbol Parameter Condltlons TA Mln Max Unlts
VIH High Level Input Voltage Guaranteed input voltage 0°C - 1 170
high for all inputs 10 kH + 25°C --1130 mV
+ 75°C - 1070
100k WC to 85°C - 1165 - 880
" Low Level Input Voltage Guaranteed input voltage 0'C - 1480
low for all inputs 10 KH + 25''C - 1480 mV
+ 75'C - 1450
100k 0°C to 85°C - 1810 - 1475
VOH High Level Output Voltage VIN = VIH Max. or " Min. 0°C - 1020 -840
10 kH +25''C -980 --810 mV
+ 75°C - 920 - 735
100k 0°C to 85°C - 1025 -880
VOL Low Level Output Voltage VIN = VIH Max. or " Min. 0°C -1950 -1630
10 kH + 25''C - 1950 - 1630 mV
+75''C -1950 -1600
100k 0''Cto 85°C --1810 -1620
IIH High Level Input Current VIN = " Max. 10 KH 0°C
+ 75°C 220 p.A
100k 0°C to 85°C
le. Low Level Input Current VIN = " Min. Except " Pins 10 kH 0°C
+ 75°C 0.5 ”A
100k 0°C to 85''C
IEE Supply Current VEE = Max. All inputs and 10 kH 0'C to 75'C
ut t - 240 mA
o pu s We" 100k ty'C to 85°C
Note: This product family has been designed to meet the specification in me test table after thermal equilibrium has been established. The circuit is in a test socket
or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
RL = 500
ch 5pr
(INCLUDING JIG AND
Switching Characteristics
Over Recommended Operating Conditions; Output load: RL = 500 to --2.ov, CL = 5 pF to GND.
Symbol Parameter Test Conditions Min Typ Max Units
tpD Input to Output' 4 6 ns
tr Output Rise Time 0.5 1 2.5 ns
tt Output Fall Time 0.5 1 2.5 ns
'Measure tPD at threshold points
Connection Diagram
Dual-tn-Line Package
I _ l " - m:
t - t 23 - t
I - a " - I
w - t 21 - no
o - s 20 - o
vcco - 6 Is - vcco
o - 7 In - 0
vo - a " - no
I - ' Is -... I
I - to Is - I
l - 11 " -- I
vs; - 12 13 - I
TL/L/6161-2
Top View
PAL Design
The first step in designing a PAL device is the selection of
the appropriate device to accommodate the logic equations.
This is accomplished by partitioning the system into logic
blocks with a defined number of inputs and outputs. Next, a
device with an equal or greater I/O capability is selected to
implement each logic block. The assignment of inputs and
outputs to specific pins follows the device selection.
This device selection procedure is most easily accom-
plished with the use of computer software such as the
PLANTM package of programs by National Semiconductor
Corporation, but can be done manually using the logic dia-
gram and logic symbols provided in this document.
Specifying the Fuse Pattern
Once a device with pinout is selected, the fuse pattern may
be specified. The best procedure is the use of the PLAN, or
a similar software package which will create the fuse pattern
from the defined logic for the device and download the pat-
tern to a programmer. Most common device programmers
are provided with an RS-232 port which accesses the data
provided in JEDEC or a selected HEX format.
Logic diagrams can be translated to PAL logic diagrams if
desired. Fuses left intact are indicated on the logic diagram
by an "X" at the intersection of the input line and the AND
gate product line. A blown fuse is not marked. The PAL logic
diagrams are provided with no fuse locations marked, allow.
ing the designer to use the diagram to manually create a
fuse map. Actually, the unprogrammed device is shipped
with all Xs (fuses) intact. Each fuse node is identified by a
product tine number and an input line number.
Each device in the ECL PAL family has the capability for its
output polarity to be user-determined, The selection of out-
put polarity is logically determined by the equations and im-
plemented, if an active low output is required, by removing
the fuse representing the appropriate output.
National Masked Logic
If a large number of devices with the same pattern are re-
quired, it may be more economical to consider mask pro-
gramming. These mask-programmed devices will meet or
exceed all of the performance specifications of the fuse-
programmed devices they replace.
To generate a mask-programmed device, National Semi-
conductor requires a set of logic equations, written in a for-
mat such as PLAN, plus test vectors which the user gener-
ates as acceptance criteria for the finished product.
8d9l00l/0l'lVd 103
ECL PAL10/10016P8
Logic Diagram PAL1016P8/PAL10016P8
INPUT LINE NouBEil-r0 2 4 6 810 1214 1618 2022 24 26 2830
13 5 7 91113151719 2123 2527 2931
PRODUCT LINE #0
FIRST CELL NUMBER "
2049 Voc
JEDEC logic array cell number = product line first cell number + input line number.
Va: 2048
TL/L/61B1-3
Programming Specifleation
This specification defines the programming and verification
procedure for the first programmable logic devices in Na-
tionals generic ECL family. The internal fuse arrays consisis
of 64 product lines (8 for each output), each containing 32
fuse locations (1 for each ot 16 inputs and its complement)
for a total of 2048 array fuses. Eight additional fuses exist to
allow changing the active output polarity.
ECL LOGIC
owxlmuuuoau‘
TL/L/6161-5
Each ECL device is programmed and verified as a 2048x1
TTL PROM. The connection diagrams in Figure t illustrate
the difference between the logical ECL device and the PRO-
GRAMMABLE TTL device.
For a list of current software and programing support tools
available for these devices, please contact your local Na-
tional Semiconductor sales representative or distributor.
TTL PROGRAMMING
A-t 24 -e
A-2 23 "-h
A-s 22 -A
o-4 21 -o
o- s 20 -o
vm1- a 19 -a2
o- 7 18 -o
0-8 17 ---0
A-t) " -r'se
A-- 10 15 H1
A- It " -,
''sr-' 12 13 '-A
TLfLm181-t'
FIGURE I. Connection Diagrams
8d9l00l/0l'lVd 103
ECL PAL10/10016P8
Array Fuse Addressing Table III. Input Line Selection vs. Programmlng Address
When programming or verifying a fuse location, the output Inputs.
(equation1 is addressed by the .3 address pins 13, 14, and Input A d dress Pin
15. The eight product lines, within the equation, are selected
by the 3 address pins 9, IO, and 11. The fuse pair locations Line 23 22 3 2 1
representing the logical inputs are selected by the 4 ad-
dress pins 2, 3, 22, and 23, with the complementing fuse 0 0 0 0 0 0
within the pair by the address pin I. The programming ad- 1 0 0 0 0 1
dress data is detailed in Tables Hit. 2 0 0 0 1 0
Table I. Logic Output (Equation) Selection vs. 3 0 0 0 1 1
Programming Address Inputs. 4 0 0 1 0 0
. 5 0 0 1 0 1
Output Address Pin 6 0 0 1 1 0
Pin 15 14 13 7 o o 1 1 1
21 0 0 0 8 0 1 0 0 O
4 0 0 1 9 o 1 o o 1
20 0 1 0 10 0 1 0 1 0
5 0 1 1 11 o 1 o 1 1
7 1 0 1 13 o 1 1 o 1
17 1 1 o 14 0 1 1 1 0
8 1 1 1 15 0 1 1 1 1
Note that the sequence of outputs represent the physical not numeric order 16 1 0 O 0 0
of logical outputs. , I 17 1 0 O 0 1
18 1 0 0 1 0
Table II. Product Line (within Equation, or Output) vs. 19 1 0 0 1 1
Programming Address Inputs. 20 1 0 1 0 0
21 1 0 1 0 1
Product Address Pin 22 1 0 1 1 0
Pin 11 10 9 23 1 0 1 1 1
24 1 1 o 0 0
0 0 0 0 25 1 1 o o 1
1 0 0 1 26 1 1 o 1 o
2 0 1 0 27 1 1 o 1 1
3 0 1 1 28 1 1 1 o o
4 1 o 0 29 1 1 1 o 1
5 1 0 1 30 1 1 1 1 o
6 1 1 o 31 1 1 1 1 1
7 1 1 1
Note pin 1 affects complementing fuse only.
Fuse Programming and Verification
The array and output polarity fuse programming waveform
diagram is shown in Figure 2. The B output pins 0N are used
only to change the polarity of the selected device output
and for removing the ''stscurity" fuse. Tables 4 and 5 define
the voltage and timing requirements.
Programming Procedure
1. Power is applied to the device. VCC, VCC1, and VCC2
(pins 24, 6, and 19) go to VCC. (T he voltage applied to
pin 24 cannot precede the voltage applied to pin 6) The
output pins (4, 5, 7, 8, 17, 18, 20, and 21), are open cir-
cuited. or held at a logic low level, while programming the
array.
2. After T0, VCC1 (pin 6) can be raised from 5.0 to 10.75V at
a slew rate not to exceed 10V/pS, or not less
than IV/ws.
3. The 11 address inputs (pins 1-3, 9-11, 13-15, 22, and
23) will define the location of the array fuse to be opened
or the applicable output pin will define the polarity fuse to
be opened.
4. After VCC1 has been stable at 10.75V for period T1 and
the address has been stable defining the applicable fuse
location for period T2, VCC2 (pin 19) may slew from 5.0
to 10.75V at a slew rate of 1 to 10V/pS.
5. VCC2 must remain stable at 10.75V for the duration ot
the programming pulse (T P) before returning to 5.0V.
6. With VCC1 at 10.75V and after V002 has been stable at
5.0V tor the period T3, VER pin (16) may be sampled. If
the fuse was properly opened, a logic low level will be
observed. It the fuse did not open, steps 4 through 6 may
be repeated up to 15 times.
7.lf additional locations are to be addressed, steps 3
through 6 must be repeated for each fuse to be opened
while observing the maximum power up time and duty
cycle.
Fuse Verification
Fuse verification may be performed independent of pro-
gramming. As seen in Figure 2, with VCCt at VCCP and
VCC2 at VCC verification may occur within the defined tim-
ing constraints. (See Table V)
5mS MAXIMUM 20% DUTY CYCLE -----
0 -.1 te L.--.
Vccl cc
-ts--i N
0 te ----tr -
o POLARl'lY FUSE
N hr ADDRESSING
A ARRAY FUSE
VN Vu. ADDRESSING
--t b-- --t w-t --t
vor, 5 a 3 a
VER / N VALID VALID \
vol I l l
TL/L/6%-7
FIGURE 2. Array/Polarlty Programming Diagram
8d9l00l/0l1Vd 103
ECL PAL10/10016P8
TABLE N. DC Requirements
Symbol Description Mln Nom Max Units
V00 Pin 24 Voltage While Programming or Verifying (Pin
19 Verifying) (Note I) 4.75 5.00 5.25 V
'00 Pin 24 Current While Programming (Note 2) 200 300 mA
VCCp VCC1/Vccz (Pins 6 and 19) Voltage While 10.50 10.75 11.00 V
Programming (Note 3)
low V001 (Pin 6) Current While Programming (Note 2) 300 450 mA
[cog VCC2 (Pin 19) Current While Programming (Note 2) 1 0 25 mA
VIL Input LOW Level - If Left Open, Pins 4, 5, T, 8, 17, 0 0.8 V
18, 20, and 21 are Held Low by Internal 50K
Resistor
In. Input LOW Current - Pins; - 1.0 - 1.5 mA
1-3, 9-11, 13-15, 22, and 23
VCC/VCC1/VCCZ = Max, VIN = 0.4V
4, 5,7, 8, 17, 18, 20, and 21 (Note 4) -0.25 -1.5 mA
VCC/VCCI /VCC2 = Max, VIN = 0.8V
VIH Input HIGH Level 2.20 VCC V
IIH Input HIGH Current 90 300 WA
Vcc/Vcc1/Vcc2 = Max, VIN = Vcc Max
Pins I-3, 9-11, 13-15, 22, and 23
4, 5, 7, 8, 17, 18, 20, and 21 3 5 mA
VOL Output (Pin 16) LOW Level 0.8 V
VCC/VCC1/VCC2 = Min, IOL = 4 mA
VOH Output (Pin 16) HIGH Level 2.20 V
VCC/VCC1/VCC2 = Max, IOH = -0.6 mA
Note l.. While programming/veritying, power can be applied to the device for 5 ms maximum with a duty cycle of 20% maximum.
Note 2: Current measurements are taken with Vcc/ch/Vccz at maximum and with all device inputs and outputs open.
Note 3: The difference between Vcc and Vccp must not exceed 6V.
Note 4: It VIN (VIL) is less than 0.8 volts at pins 4, 5, 7, 8, 17, 18, 20, or 21, means must be provided to limit the current sourced by the device pins to 10 mA.
Note s.. All programming and verification to be panormed at 2S'C l 5'C
TABLE V. Timing
Symbol Descrlption Min Nom Max Units
T0 Power-Up Before Raising V351 (Note 1) 0 500 ns
T1 V001 at Vccp Before Raising V002 400 500 ns
T2 Address Set-Up Time to Vcca> Vccp 400 500 ns
T3 VER Valid After Vccg at Vcc (Note 2) 200 500 ns
T4 V002 at VCC Before Lowering V061 400 500 ns
T5 VER Valid After Raising Vcc1 (Note 2) 200 500 ns
T5b Address Set-Up Time to VER Valid (Note 2) 200 500 ns
T6 VER Valid Hold Time From Address 0 ns
T7 Vccz at Vcc Before Address Change 400 500 ns
T8 VER Valid Hold Time From VCCZ > Vccp (Note 2) 0 100 ns
T9 ch at V00 Before Power Down 0 ns
TP Programming Pulse 10 10 30 14,5
Note 1: Observe the maximum power-up time or 5 ms and duty cycle of 20% tor Vcc/Voc1 /Vcce during programming.
Note 2: VER is valid when V002 = Vcc and Vcc1 = Vccp.
Security Fuse Programming
The security fuse is opened using the same procedure as used for changing the output polarity, except all 8 outputs (pins 4, 5, 7,
8, 17, 18, 20, and 21) must be selected with the application otVtH. Verification is determined by the inability to further verify the
array.
-----5 ms MAXIMUM 20% DUTY CYCLE --------
0 -...u/ Nc-
- lo VccP ts
vcc1 _/ t L.
tt llep +44
o_/ L.
hrs t2 _ -1
0 ALL OUTPUTS HIGH
N ID SELECT SECURITY FUSE
TL/L/6181-8
FIGURE 3. Secuer Fuse Programming Diagram
SdQLOOL/Ol'lVd 103
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
PAL1016P8JC - product/pal1016p8jc?HQS=T|-nu|l-null-dscatalog-df-pf—nulI-wwe
PAL10016P8JC - product/pal10016p8jc?HQS=Tl-nulI-nulI-dscatalog-df—pf—nuII-wwe
