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PAL10016RM4AJC
100K, 4 ns, ECL registered programmable array logic
ECL PAL10/10016RM4A
[ National
Semiconductor
PAL10/10016RM4A
ECL Registered Programmable Array Logic
General Description
The PAL10/10016RM4A is a member of the National Semi-
conductor ECL PALO family. The ECL PAL Series-A is char-
acterized by 4 ns maximum propagation delays (combinato-
rial input-to-output). The pinout, JEDEC fuse-map format
and programming algorithm of these devices are compatible
with those of all prior ECL PAL products from National. Se-
ries-A ECL PAL devices are manufactured using National
Semiconductor’s advanced oxide-isolated process with
proven titanium-tungsten fuse technology to provide high-
speed user-programmable replacements for conventional
ECL SSl/MSI logic with significant chip-count reduction.
Programmable logic devices provide convenient solutions
for a wide variety of application-specitic functions, including
random logic, custom decoders, state machines, etc. By
programming fuse links to configure AND/OR gate connec-
tions, the system designer can implement custom logic as
convenient sum-of-products Boolean functions. System pro-
totyping and design iterations can be performed quickly us-
ing these off-the-shelf products.
The PAL10/10016RM logic array has a total of 16 comple-
mentary input pairs, 32 product terms and four output func-
tions; each output function is the OR-sum of 8 product
terms. The 16HM4A provides an edge-triggered D-type reg-
ister on each of its four outputs. Registers allow the PAL
device to implement sequential logic circuits. Polarity fuses
allow each output to be active-high or active-low.
Programming equipment and software make PAL design de-
velopment quick and easy. Programming is accomplished
using TTL voltage levels and is therefore supported by sev-
eral conventional TTL PLD programming units. After pro-
gramming and verifying the logic array, an additional securi-
ty fuse may be programmed to prevent direct copying of
proprietary logic designs.
Features
I: High speed:
tsu = 3 ns min
tCLK = 2 ns max
MAX = 200 MHz max (registered)
tpD = 4 ns max (combinatorial)
II Programmable replacement for ECL SSI/MSI logic
Both 10 KH and 100K IIO compatible versions
Four registered output functions with l/O pin feedback;
twelve dedicated inputs
Individually programmable polarity on all logic outputs
Reliable Titanium Tungsten fuses
Security fuse to prevent direct copying
Programmed on conventional TTL PLD programmers
Fully Supported by PLANT" Software
Packaging:
24-pin thin DIP (0.300")
24-pin Quad Cerpak
Ordering Information
The device number is used to form part of a simplified pur-
chasing code where a package type and temperature range
are defined as follows:
—-———— Programmable Array Logic Family
ECL l/O Compatibility:
10 = 10 kH
100 = 100K
Number of Arrays
Output Type:
RM = Registered with Multiple Clocks
Number of Registered Outputs
Speed/Power Version:
No Symbol = 6 ns tPD
A = 4 ns tpo
Package:
J = 24-Pin Ceramic DIP
W = 24-Pin Quad Cerpak
Temperature Range:
C = Commercial:
O'C to + 75"C for 10 KH,
O'C to + 85''C for 100k
PAL1016RM4AJC
Block Diagram
TL/L/9772-2
VEE = 12, Vcc = 24, Voco W,7) = 6, Vcco (18,20) = 19
Pinout applies to 24-pin DIP.
Absolute Maximum Ratings
lf Mllltary/Aerotrpatre specified devlces are required, Input Voltage VEE to + 0.5V
please contact the National Semiconductor Sales Output Current - 50 m A
ofmtefDitgtrhutors Pr availability and 1te,taltl,t, L a a d T emperaturs (Soldering, 10 s e c o n d s) 300.0
Temperature Under Bias -,E,f, to + 125 C ESD T ol e r a n c 9 wow
Storage Temperature Range -65 C to +150°C CZAP = 100 pp
VEE Relative to Vcc - 7V to + 0.5V HZAP = 1500.0
Test Method: Human Body Model
Test Specification: NSC SOP-5-028
Recommended Operating Conditions
Symbol Parameter Mln Typ Max Units
VEE Supply Voltage 10 KH -5.46 -5.2 -4.94 V
100K - 4.73 -4.5 - 4.27
T Operating Temperature 10 KH 0 + 75 "C
(Nota) 100K 0 + 85
RL Standard 10 KH/100K Load 50 n
Cr. Standard 10 KH/100K Load 5 pF
tsu Setup Time of Input or Feedback 3.0 ns
tH Input Hold Time 0 ns
tw Clock or Enable Pulse Width 2.0 ns
tWMR Master Reset Pulse Width 2.0 ns
Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter Conditions TA Min Max Units
Ihre High Level Input Voltage Guaranteed Input Voltage 0°C - 1 170 -840
High For All Inputs 10 KH + 25''C -It30 - 810 mV
+ 75°C - 1070 - 735
100K 0°C to +85''C -1165 -880
" Low Level Input Voltage Guaranteed Input Voltage 0°C - 1950 - 1480
Low For All Inputs 10 KH + 25°C - 1950 - 1480 mV
+ 75''C - 1950 - 1450
100K 0°C to +85''C -1810 -1475
VOH High Level Output Voltage VIN = VIH Max. or " Min. WC - 1020 -840
10KH +25''C -980 --810 mV
+ 75°C - 920 -735
100K 0°C to + 85''C - 1025 - 880
VOL Low Level Output Voltage " = ViH Max. or " Min. 0°C -1950 - 1630
10 KH + 25''C - 1950 - 1630 mV
+ 75"C - 1950 -1600
100K 0°Cto +85°C --1810 -1620
IIH High Level InputCurrent VIN = " Max. Inputs, IIOs
and MR 220 pA
Clocks 350
Il,. Low Level Input Current VIN = " Min. Except I/O Pins 0.5 p.A
IEE Supply Current VEE = Min., All Inputs and Outputs Open - 240 mA
Note: Operating temperatures for tpimuits in Dual-ln-Line packages are specified as ambient temperatures (TA) with circuits mounted in socket or printed circuit
board and transvelse tiflttw exceetrog 500 linear 1th per minute, Operating temperatures for circuits packaged in Quad Cerpak are specified as case tempera-
tures (T c). Ail spi'circations apply after thermal equilibrium has been established.
VPWHSIOOL/OHVd "103
ECL PAL10/1DO1GRM4A
Switching Characteristics Over Recommended Operating Conditions
Output Load: RL = 500 to --2.OV, CL = 5 pF to GND
Symbol Parameter Measured Mln Max Unlts
From To
tCLK Clock to Output or Feedback Cn t IIO 2.0 ns
tpD Input or Feedback to Output I I/O 4.0 ns
tMR Master Reset to Output MR t l/O l 3.5 ns
fMAx (Note 1) Maximum Frequency 200 MHz
tr Output Rise Time Measured Between 0.5 2.0 ns
t, Output Fall Time 20% and 80% points 0.5 2.0 ns
Note1:1MAx = (tsu + loud"
Test Load
TL/L/9772-3
Timing Waveform PAL10/10016RM4A
OUTPUT
50% 502,
tsu - ts,
I------ ku
- hm -/
---- tmm
TL/L/9772-4
Connection Diagrams
24-Pln DuaHn-Llne Package
PAL10/10016RM4A
HR- 1 24 “Va:
l-- 2 23 -l
l- 3 22 -t
l-- 4 21 -l
I/o- 5 20 --1/0
Vcoo‘ 6 19 'Vcco
IN- 7 18 -1/0
I- 8 17 .-l
Cl- 9 16 -CZ
l-- to 15 --l
I-- 11 14 --l
v- 12 13 '-cc
TL/L/g772-6
Pin Descriptions
Pln Description
I Twelve dedicated inputs to logic array.
l/O Four outputs from registered provides feedback and
may be used for additional inputs to logic array.
C1 Clock input ORed with CC to control registers on out-
put pins' 5 and 7. Data is written into registers on
rising edge of clock.
C2 Clock input ORed with CC to control registers on out-
put pins' 18 and 20. Data is written into registers on
rising edge of clock.
CC Common Clock input (see C1, C2).
MR Master Reset input. Asynchronously resets all regis-
ters to the low state while MR is high (overrides
clock input).
VEE Supply voltage.
Vcc Ground for internal circuitry.
Vcco Ground for Output drivers (2 outputs per V000).
'Corresponds to DIP pinout
Functional Description
The PAL10/10016RM consists of a single programmable
AND-gate array with fixed OR-gate connections. The AND
array consists of 16 complementary pairs of input lines
crossing 32 product-term lines with a programmable fuse at
each intersection (1024 fuses). The product terms are orga-
nized into four groups of eight each. The eight product
terms in each group are connected into an OR-gate to pro-
duce the sum-of-products logic function.
An unprogrammed fuse establishes a connection between
an input line (true or complement phase of an array input
signal) and a product term. Programming the fuse removes
the connection. A product term is satisfied (logically true)
while all the input lines connected to it (via intact fuses) are
in the proper logic state. Therefore, if both the true and
complement of at least one array input are left connected to
a product line, that product term would always be held in the
low logic state (which is the state of all product terms in an
unprogrammed device).
The tour outputs of the PAL10/10016RM4A pass through
D-type registers triggered on the high-going edge of the ap-
propriate clock input. The tour registers are separated into
two pairs. A separate clock input is provided for each pair.
An additional common clock input is ORed with each (see
logic diagrams which follow).
The AND-OR logic functions can be optionally inverted be.
fore the registers. Polarity inversion is controlled by an indi-
vidual "pofarity fuse" associated with each output function
(the original unprogrammed state produces active-high logic
functions). Device output pins always indicate active-high
register outputs.
The l/O pins used for outputting the registered logic func-
tions also feed back into the logic array as additional inputs.
This is useful, for example, to implement sequential circuits
with registered parts. Any of these vo pins may, instead, be
used as an additional dedicated input pin. By leaving the
associated logic function unprogrammed, the output driver
would remain in the low logic state allowing an externally-
applied signal to control the array input.
Logic functions requiring more than eight product terms can
be implemented conveniently by OH-tying two (or more) de-
vice outputs. Partial sums are formed on each of the OR-
tied output functions. Each function, however, must be pro-
grammed for active-high output polarity, and the associated
registers should be controlled by the same clock signal.
Each of the array inputs fed back from the OR-tied l/O pins
would indicate the correct final logic function.
All input and IIO pins have on-chip 50 kn pull-down resis-
Functional Testing
As with all iield-programrnable devices, the user of ECL PAL
devices provides the final manufacturing step. While Nation-
al's PAL devices undergo extensive testing when they are
manufactured, their logic function can be fully tested only
after they have been programmed to the user's pattern.
To ensure that the programmed PAL devices will operate
properly in your system, National Semiconductor (along with
most other manufacturers of PAL devices) strongly recom-
mends that PAL devices be functionally tested before they
are installed in your system. Even though the number of
post-programming functional failures is small, testing the
logic function of the PAL devices before they reach system
assembly will save board debugging and rework costs. For
more information about the functional testing of PAL devic-
es, please refer to National Semiconductor‘s Application
Note #351 and the Programmable Logic Design Guide.
VVWHQI-OOL/Ol'lVd 103
ECL PAL10/10016RM4A
Design Development Support
A variety of software tools and programming hardware is
available to support the development of designs using PAL
products. Typical software packages accept Boolean logic
equations to define desired functions. Most are available to
run on personal computers and generate JEDEC-compati-
ble "fuse maps". The industry-standard JEDEC format en-
sures that the resulting tuse-map files can be down-loaded
into a large variety of programming equipment. Many soft-
ware packages and programming units support a large vari-
ety of programmable logic products as well. The PLANTM
software package from National Semiconductor supports all
programmable logic products available from National and is
fully JEDEC-compatible PLAN software also provides auto-
matic device selection based on the designer's Boolean
logic equations.
Detailed logic diagrams showing all JEDEC fuse-map ad-
dresses for the PAL10/10016RM are provided for direct
map editing and diagnostic purposes. For a list of current
software and programming support tools available for these
devices. please contact your local National Semiconductor
sales representative or distributor. If detailed specifications
of the ECL PAL programming algorithm are needed, please
contact the National Semiconductor Programmable Device
Support Department.
Logic Diagram-PAL1016RM4AfPAL10016RM4A
DIP PIN
NUMBERS
DIP PIN l
NUMBERS
l INPUT LINE NoulEft-.0 t 4 s a 10 I214 151: 2022 24 26 2B m y 24
135191|1515I7I92l232527233I cc
PRODUCT LINE
FIRST CELL
NUMBER
JEDEC logic array cell number = product line first cell number + Input line number.
TL/tly77g-10
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
PAL10016RM4AJC - product/pal10016rm4ajc?HQS=TI-nu|l-nulI-dscataIog-df-pf-null-wwe
PAL10016RM4AWC - product/pal10016rm4awc?HQS=T|-nu||-nu|I-dscatalog-df—pf—nulI-wwe
PAL1016RM4AJC - product/pal1016rm4ajc?HQS=T|-nu|I-nulI-dscatalog-df—pf-nuII-wwe
PAL1016RM4AWC - product/pal1016rm4awc?HQS=TI-null-nuII-dscataIog-df—pf-nuII-wwe
