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PCF8593P-PCF8593T
Low power clock/calendar
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
CONTENTS FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
7.1 Counter function modes
7.2 Alarm function modes
7.3 Control/status register
7.4 Counter registers
7.5 Alarm control register
7.6 Alarm registers
7.7 Timer
7.8 Event counter mode
7.9 Interrupt output
7.10 Oscillator and divider
7.10.1 Designing
7.11 Initialization (see Fig.12) CHARACTERISTICS OF THE I2C-BUS
8.1 Bit transfer
8.2 Start and stop conditions
8.3 System configuration
8.4 Acknowledge
9I2C-BUS PROTOCOL
9.1 Addressing
9.2 Clock/calendar READ/WRITE cycles LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION
14.1 Quartz frequency adjustment
14.1.1 Method 1: Fixed OSCI capacitor
14.1.2 Method 2: OSCI Trimmer
14.1.3 Method 3: direct output PACKAGE OUTLINES SOLDERING
16.1 Introduction
16.2 DIP
16.2.1 Soldering by dipping or by wave
16.2.2 Repairing soldered joints
16.3 SO
16.3.1 Reflow soldering
16.3.2 Wave soldering
16.3.3 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
FEATURESI2 C-bus interface operating supply voltage: 2.5to 6.0V Clock operating supply voltage (Tamb =0to+70 °C):
1.0to 6.0V 8 bytes scratchpad RAM (when alarm not used) Data retention voltage: 1.0to 6.0V External RESET input resets I2 C interface (only) Operating current (fscl=0 Hz, 32 kHz time base,
VDD= 2.0 V): typ.1μA Clock function with four year calendar Universal timer with alarm and overflow indication 24 or 12 hour format 32.768 kHz or 50 Hz time base Serial input/output bus (I2 C-bus) Automatic word address incrementing Programmable alarm, timer and interrupt function Space-saving SO8 package available Slave address: READ A3 WRITE A2.
GENERAL DESCRIPTIONThe PCF8593 is a CMOS clock/calendar circuit, optimized
for low power consumption. Addresses and data are
transferred serially via the two-line bidirectional I2 C-bus.
The built-in word address register is incremented
automatically after each written or read data byte.
The built-in 32.768 kHz oscillator circuit and the first 8
bytes of RAM are used for the clock/calendar and counter
functions. The next 8 bytes may be programmed as alarm
registers or used as free RAM space.
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
5 BLOCK DIAGRAM
6 PINNING
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
FUNCTIONAL DESCRIPTIONThe PCF8593 contains sixteen 8-bit registers with an 8-bit
auto-incrementing address register, an on-chip
32.768 kHz oscillator circuit, a frequency divider and a
serial two-line bidirectional I2C-bus interface.
The first 8 registers (memory addresses 00to 07) are
designed as addressable 8-bit parallel registers. The first
register (memory address 00) is used as a control/status
register. The memory addresses 01to 07 are used as
counters for the clock function. The memory addressesto 0F may be programmed as alarm registers or used
as free RAM locations.
7.1 Counter function modesWhen the control/status register is programmed, a
32.768 kHz clock mode, a 50 Hz clock mode or an
event-counter mode can be selected.
In the clock modes the hundredths of a second, seconds,
minutes, hours, date, month (four year calendar) and
weekday are stored in a BCD format. The timer register
stores up to 99 days. The event counter mode is used to
count pulses applied to the oscillator input (OSCO left
open-circuit). The event counter stores up to 6 digits of
data.
When one of the counters is read (memory locationsto 07), the contents of all counters are strobed into
capture latches at the beginning of a read cycle. Therefore,
faulty reading of the count during a carry condition is
prevented.
When a counter is written, other counters are not affected.
7.2 Alarm function modesBy setting the alarm enable bit of the control/status register
the alarm control register (address 08) is activated.
By setting the alarm control register a dated alarm, a daily
alarm, a weekday alarm or a timer alarm may be
programmed. In the clock modes, the timer register
(address 07) may be programmed to count hundredths of
a second, seconds, minutes, hours or days. Days are
counted when an alarm is not programmed.
Whenever an alarm event occurs the alarm flag of the
control/status register is set. A timer alarm event will set
the alarm flag and an overflow condition of the timer will set
the timer flag. The open-drain interrupt output is switched
on (active LOW) when the alarm or timer flag is set
(enabled). The flags remain set until directly reset by a
write operation.
When the alarm is disabled (Bit 2 of control/status
register= 0) the alarm registers at addresses 08 to 0F may
be used as free RAM.
7.3 Control/status registerThe control/status register is defined as the memory
location 00 with free access for reading and writing via the2 C-bus. All functions and options are controlled by the
contents of the control/status register (see Fig.3).
7.4 Counter registersIn the clock modes 24 h or 12 h format can be selected by
setting the most significant bit of the hours counter
register. The format of the hours counter is shown in Fig.5.
The year and date are packed into memory location05
(see Fig 6). The weekdays and months are packed into
memory location 06 (see Fig.7). When reading these
memory locations the year and weekdays are masked out
when the mask flag of the control/status register is set.
This allows the user to read the date and month count
directly.
In the event-counter mode events are stored in BCD
format. D5 is the most significant and D0 the least
significant digit. The divider is by-passed.
In the different modes the counter registers are
programmed and arranged as shown in Fig.4. Counter
cycles are listed in Table1.
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
Table 1 Cycle length of the time counters, clock modes.
7.5 Alarm control registerWhen the alarm enable bit of the control/status register is
set (address 00,bit 2) the alarm control register
(address 08) is activated. All alarm, timer, and interrupt
output functions are controlled by the contents of the alarm
control register (see Fig.8).
7.6 Alarm registersAll alarm registers are allocated with a constant address
offset of hexadecimal 08 to the corresponding counter
registers (see Fig.4,Register arrangement).
An alarm signal is generated when the contents of the
alarm registers matches bit-by-bit the contents of the
involved counter registers. The year and weekday bits are
ignored in a dated alarm. A daily alarm ignores the month
and date bits. When a weekday alarm is selected, the
contents of the alarm weekday/month register will select
the weekdays on which an alarm is activated (see Fig.9).
Remark: in the 12 h mode, bits 6 and 7 of the alarm hours
register must be the same as the hours counter.
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
The timer (location 07) is enabled by setting the
control/status register = XX0X X1XX. The timer counts up
from 0 (or a programmed value) to 99. On overflow, the
timer resets to 0. The timer flag (LSB of control/status
register) is set on overflow of the timer. This flag must be
reset by software. The inverted value of this flag can be
transferred to the external interrupt by setting bit 3 of the
alarm control register.
Additionally, a timer alarm can be programmed by setting
the timer alarm enable (bit 6 of the alarm control register).
When the value of the timer equals a pre-programmed
value in the alarm timer register (location 0F), the alarm
flag is set (bit 1 of the control/status register). The inverted
value of the alarm flag can be transferred to the external
interrupt by enabling the alarm interrupt (bit 6 of the alarm
control register).
Resolution of the timer is programmed via the 3 LSBs of
the alarm control register (see Fig.11, Alarm and timer
Interrupt logic diagram).
Event counter mode is selected by bits 4 and 5 which are
logic1, 0 in the control/status register. The event counter
mode is used to count pulses externally applied to the
oscillator input (OSCO left open-circuit). The event counter
stores up to 6 digits of data, which are stored as hexadecimal values located in locations 1, 2, and 3.
Thus, up to 1 million events may be recorded.
An event counter alarm occurs when the event counter
registers match the value programmed in locations 9, A,
and B, and the event alarm is enabled (bits 4 and 5 which
are logic0, 1 in the alarm control register). In this event,
the alarm flag (bit 1 of the control/status register) is set.
The inverted value of this flag can be transferred to the
interrupt pin (pin 7) by setting the alarm interrupt enable in
the alarm control register. In this mode, the timer
(location 07) increments once for every one, one-hundred,
ten thousand, or 1 million events, depending on the value
programmed in bits 0,1 and 2 of the alarm control register.
In all other events, the timer functions are as in the clock
mode.
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
7.9 Interrupt outputThe conditions for activating the open-drain n-channel
interrupt output INT (active LOW) are determined by
appropriate programming of the alarm control register.
These conditions are clock alarm, timer alarm, timer
overflow, and event counter alarm. An interrupt occurs
when the alarm flag or the timer flag is set, and the
corresponding interrupt is enabled. In all events, the
interrupt is cleared only by software resetting of the flag
which initiated the interrupt.
In the clock mode, if the alarm enable is not activated
(alarm enable bit of control/status register is logic 0), the
interrupt output toggles at 1 Hz with a 50% duty cycle (may
be used for calibration). The OFF voltage of the interrupt
output may exceed the supply voltage, up to a maximum
of 6.0 V. A logic diagram of the interrupt output is shown in
Fig.11.
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
Philips Semiconductors Product specification
Low power clock/calendar PCF8593
7.10 Oscillator and dividerA 32.768 kHz quartz crystal has to be connected to OSCI
(pin 1) and OSCO (pin 2). A trimmer capacitor between
OSCI and VDD is used for tuning the oscillator (see
Chapter 14, Section 14.1). A 100 Hz clock signal is derived
from the quartz oscillator for the clock counters.
In the 50 Hz clock mode or event-counter mode the
oscillator is disabled and the oscillator input is switched to
a high-impedance state. This allows the user to feed the Hz reference frequency or an external high-speed
event signal into the input OSCI.
7.10.1 DESIGNING
When designing the printed-circuit board layout, keep the
oscillator components as close to the IC package as
possible, and keep all other signal lines as far away as
possible. In applications involving tight packing of
components, shielding of the oscillator may be necessary.
AC coupling of extraneous signals can introduce oscillator
inaccuracy.
7.11 Initialization (see Fig.12)
Note that immediately following power-on, all internal
registers are undefined and, following a RESET pulse on
pin 3, must be defined via software. Attention should be
paid to the possibility that the device may be initially in
event-counter mode, in which event the oscillator will not
operate. Over-ride can be achieved via software.
Reset is accomplished by applying an external RESET
pulse (active LOW) at pin 3. When reset occurs only the2 C-bus interface is reset. The control/status register and
all clock counters are not affected by RESET. RESET
must return HIGH during device operation.
An RC combination can also be utilized to provide a
power-on RESET signal at pin 3. In this event, the values
of the RC must fulfil the following relationship to guarantee
power-on reset (see Fig.12).
RESET input must be ≤0.3VDD when VDD reaches VDDmin
(or higher).
It is recommended to set the stop counting flag of the
control/status register before loading the actual time into
the counters. Loading of illegal states may lead to a
temporary clock malfunction.
