PDI1284P11DGG ,3.3V Parallel interface transceiver/bufferFEATURES DESCRIPTIONThe PDI1284P11 parallel interface chip is designed to provide an• Asynchronous ..
PDI1284P11DL ,3.3 V parallel interface transceiver/bufferINTEGRATED CIRCUITSPDI1284P113.3V Parallel interface transceiver/bufferProduct specification 1999 S ..
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PDI1284P11DGG-PDI1284P11DL
3.3V Parallel interface transceiver/buffer
Product specification
Supersedes data of 1997 Sep 15
1999 Sep 17
Philips Semiconductors Product specification
PDI1284P113.3V Parallel interface transceiver/buffer
FEATURES Asynchronous operation 8-Bit transceivers 6 additional buffer/driver lines peripheral to cable 5 additional control lines from cable 5V tolerant ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model Latch up protection exceeds 500 mA per JEDEC Std 19 Input Hysteresis Low Noise Operation IEEE 1284 Compliant Level 1 & 2 Overvoltage Protection on B/Y side for OFF-state A side 3-State option B side active or resistive pull up option Cable side VCC for 5V or 3V operation
DESCRIPTIONThe PDI1284P11 parallel interface chip is designed to provide an
asynchronous, 8-bit, bi-directional, parallel interface for personal
computers. The part includes all 19 signal lines defined by the
IEEE1284 interface specification for Byte, Nibble, EPP, and ECP
modes. The part is designed for hosts or peripherals operating at
3.3V to interface 3.3V or 5.0V devices.
The 8 transceiver pairs (A/B 1-8) allow data transmission from the A
bus to the B bus, or from the B bus to the A bus, depending on the
state of the direction pin DIR.
The B bus and the Y9-Y13 lines have either totem pole or resistor
pull up outputs, depending on the state of the high drive enable pin
HD. The A bus has only totem pole style outputs. All inputs are TTL
compatible with at least 400mV of input hysteresis at VCC = 3.3V.
QUICK REFERENCE DATA
ORDERING INFORMATION
Philips Semiconductors Product specification
PDI1284P113.3V Parallel interface transceiver/buffer
PIN CONFIGURATION
PIN DESCRIPTION
Philips Semiconductors Product specification
PDI1284P113.3V Parallel interface transceiver/buffer
LOGIC SYMBOL
PINS WITH PULL UP RESISTORS TO LOAD CABLE
FUNCTION TABLE = Side driving internal IC = Side driving external cable (bidirectional) = Side receiving control signals from internal cable = Side driving external cable (unidirectional) = Don’t care – control signals in = High Z or 3-State
O.C.= Open collector = Totem pole output = Resistive pull up: 1.4kΩ (nominal) on B/Y/C cable side and
VCC. However, while a B/Y side output is Low as driven by a
Low signal on the A side, that particular B/Y side resistor is
switched out to stop current drain from VCC through it. When DIR = L and OEA = H, the output signal is isolated
from the input signal. B1 – 8 signals maintain an rP = 1.4kΩ
on the input for this mode.
Philips Semiconductors Product specification
PDI1284P113.3V Parallel interface transceiver/buffer
ABSOLUTE MAXIMUM RATINGS1, 2
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. VOUT B/Y (tr) guarantees only that this part will not be damaged by reflections in application so long as the voltage levels remain in the
specified range.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product specification
PDI1284P113.3V Parallel interface transceiver/buffer
DC ELECTRICAL CHARACTERISTICS
NOTES: The pull up resistor on the B side outputs makes it impossible to test IOZ on the B side. This applies to the input current on the C side inputs
as well. Includes extra ICCB current from pull-up resistors, i.e. ICCBL = (#B + #C LOW inputs) * (VCCB/RPU).
