PHY1070 ,VCSEL Driver/Postamplifier with Digital Diagnosticsapplications. • Programmable mean power control loop The transmitter integrates a high speed output ..
PHY1071 ,125Mbps to 2.125Gbps VCSEL Driver/Postamp with Digital Diagnosticsapplications. • Programmable mean power control loop The transmitter integrates a high speed output ..
PHY1075 ,125Mbps to 4.25Gbps Laser Driver/Postamp with Digital Diagnosticsapplications. • Temperature compensated modulation current The transmitter integrates a high speed ..
PHY1078-01QS-RR ,125Mbps to 2.5Gbps FTTx Burst-Mode Laser Driver/Postamplifierapplications. Used with the • 7ns output switching in Burst Mode PHY1095 or PHY1097 transimpedance ..
PHY1078-01QT-RR ,125Mbps to 2.5Gbps FTTx Burst-Mode Laser Driver/PostamplifierApplications threshold and hysteresis. • GEPON Operating with a 3.3V supply and rated from -40 to • ..
PHY2078 ,125Mbps to 2.5Gbps FTTx Burst-Mode Laser Driver/PostamplifierApplications threshold and hysteresis. • GPON Operating with a 3.3V supply and rated from -40 to • ..
PLUS153BN ,Programmable logic arrays 18 ?42 ?10
PLUS153BN ,Programmable logic arrays 18 ?42 ?10
PLUS153BN ,Programmable logic arrays 18 ?42 ?10
PLUS16L8-7A , PAL devices
PLUS16L8-7A , PAL devices
PLUS16R4-7N , PAL devices
PHY1070
VCSEL Driver/Postamplifier with Digital Diagnostics
19-5681; Rev 2/12
1Gbps – 4.25Gbps VCSEL Driver / Post amp with Digital Diagnostics
Features • Multi-rate from 1Gbps to 4.25Gbps • VCSEL driver output stage with 16mA max
modulation drive and 20mA bias current • Programmable mean power control loop • Temperature compensated modulation current • Integrated limiting amplifier with selectable
swing CML output to reduce radiated emissions • Programmable receiver low pass filter • Integrated Loss Of Signal function • Digital diagnostic mode compliant with SFF-
8472 using an external MCU • Stand-alone mode where device parameters
are loaded from an external EEPROM • -40°C to +85°C operating range • 36pin 6mm x 6mm QFN package • Eye safety logic certified by TUV
Applications • Fibre Channel 1x, 2x, 4x • SFF and SFP Modules
Low Pass
Filter
RXOUT+
RXOUT-
RXIN+
RXIN-
TXIN+
TXIN-
VCSEL+
VCSEL-
TX_DISABLE
LOS
VCSEL_BIAS
TX_FAULTMPD
Internal
Registers
& 2 Wire I/F
SCL
SDASA_SCL
Safety
Logic
SA_SDA
Mean Power
Control Loop
ModulationTemperature
Comp
TSENSE
Driver
O/P
Level
Detect
Ref
RSSI
Ref
Voltage
Reg
MUX
SHUTDOWN
Description The PHY1070-01 is a combined VCSEL driver and
limiting amplifier with support for Digital Diagnostic
Monitoring for use within small form factor
modules for Fibre Channel applications.
The transmitter integrates a high speed output
stage with programmable bias and modulation
currents, controlled through a 2-wire serial
interface. The mean power control loop allows
connection in both common cathode and common
anode configurations.
A Loss Of Signal (LOS) detector is included with
detection based on either the receiver photo
detector average current or received signal
modulation amplitude.
When used in digital diagnostics mode the
integrated A/D converters measuring temperature,
TX Bias, Supply Voltage, RX Signal Strength and
Mean Power are read via a 2-wire serial interface.
An external Microcontroller Unit (MCU) is used for
calibrating real time diagnostic monitors and alarm
generation.
RATESEL
QFN36
SA_SDA1
RESET
VSS_RX
RXOUT+
RXOUT-
SDA
RREF
VDD_TX
VCSEL-
VSS_TX
VSS_TX
VDD_TXO
VCSEL_BIAS
SA_SCL
VDD_RXO
VDD_RXVSS_RXRXIN+RXIN-LOSSHUTDOWNTSENSERSSI
TX_FAULT
TX_DISABLE
TXIN+TXIN-
VSS_TXVSS_TX
MPD
SCL
VGG
VCSEL+
VDD_TX181936
PHY1070-01 A Maxim Integrated Products Brand The PHY1070-01 includes eye safety
features which have been certified by TUV for
use in Fibre Networks.
Table of Contents 1. Ordering Information .................................................................................................................................... 3
2. Pin Description ............................................................................................................................................. 3
3. Key Specifications........................................................................................................................................ 5
3.1. Absolute Maximum Ratings ................................................................................................................ 5
3.2. Continuous Ratings ............................................................................................................................. 5
3.3. Receiver .............................................................................................................................................. 5
3.4. Transmitter .......................................................................................................................................... 7
3.5. 2-Wire Serial Interface ...................................................................................................................... 10
3.6. Typical Operating Characteristics ..................................................................................................... 12
4. Functional Description ............................................................................................................................... 13
4.1. Overview ........................................................................................................................................... 13
4.2. Receiver Features ............................................................................................................................. 13
4.3. Transmitter Features ......................................................................................................................... 17
4.4. VCSEL Safety Features .................................................................................................................... 19
4.5. Tsense Temperature Sensor ............................................................................................................ 21
5. Control Interface ........................................................................................................................................ 22
5.1. Memory Map ..................................................................................................................................... 22
5.2. Operation........................................................................................................................................... 23
5.3. Digital Diagnostics Mode ................................................................................................................... 27
5.4. Stand-Alone Mode ............................................................................................................................ 29
5.5. 2-wire Serial Interface ....................................................................................................................... 31
6. Register Map .............................................................................................................................................. 33
7. Simplified Interface Models ........................................................................................................................ 42
8. Typical Applications ................................................................................................................................... 44
8.1. Power Supply Connections ............................................................................................................... 45
9. Packaging .................................................................................................................................................. 47
10. Contact Information.................................................................................................................................... 48
1. Ordering Information
Part Number Description Package PHY1070-01QD-RR Enhanced 4G VCSEL driver and Post
Amp
QFN36, 6mmx6mm in Tape and Reel;
RoHS-compliant (see Figure 41, p. 47)
PHY1070-01QS-RR
NOT FOR USE IN NEW DESIGNS Enhanced 4G VCSEL driver and Post
Amp
QFN36, 6mmx6mm in Tape and Reel;
RoHS-compliant (see Figure 41, p. 47)
2. Pin Description
Pin
No
Name Direction Type Description SA_SDA1,4 I/O LVTTL 2-wire serial interface. Connects to EEPROM in stand-alone mode RESET I/P CMOS Reset VDD_RXO2 Power Limiting amplifier output power supply VSS_RX3 Ground Receiver section ground connection RXOUT- O/P CML Limiting amplifier differential serial data output. RXOUT+ O/P CML Limiting amplifier differential serial data output. SDA4 I/O LVTTL 2-wire serial data interface. Used in Digital Diagnostics Mode. SCL4 I/P LVTTL 2-wire serial interface clock. Used in Digital Diagnostics Mode. RREF I/P Analog Connect to Ground through a 10k resistor
10 TX_FAULT O/P LVTTL
(open collector)
Transmit fail alarm. A logic 1 indicates a fault in the transmission
system. Requires external pull up for SFP MSA compliance
11 TX_DISABLE4 I/P LVTTL Output disable (active high). Disables VCSEL drive. On chip 8k pull
up
12 VSS_TX3 Ground Transmission circuitry ground connection
13 TXIN+ I/P CML Differential VCSEL driver input from host
14 TXIN- I/P CML Differential VCSEL driver input from host
15 RATESEL I/P LVTTL Toggles between two low pass filter characteristics. External 30k
pull down resistor required for SFP MSA compliance
16 VSS_TX3 Ground Transmission circuitry ground connection
17 NC No connection. Leave open circuit
18 MPD I/P Analog Monitor photodiode input
19 VCSEL_BIAS O/P Analog VCSEL bias current output
20 VDD_TX2 Power Transmission circuitry power supply connection
21 VDD_TXO2 Power Transmission circuitry power supply connection
22 VSS_TX3 Ground Transmission circuitry ground connection
23 VCSEL- O/P High speed VCSEL differential driver output
24 VCSEL+ O/P High speed VCSEL differential driver output
25 VSS_TX3 Ground Transmission circuitry ground connection
26 VGG Ground Ground substrate connection
27 VDD_TX2 Power Transmission circuitry power supply connection
28 SHUTDOWN O/P CMOS Gate drive for optional VCSEL shutdown FET switch
29 TSENSE I/P Analog External temperature sensing transistor connection
30 RSSI I/P Analog Receive signal strength indicator & regulated supply for Rx
photodiode
31 LOS O/P LVTTL
(open collector)
Loss of signal output. Requires external pull up for SFP MSA
compliance
32 RXIN+ I/P CML Limiting amplifier differential serial data input
33 RXIN- I/P CML Limiting amplifier differential serial data input
34 VSS_RX3 Ground Receiver ground connection
35 VDD_RX2 Power Limiting amp power supply
36 SA_SCL1,4 I/P LVTTL EEPROM 2-wire serial interface clock PADDLE Ground Ground / Thermal Paddle
1 Used in stand-alone mode only.
2 All VDDs are internally connected by back-to-back protection diodes. VDDs should not be powered up independently.
3 All VSSs are internally connected to the IC substrate connection. 4 Internally pulled high with an 8kΩ pull-up resistor.
3. Key Specifications 3.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Unit Supply Voltage - 0.5 +6.5 V
Voltage on any pin VSS - 0.5 VDD + 0.5 V
Storage Temperature 150 °C
Soldering Temperature For 25 seconds 260 °C
Junction Temperature 140 °C
ESD Human Body Model 2 kV
Under absolute maximum rating conditions device not guaranteed to meet specifications; permanent damage
may be incurred by operating beyond these limits.
3.2. Continuous Ratings
Parameter Conditions Min Typ Max Unit Operating Supply Voltage Continuous operation 2.97 3.3 3.63 V
Current consumption Excluding bias & modulation
at 10mA bias & 8mA modulation 102 mA
Operating temperature Ambient Still Air, Max Bias and Modulation
Current -40 25 +85 °C
3.3. Receiver
3.3.1. Receive Limiting Amplifier
Parameter Symbol Conditions Min Typ Max Unit Sensitivity Differential, BER=1*10-12 <2.125Gbps
<4.25Gbps 5
6.5
7.5
10 mVpp
Max Differential Input Overshoot and TJ within spec 1200 mVpp
Input Termination
Impedance Differential RXIN+ to RXIN-, DC 100 Ω
Input Return Loss Differential, f<4GHz, device powered on 10 dB
Output Return Loss Differential, f<4GHz, device powered on 10 dB
Low Frequency Cutoff High pass 3dB point for RX system 15 kHz
Output Rise and Fall
Times (20%-80%) 2125 Mbps, Rx_slew = ‘1’ 120 160
ps 4250 Mbps, Rx_slew = ‘0’ 60 80
Differential Output
Swing High swing mode1
Low swing mode1 700
370 900
470 mVpp
Total Jitter, Tj Measured over RX input voltage range 100 mUI pp
Output Resistance RXOUT+/- Single ended to VDD_RXO 40 50 60 Ω
Rate select change time t_ratesel Using RATESEL pin 10 µs
1 Receiver differential output swing characterised at 155Mbps and 27-1 PRBS using DCA eye amplitude function
3.3.2. RSSI Indicator and Rx PD Regulator
Parameter Symbol Conditions Min Typ Max Unit Voltage on RSSI pin Ireg=2mA (10nF & 100Ω minimum load) 2.4 V
Current sourced by
RSSI pin Measured using Rx Power ADC 0 2000 µA
3.3.3. Receive Photocurrent LOS
Parameter Symbol Conditions Min Typ Max Unit RSSI LOS assert time 10 µs
RSSI LOS de-assert
time 40 µs
Electrical Hysteresis 20log10 (RSSIdeassert / RSSIassert) 2 4 dB
RSSI LOS assert level
range Set by AVG_LOS_set, Address F4h 4.0 411 µA
3.3.4. OMA LOS
Parameter Symbol Conditions Min Typ Max Unit OMA LOS assert time t_loss_on 100 µs
OMA LOS de-assert
time
t_loss_off 20 µs
Electrical Hysteresis 20log10 (Vdeassert / Vassert) 2.5 5.5 dB
OMA LOS assert level Set by OMA_LOS_set, Address F3h 10 50 mV
t_loss_ont_loss_off
OMA
Signal
LOS
Figure 3 - OMA LOS Detection
3.4. Transmitter
3.4.1. Transmitter Inputs
Parameter Symbol Conditions Min Typ Max Unit High-Speed Data Input
Signal Voltage1 Differential, AC-coupled, from 1Gbps to
4.25Gbps 200 2400 mVpp
High-Speed Data Input
Impedance Differential, DC 80 100 120 Ω
Input Return Loss Differential, f<4GHz, device powered on 10 dB
Input common mode
return loss Both inputs shorted together, measured using
25Ω source termination, 100MHz – 2.5GHz 10 dB
3.4.2. VCSEL Driver
Parameter Symbol Conditions Min Typ Max Unit Modulation Current Imod 0.5 16 mA
Electrical 20% to 80%
rise / fall time Measured using 50Ω effective termination, AC
and DC coupled applications 55 65 ps
Total Jitter contribution Measured over modulation current range 100 mUI pp
VCSEL output
compliance range Allowed voltage for VCSEL driver output pins in
dynamic operation, referenced to ground
(VSS_TX).
600 mV
Bias current output
compliance Minimum allowed voltage for pin VCSEL_BIAS,
referenced to ground (VSS_TX) 300 mV
3.4.3. VCSEL Mean Power Control Loop
Parameter Symbol Conditions Min Typ Max Unit Bias Current 0.1 20 mΑ
Bias current off Transmitter disabled 10 µA
Max current at MPD pin Sink current 2.6 mA
Turn on/off overshoot Bias current overshoot, Loop_BW=1 15 %
APC -3dB Loop
Bandwidth fLoop_BW Loop_BW = “0”
Loop_BW = “1” 5
15 kHz
Bias loop settling time t_settle Loop_BW = “0”
Loop_BW = “1” 5
500
10
1000
ms µs
3.4.4. Eye Safety Internal Fixed Limits
Operation outside these limits causes a TX_FAULT to be asserted
Parameter Symbol Conditions Min Typ Max Unit High supply voltage
assert limit VeyeHa 3.75 4.10 V
High supply voltage
de-assert limit VeyeHd 3.65 4.05 V
High Supply
Hysteresis 0.05 0.15 V
Low supply voltage
assert limit VeyeLa 2.70 2.95 V
Low supply voltage
de-assert limit VeyeLd 2.75 2.95 V
Low Supply Hysteresis 0.01 0.15 V
RREF pin voltage limit RREF voltage applied to pin after calibration 0.9 1.1 V
3.4.5. Fault Timing
Parameter Symbol Condition Min Typ Max Unit Time to initialize t_init From power on or application of Vcc>2.97V
during plug in 300 ms
Hard TX_DISABLE
assert time
t_off Time from rising edge of TX_DISABLE to when
the optical output falls below 10% of nominal 2 µs
Hard TX_DISABLE
negate time
t_on Time from falling edge of TX_DISABLE to when
the modulated optical output rises above 90%
of nominal 1 ms
Hard TX_Fault assert
time
t_fault Time from fault to TX_FAULT on 100 µs
TX_DISABLE pulse
width
t_reset Time TX_DISABLE must be held high to reset
TX_FAULT µs
TX_FAULT deassert
time
t_faultdass Time to deassert TX_FAULT after
TX_DISABLE 300 ms
3.4.6. Diagnostic Timing Diagrams
TX_FAULT
VCC>2.97
TX_DISABLE
VCSEL_BIAS
t_initt_offt_on
Figure 4 - Device turn on
TX_FAULT
TX_DISABLE
VCSEL
Transmitting
t_fault
Occurrence of
Fault
t_resett_faultdass
Figure 5 - Fault detection
3.5. 2-Wire Serial Interface
3.5.1. AC Electrical Characteristics
Parameter Symbol Comment Min Typ Max Unit SCL clock frequency fSCL 0 100 kHz
LOW period of the SCL
clock
tLOW 4.7 – µs
HIGH period of the SCL
clock
tHIGH 4.0 – µs
Set-up time for a
repeated START
condition
tSU:STA 4.7 – µs
Hold time (repeated)
START condition
tHD:STA 4.0 – µs
Data hold time tHD:DAT 0 3.45 µs
Data set-up time tSU:DAT 250 – ns
Rise time of both SDA
and SCL signals
tR – 1000 ns
Fall time of both SDA
and SCL signals
tF – 300 ns
Set-up time for STOP
condition
tSU:STO 4.0 – µs
Bus free time between a
STOP and START
condition
tBUF
4.7 – µs
Output fall time from
VIHmin to VILmax
tof 10pF < Cb(1 ) < 400pF 0 250 ns
Capacitance for each
I/O pin
Ci – 10 pF
1 Cb = capacitance of a single bus line in pF. HD:STA
tSU:STAHIGHtLOW
tSU:DATtHD:DATtF
tSU:STOtBUF
SDA
SCLt
Figure 6 - SDA and SCL bus timing
3.5.2. DC Electrical Characteristics
Parameter Symb
ol Condition Min Typ Max Unit Low level input voltage VIL - 0.5 0.3 VDD V
High level input voltage VIH 0.7 VDD VDD + 0.5 V
Low level O/P voltage VOL 3 mA sink current 0 0.4 V
I/P current each I/O pin Ii 0.1VDD < Vi < 0.9VDD -10 10 mA
3.5.3. DC Characteristics: TX_FAULT; TX_DISABLE; LOS.
Parameter Comment Min Typ Max Unit LVTTL Voltage Out High External 4.7k to 10k pull-up Host VCC
- 0.5 Host VCC
+ 0.3 V
LVTTL Voltage Out Low External 4.7k to 10k pull-up 0 0.5 V
LVTTL Voltage In High Internal pull-up 2.0 VDD
+ 0.3 V
LVTTL Voltage In Low Internal pull-up 0 0.8 V
R pull-up Internal pull-up 6 10 kΩ
3.6. Typical Operating Characteristics
3.6.1. Electrical Receiver Eye Diagrams (3.3V; Ta = 25oC; PRBS 27-1)
Figure 7 - 4.25Gbps Low swing mode
Figure 8 - 4.25Gbps High swing mode
3.6.2. Optical Transmit Eye Diagrams (3.3V; Ta = 25oC; PRBS 27-1)
Transmitter setup with Pmean = -4.5dBm; E.R. =8.5dB; OMA=500µW
Figure 9 - 4.25Gbps; 60% margin
Figure 10 - 4.25Gbps; unfiltered rise and fall times
4. Functional Description 4.1. Overview
RSSI
RAM
VCSEL safety
2-wire
slave
LOS
AGC
Receiver
LOS
CML
RXIN+
RXIN-
Programmable
LPF
Modulation
DAC
Mean power
DACBias current
VCSEL+
VCSEL-
VCSEL_BIAS
MPD
Transmitter
Safety
critical
shutdown
SHUTDOWN
TX_FAULT
Control interface
2-wire
master
Control
registersController
TX_DISABLE
RXOUT+
RXOUT-
TXIN+
TXIN-
RESET
SDA
SA_SDA
SA_SCL
SCL
TSENSE
RREF
Temperature
ADC
RATESEL
Comp
Figure 11 - Top-level block diagram of the PHY1070-01
4.2. Receiver Features
The receiver input is designed to be AC-coupled to the transimpedance amplifier, with internal 100Ω
differential termination. The AGC amplifier is followed by a low-pass filter with programmable cut-off
frequency, enabling the PHY1070-01 receiver to support five discrete data rates in the range 1 Gbps to
4.25 Gbps.
The filter output is followed by a limiting stage. For minimum duty cycle distortion, DC feedback from the
limiter output is used for offset cancellation.
The output CML buffer completes the receiver chain, delivering the output at pins RXOUT+ and RXOUT-.
The output edge rate is dependent on the programmable filter setting. Additionally, the output swing is
programmable to satisfy different interface requirements (e.g. CML, ac-coupled LVPECL compatible).
The PHY1070-01 includes a regulator to deliver a controlled voltage to the receiver photodiode cathode at
the RSSI pin. The current at RSSI is digitized for use in measuring the received signal strength. This
signal can also be used to generate a Loss of Signal (LOS) alarm, with a pre-set hysteresis for assert and
de-assert levels. The LOS assert threshold can be adjusted using the LOS LEVEL DAC.
Alternatively, the LOS alarm can be programmed to detect the amplitude of the AC signal, representative
of the Optical Modulation Amplitude (OMA) at the receiver input. The OMA LOS assert threshold can be
adjusted using the RX AMP DAC.
4.2.1. Input Stage Configuration
The differential RXIN inputs from the ROSA can be terminated to a common mode voltage. This should be
used for all recommended application frequencies of the PHY1070-01, where the inputs are AC coupled.
The common mode voltage should be connected by setting RX_dccouple = ‘0’ (E8h rxControl0 bit 3).
4.2.2. Rate Selection
Figure 12 - Low pass filter rate selection
A programmable low pass filter provides band limiting in the received signal path. The filter bandwidth is
set to 0.75 x signal data rate for optimum signal to noise performance and is controlled by a 3-bit control
word as shown in Table 1.
The rate selection register, rateSel, stores two 3-bit codes for controlling the filter; code A in bits 0 to 2,
and code B in bits 3 to 5. The selection between the two codes is determined by the RATESEL pin and
the Soft Rate Select bit as shown in Figure 12. Thus, the RATESEL pin can be used to switch between
two pre-selected rates.
The rateSel register is unique in that it is directly accessible from the 2-wire serial slave interface. Write
accesses are routed to both the register in hardware and the RAM. Read accesses read the rateSel value
from the hardware. This enables the PHY1070-01 to respond more quickly to updates of this register.
Table 1 - Signal data rates supported by the low pass filter
4.2.3. CML Output Stage Configuration
The CML output stage has two slew rate settings. For maximum receiver eye opening set CMLslew = ‘0’
(E8h rxControl0 bit 0). To minimise emitted radiation set CMLslew = ‘1’. The slew rates are defined in the
table of Parametric Performance characteristics for the Receive limiting amplifier (Section 3.3.1).
The signal swing can also be adjusted. Set HiLoSwing = ‘1’ (E9h rxControl1 bit 1) for higher amplitude
differential output swing as defined in the table in section 3.3.1. Set HiLoSwing = ‘0’ for lower amplitude
Bit
2 1 0
Data Rate 0 0 N/A 0 1 N/A 1 0 1062 Mbps 1 1 1250 Mbps 0 0 2125 Mbps 0 1 2488 Mbps 1 0 4250 Mbps 1 1 N/A
signal
outRATESEL
F5h
0 - 2RateselA
RateselB
rateSel
Programmable
low-pass
filter
bit 3Soft Rate Select
STAT_CON
signal
6Eh
3 - 5
4.2.4. Loss Of Signal
RXIN+
RSSI
RX AMP
DAC
OMA based LOSRXIN-
E8h
bit 2
bit 1
LOSpolarity
LOStype
rxControl0Amplitude
detect
LOS
LEVEL
DAC
Power
detect
Rx Power
ADC
OMA_LOS_setF3h
rxPowerADCFBh
AVG_LOS_setF4h
Mean Rx power based LOSLOS
LOS
STAT_CON6Eh
bit 1
Figure 13 - Control of the LOS pin
Loss of signal (LOS) is determined in one of two ways. If
LOStype = ‘1’ then the optical modulation
amplitude (OMA) method is selected. The signal amplitude measured at RXIN+/- is compared against a
threshold level set by the
OMA_LOS_set register. If the OMA does not exceed the threshold then the LOS pin and consequently the LOS bit in STAT_CON will be asserted.
If LOStype = ‘0’ then the mean received power based method is selected. The signal power detected on
the receiver signal strength indicator (RSSI) pin is compared against a threshold level set by
AVG_LOS_set. If the RSSI does not exceed the threshold then the LOS pin and LOS bit are asserted. The polarity of the LOS pin is controlled by LOSpolarity. If LOSpolarity = ‘0’ then LOS is set high during
a loss of signal condition. Conversely, if LOSpolarity = ‘1’ then LOS is set high when a signal is detected.
Register DAC Step Size Threshold Range AVG_LOS_set LOS LEVEL DAC
(8 bits)
For Codes 00h – 1Fh Step Size =1.3µA±0.4µA
For Codes 1Fh – 7Eh Step Size = 4.6µA±1.0µA
0µA to 31µA
31µA to 411µA
OMA_LOS_set RX AMP DAC
(8 bits)
Use Codes 28h to C8h Step Size = 250µV
(nominal DAC range = 0mV to 64mV)
10mV to 50mV
Table 2 - LOS DAC characteristics
For measurement of RSSI, which is used by SFF-8472 Digital Diagnostics Monitoring, the PHY1070-01
can be connected as shown in Figure 14, sourcing the photodiode bias current. This shows a PHY1094
TIA interfacing to the PHY1070-01. The photodiode used is biased using the regulated output of the
PHY1070-01, providing a stable and low noise bias for the photodiode. The PHY1070-01 measures the
photodiode current and generates a report of received signal strength via an on board A-D converter.
RXIN+
AMP
ProgrammableProgrammable
Low Pass Filter &
Output Buffer
LOS
ADCRSSI
LOS
Overload
DC Restore
50Ω50Ω
AGC
Amp
Voltage
Regulator
PDA
FILT
RX+
RX-
VCC
GNDA
PDC
100ΩAmplifier
RXOUT-
RXOUT+
PHY1070-013.3V
RXIN-
AMP
LOS
Signal Detect &
VCC
GNDA
Amplifier
PHY1094LOS
DAC
Photodiode
Regulator
100Ω
1nF
Figure 14: Connection to TIA for RSSI method of LOS detection
In some cases the TIA may source an output current which is proportional to the Received Signal
Strength. In this case the application circuit shown in Figure 15 should be used. The current IRSSI is
mirrored using a dual NPN transistor as shown. This sinks an output current from the PHY1070-01 which
can then be measured using the on chip ADC.
RXIN+
AMP
ProgrammableProgrammable
Low Pass Filter &
Output Buffer
LOS
ADCRSSI
LOS
Overload
Voltage
Regulator
PDA
RX+
RX-
VCC
PDC
100Ω
RXOUT-
RXOUT+
PHY1070-013.3V
RXIN-
AMP
LOS
VCC
GNDA
Amplifier
TIALOS
DAC
Photodiode
Regulator
BCV61 or Similar
IRSSI
Figure 15: Connection to TIA with integrated RSSI output
4.3. Transmitter Features
The transmitter input buffer provides the necessary drive to the VCSEL driver output stage. It is designed
to be AC-coupled, with an internal 100Ω differential termination.
The VCSEL driver output is designed to drive VCSELs in both common-cathode and common-anode
configurations, using either AC or DC coupling. The driver circuit delivers a maximum peak to peak
modulation current of 16mA. The maximum current delivered in DC-coupled mode is dependent on the
VCSEL impedance. The voltage swing must remain in the compliance range of the output stage as
specified in section 3.4.2.
The PHY1070-01 VCSEL driver operates with an analog mean-power control loop, which is digitally
programmed using the Mean Power DAC. Modulation current is controlled by a VCSEL modulation DAC
with the characteristics shown in Table 3. The modulation DAC has a 75μA/bit resolution which suggests
an upper limit of 19.1mA at full scale, however the modulation output stage is rated to 16mA over
operating temperature and voltage only for jitter compliance. To satisfy the digital diagnostics
requirements, the mean power, as represented by the monitor photocurrent, is measured using the MPD
current monitor analogue to digital converter (Tx Power ADC). The bias current ADC (Tx Bias ADC)
samples the VCSEL bias current.
Register DAC Step Size Range tx_power_set Mean Power DAC
(8 bits)
12µA
(Actual DAC range 0μA to 3060μA)
0 to 3mA
modulationDACDefault VCSEL modulation DAC1 (8
bits)
75µA
(Actual DAC range 0.5mA to 19.1mA)
0mA to 16mA
1 Range of modulation current measured at VCSEL+/- (jitter within spec)
Table 3 - Characteristics of the modulation and bias current DACs
4.3.1. Bias Current Control
E0h
1 - 2Kselect
txControl1
DFh
bit 1Loop_BW
txControl0
MPDtx Power ADCFDh
VCSEL_BIAS
tx_power_setF2h
txBiasADCFCh
Tx Power
ADC
Mean
Power
DAC
Comp
Kfactor
Tx Bias
ADC
Figure 16 - Control registers affecting the APC loop
The VCSEL bias current is controlled by the mean-power control loop in which the current from the
monitor photodiode in the TOSA is compared with a reference current controlled by tx_power_set. The
mean-power control loop can be configured for either common-cathode or common anode VCSELs using
the MPC_polarity bit of the txControl0 (DFh) register.
Note: the comparator is sensitive to large step changes in the value written to tx_power_set (or a small
step change at low values). This can cause the safety critical shutdown module to assert a TX_FAULT, as
will writing zero to tx_power_set.
Loop bandwidth and Kselect are used to optimise APC loop dynamics providing stability of the mean
power control and the required transmitter start up time. These settings are affected by the coupling
coefficient (Kfactor) between the Laser and monitor photodiode. The Kselect bits shown in Table 4 should
Table 4 shows Kselect values that can be chosen to meet the start-up time and APC loop stability
requirements:
Kselect
1 0
Coupling
coefficient 0 1/500 – 1/150 1 1/150 – 1/50 0 1/50 – 1/25 1 1/25 – 1/8
Table 4 – Kselect guide for the APC loop
The bandwidth of the control loop response can be controlled with
Loop_BW. For a critically damped loop, set Loop_BW to ‘0’. For a more rapid response, set Loop_BW to ‘1’. The frequency response of the
loop is detailed in section 3.4.3 VCSEL Mean Power Control Loop.
4.3.2. Modulation Current Control
The modulation current can be controlled in two ways:
Set
ModLUTdisab (DFh
txControl0 bit5) to ‘1’ to directly access the modulation DAC. Then, adjust
modulation current by writing to modulationDACDefault (D5h).
Set
ModLUTdisab to ‘0’to enable the modulation current vs. temperature look-up table (LUT) in the
PHY1070-01. The 45 byte LUT is indexed by the value in temperatureADC (FEh), where Index is given
by:
Index = (temperatureADC x 45) / 255
and the index rounds down to the lower temperature. When the LUT is switched from the enabled to
disabled state, the last control value from the LUT will persist. On disabling the LUT the modulation DAC
will not revert back to a value previously written to
modulationDACDefault. A new value must be explicitly written to modulationDACDefault once the LUT has been disabled.
On power up the modulation DAC will not be programmed with the value uploaded from the EEPROM
and will default to taking the value from the LUT for the measured temperature.
4.3.3. VCSEL Driver Setup
There is a trimming network on the output driver which adjusts the time constant for output damping on
VCSEL ± . It is controlled by the value in
txDriverCap (F6h) which is used to select between 1 and 8 capacitors connected to the VCSEL± outputs as shown in figure 17. All capacitors are ~0.09pF. Set
txDriverCap to '00h' for no damping and fastest edges; set to ‘FFh’ for full damping and slowest edges. CCCC
VCSEL +/-From modulation driver
Bit 4Bit 3Bit 2Bit 1Bit 0C
Bit 7Bit 6Bit 5
Figure 17 -Time constant selection for the Tx output damping network.
4.4. VCSEL Safety Features
The VCSEL safety circuitry monitors the device for potential faults. If a fault is detected, the safety logic
turns off the transmitter bias and modulation currents and indicates the fault condition at pin TX_FAULT.
The VCSEL output driver can be disabled in one of four ways:
1. The TX_DISABLE pin is taken high.
2. The internal safety critical shutdown circuitry detects a fault with
a. the APC loop or bias current
b. power supply 2.7V>VDD or VDD>3.9V
c. RREF shorted to Ground, VDD or open circuit
3. The Soft Tx Disable bit in STAT_CON is asserted
4. The watchdog timer times out, indicating that communication with the host/MCU has been
interrupted.
In all cases the modulation current and the current to the VCSEL_BIAS pin will be disabled, and the
SHUTDOWN pin will be asserted. The purpose of the SHUTDOWN pin is to provide a means by which the
VCSEL can be isolated from ground (common cathode configuration) when an electrical fault is detected.
In cases 2 and 4, TX_FAULT will also be set.
Safety critical
shutdown circuitDFh
bit 6Hardware_ignore
txControl0
E1h
bit 7HostSFTtxfault
txControl2
6Eh
bit 2TX Fault
STAT_CON
6Eh
bit 6Soft Tx Disable
STAT_CON
E0h
bit 3SDpolarity
txControl1
Controller
SHUTDOWN
TX_FAULT
shutDownPassword7Ah
VCSEL_BIAS
VDD
FET
eg. short
circuit
bit 7Tx Disable State
GND
Figure 18 - TX_FAULT and SHUTDOWN pin control logic
4.4.1. PHY1070-01 Fault Management
The safety critical shutdown circuit will shutdown and isolate the VCSEL if it senses a fault with the bias
current, the supply voltage or the reference voltage.
For example, consider a VCSEL arranged in common cathode configuration. The VCSEL anode connects
to the VCSEL_BIAS pin and the cathode connects to ground. If a short circuit to VDD occurs on the route
between the anode and VCSEL_BIAS then the safety critical shutdown circuit will switch off the bias
current. However, this will not protect the laser as a current path from VDD to ground still exists. A FET
device can provide the required isolation when switched off by the SHUTDOWN pin as shown in figure 18.
The SHUTDOWN pin is controlled by the same signal which switches off the bias current. The
SHUTDOWN pin output response to faults and polarity setting is shown in table 5.
In common anode configuration the polarity of the SHUTDOWN pin needs to be reversed. The polarity of
the shutdown pin is controlled by SDpolarity.
The safety critical shutdown circuit can be disabled in software by setting Hardware_ignore = ‘1’, and
entering the value 42h to the shutDownPassword register. In this case the VCSEL will not be disabled
when a fault is detected; however, a TX_FAULT will still be reported. This feature should be used with
great caution as the eye safety features of the device will be disabled. The PHY1070-01 will respond to
TX_DISABLE being set even if Hardware_ignore is set.
Power supply and VREF faults result in the TX_FAULT latching and the laser being disabled momentarily.
Once the fault condition is removed the laser will be reactivated, however the TX_FAULT output must be
after a fault, there will be a short period during which the bias control loop is allowed to settle (t_settle, see
Section 3.4.3) before the safety control loop circuit is enabled.
Fault Status SDpolarity
(TxControl2, Bit 3)
SHUTDOWN
Pin Voltage No Fault 0 High Low
Fault 0 Low High
Table 5 – Shutdown Output Voltage under Fault/No Fault conditions
4.4.2. MCU and Host Fault Management
The MCU is responsible for maintaining and reporting alarms and warnings in accordance with the SFF-
8472 specification. When an alarm is triggered, the MCU must set HostSFTtxfault = ‘1’. This will cause
the PHY1070-01 to report a fault on the TX_FAULT pin and in the STAT_CON register. The PHY1070-01
will not disable the VCSEL at this point. The MCU or the host could disable the VCSEL when a TX Fault is
detected in STAT_CON by asserting Soft Tx Disable.
4.4.3. Watchdog
A watchdog is implemented by the PHY1070-01 to monitor the activity of the attached MCU in digital
diagnostics mode. When WatchdogEn (E1h
txControl2 bit0) is set to ‘1’, the PHY1070-01’s watchdog
feature is enabled. The MCU is required to increment the Watchdog[0:5] counter (E1h txControl2) at
least every 100ms. If no change is detected in the counter, the PHY1070-01 will disable the VCSEL and
will assert TX_FAULT. The VCSEL will be re-enabled, and TX_FAULT de-asserted when either the
watchdog counter is incremented, or the watchdog feature is disabled by writing ‘0’ to WatchdogEn. On
power up the watchdog feature is disabled.
4.5. Tsense Temperature Sensor
The temperature is determined by measuring the ∆VBE across an external transistor connected to the
TSENSE pin. The transistor can be any standard npn silicon transistor with a beta > 100 connected in
diode mode (base and collector tied together). Phyworks recommends using a BC847 or similar.
Calibration including averaging of the temperature sensor output is required to meet accuracy
requirements. Calibrating over temperature the PHY1070-01 can report temperature to within ±2°C over
the recommended operating conditions.
The temperature sensor operating range and corresponding TSENSE input levels are shown in Table 6.
Symbol Unit Minimum Maximum
Temperature t °C -70 +115
TSENSE differential input voltage BEΔV mV 50 100
Table 6 – Temperature sensor operating range
TSENSE
Temperature
ADC
Signal
Conditioning
Switching Current
Generator
i10uAi200uABE
Figure 19 – Temperature sensor functional block diagram
5. Control Interface The PHY1070-01 can be operated in one of two modes as dictated by the design of the module. The
PHY1070-01 will identify the mode by attempting to read from its 2-Wire serial EEPROM interface (See
section 5.4) on power up. If no EEPROM is present then diagnostic mode is inferred.
In digital diagnostics mode, the Micro Controller Unit (MCU) and EEPROM (Address A0h) present an
SFF-8472 compliant interface to the host. The MCU provides read/write access to all registers in the A2h
registers map, calculates digital diagnostics monitor values and maintains alarms and warnings. The MCU
must initialise the PHY1070-01 control registers from EEPROM, relay control information to the PHY1070-
01, and fetch status information in real time.
In stand-alone mode, the PHY1070-01 is initialised directly from an external 4 kbit (8 x 512 bit) Serial
EEPROM. Serial ID information as specified in the SFP MSA is accessible via the two wire interface. This
mode supports temperature compensation of modulation current using a look-up table stored in EEPROM.
Figure 20 - Optical transceiver module configurations
5.1. Memory Map
Figure 21 - Memory map for a 4G SFP or SFF transceiver module containing a PHY1070-01 device
Figure 21 shows the memory map of a module containing a PHY1070-01. An 8 kbit memory space is a
natural step up from the minimum 4 kbit memory space required for SFF-8472 compliance, providing
additional space in which to map the Device Settings registers of the PHY1070-01.
The internal RAM of the PHY1070-01 implements the SFF-8472 Diagnostics table and the Device
Settings table. Selection between tables is achieved using the tableSelect (tabsel) register located at
SFF-8472 Serial ID Serial ID (96)
Vendor specific (32)
SFF-8472 Reserved (128)
A0h
SFF-8472 Diagnostics SFP MSA Diag (120)
Vendor specific (7)
PHY1070-01
Expansion
EEPROM Undefined (127)
PHY1070-01
Expansion
EEPROM Undefined (127)
SFF-8472 U. EEPROM User EEPROM (120)
Vendor specific (8)
PHY1070-01
Expansion
EEPROM Undefined (128)
A2h tabsel = 00h or 01h
Device Settings (128)
tabsel
tabsel
tabsel
7Fh
A2h tabsel = 02h
A2h tabsel = 03h
MCU
A2h
EEPROM
PHY1070-01
ROSA
TOSA A0h
EEPROM
TWI
PHY1070-01
ROSA
TOSA
A0h +
A2h
EEPROM
TWI
Digital diagnostic mode Stand alone mode
Tabsel is effectively write-only because to write to tabsel has the effect of switching to a different register
table. Thus, reading tabsel will not yield the value which was previously written.
5.2. Operation
Figure 22 - Serial interfaces to RAM and the on-chip controller
5.2.1. Data Transfer Mechanisms
Three distinct data paths are identified in Figure 22.
When the PHY1070-01 comes out of reset, the 2-wire serial slave interface is disabled. Only path 1 is
active. The controller instructs the 2-wire serial master interface to attempt to transfer A2h register tables
(SFF-8472 diagnostics and device settings) from the external EEPROM to RAM. If this is successful then
the PHY1070-01 will operate in stand-alone mode. If the transfer fails, then the dsfail and eerxfail alarm
bits in the alarmBytePHY1070 (78h) register will be set and the PHY1070-01 will operate in diagnostics
mode. Regardless of the outcome, when the EEPROM read process is complete the controller enables
the 2-wire serial slave interface. The 2-wire serial master interface is then no longer used.
The 2-wire serial slave interface has slave address A2h. In diagnostics mode, the host or external MCU
uses the 2-wire serial slave interface to write to or read from copies of the device settings held in RAM.
When the boot sequence is complete, the controller transfers data between the RAM and the actual
registers implemented in hardware periodically every 10ms.
In stand-alone mode the RAM space is not used once the boot sequence is complete. Reading from A2h
will return zero.
Path 3 is a special case which supports modules designed for stand-alone mode, enabling them to be set
up or re-configured via the 2-wire serial interface slave. The PHY1070-01 can be forced into diagnostic
mode if the data integrity numbers in the EEPROM are deliberately erased (see section 5.4.2). This
enables the host/MCU to access both the RAM (path 2) and the EEPROM (path 3). All accesses to the
A0h address space are directed to the EEPROM only. Accesses to the A2h address space are examined
as they arrive by the 2-wire serial slave module, which in turn instructs the arbitration logic. The
destination for the transaction depends on the value of tabsel and the register address as shown in Table
7.
SCL
RESET
2-wire serial interface
slave
EEPROM
SA_SDA
2-wire serial interface
master
RAM
Controller
Hardware registers
STAT_CON6Eh
Host or
MCU
SDA
SA_SCL
arbiter
alarmBytePHY107078h
testControl79h
modulationDACDefaultD5h
txPowerDownD6h
rxPowerDownDBh
txControlDFh-E1h
diagnosticsSelectE7h
E8h-E9hrxControl
F1h-F4hDACs
F5hrateSel
F6htxDriverCap
FBh-FFhADCs
7FhtableSelect
Access
type
tabsel Address
range1 Destination
memory read 00 lower RAM
read 03 upper RAM
write 00 lower RAM + EEPROM
write 00 upper EEPROM
write 03 upper RAM
1 Addresses 00h to 7Fh = lower. Addresses 80h to FFh = upper.
Table 7 - Destination of 2-wire serial interface transactions as a function of tabsel and address.
5.2.2. Device Initialisation Sequence
The Initialisation Sequence is illustrated in Figure 23. The Data_Ready_Bar bit in the STAT_CON register
indicates when data from the ADCs may be read after power up. It is first set to ‘1’ before the 2-wire serial
slave interface is enabled to indicate that the PHY1070-01 is not ready. Once initialisation is complete and
the ADC data is ready
Data_Ready_Bar is cleared to ‘0’. This event can be used by the external
host/MCU as a signal that the PHY1070-01 is ready for device settings to be uploaded from the MCU to
the PHY1070-01 RAM. The PHY1070-01 will not enter the main diagnostic function loop until the upload is
complete. This is initiated by the host/MCU clearing the dsfail and eerxfail bits in the alarmBytePHY1070
(78h) register. When
dsfail is cleared and the main loop is executed the contents of RAM will be
transferred into the hardware registers of the PHY1070-01.
