PMK50XP ,P-channel TrenchMOS extremely low level FETGeneral descriptionExtremely low level P-channel enhancement mode Field-Effect Transistor (FET) in ..
PMK50XP ,P-channel TrenchMOS extremely low level FETPMK50XPP-channel TrenchMOS extremely low level FETRev. 02 — 28 April 2010 Product data sheet1. Prod ..
PMK50XP ,P-channel TrenchMOS extremely low level FETApplications Battery management Load switching1.4 Quick reference data Table 1. Quick reference d ..
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PMK50XP
P-channel TrenchMOS extremely low level FET
PMK50XP
P-channel TrenchMOS extremely low level FET
Rev. 02 — 28 April 2010 Product data sheet Product profile
1.1 General descriptionExtremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits Low conduction losses due to low
on-state resistance
1.3 Applications Battery management Load switching
1.4 Quick reference data Table 1. Quick reference dataVDS drain-source
voltage°C≤Tj≤ 150°C - - -20 V drain current Tsp =25°C; VGS =-4.5V;
see Figure 1; see Figure 3
---7.9 A
Ptot total power
dissipation
Tsp =25°C; see Figure 2 --5 W
Static characteristicsRDSon drain-source
on-state
resistance
VGS =-4.5V; ID =-2.8A; =25°C; see Figure 9;
see Figure 10 4050mΩ
Dynamic characteristicsQGD gate-drain charge VGS =-4.5V; ID =-4.7A;
VDS= -10 V; see Figure 11;
see Figure 12
-1.3 -nC
NXP Semiconductors PMK50XP
P-channel TrenchMOS extremely low level FET Pinning information Ordering information
Table 2. Pinning information source
SOT96-1 (SO8) source source G gate D drain D drain D drain D drain
Table 3. Ordering informationPMK50XP SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
NXP Semiconductors PMK50XP
P-channel TrenchMOS extremely low level FET Limiting values
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage 25°C≤Tj≤ 150°C ---20 V
VDGR drain-gate voltage 25°C≤Tj≤ 150 °C; RGS =20kΩ ---20 V
VGS gate-source voltage -12 - 12 V drain current Tsp =25 °C; VGS =-4.5V;
see Figure 1; see Figure 3
---7.9 A
Tsp= 100 °C; VGS =-4.5V;
see Figure 1
---5 A
IDM peak drain current Tsp =25 °C; tp≤10 µs; pulsed;
see Figure 3
---31.6 A
Ptot total power dissipation Tsp =25 °C; see Figure 2 --5 W
Tstg storage temperature -55 - 150 °C junction temperature -55 - 150 °C
Source-drain diode source current Tsp=25°C ---4.1 A
ISM peak source current Tsp =25 °C; tp≤10 µs; pulsed - - -16.4 A
NXP Semiconductors PMK50XP
P-channel TrenchMOS extremely low level FET Thermal characteristics
Table 5. Thermal characteristicsRth(j-sp) thermal resistance
from junction to solder
point
see Figure 4 --25 K/W
NXP Semiconductors PMK50XP
P-channel TrenchMOS extremely low level FET Characteristics
Table 6. Characteristics
Static characteristicsV(BR)DSS drain-source
breakdown voltage =-250µA; VGS =0V; Tj= -55°C -18 --V =-250µA; VGS =0V; Tj=25°C -20 --V
VGS(th) gate-source threshold
voltage =-250µA; VDS =VGS; Tj =-55 °C;
see Figure 7; see Figure 8
---1.1 V =-250µA; VDS =VGS; Tj= 150 °C;
see Figure 7; see Figure 8
-0.35 --V =-250µA; VDS =VGS; Tj =25°C;
see Figure 7; see Figure 8
-0.55 -0.75 -0.95 V
IDSS drain leakage current VDS =-20 V; VGS =0V; Tj=25°C ---1 µA
VDS =-20 V; VGS =0V; Tj=70°C ---5 µA
IGSS gate leakage current VGS =12V; VDS =0V; Tj=25°C - -10 -100 nA
VGS =-12 V; VDS =0V; Tj=25°C - -10 -100 nA
RDSon drain-source on-state
resistance
VGS =-2.5V; ID =-2.3A; Tj =25°C;
see Figure 9; see Figure 10 5670mΩ
VGS =-4.5V; ID =-2.8A; Tj= 150 °C;
see Figure 9; see Figure 10 6480mΩ
VGS =-4.5V; ID =-2.8A; Tj =25°C;
see Figure 9; see Figure 10 4050mΩ
Dynamic characteristicsQG(tot) total gate charge ID =-4.7A; VDS =-10 V; VGS =-4.5V;
see Figure 11; see Figure 12
-10 - nC
QGS gate-source charge - 2.2 - nC
QGD gate-drain charge - 1.3 - nC
VGS(pl) gate-source plateau
voltage =-4.7A; VDS= -10 V; see Figure 11;
see Figure 12
--1.6 - V
Ciss input capacitance VDS =-20 V; VGS=0 V; f=1 MHz; =25°C; see Figure 13 1020 - pF
Coss output capacitance - 140 - pF
Crss reverse transfer
capacitance 100 - pF
td(on) turn-on delay time VDS =-10 V; RL =10 Ω; VGS =-4.5V;
RG(ext) =6Ω
-8.5 -ns rise time - 7.5 - ns
td(off) turn-off delay time - 82 - ns fall time - 35 - ns
Source-drain diodeVSD source-drain voltage IS =-1.7A; VGS =0V; Tj =25°C;
see Figure 14 -0.77 -1.2 V
NXP Semiconductors PMK50XP
P-channel TrenchMOS extremely low level FET
NXP Semiconductors PMK50XP
P-channel TrenchMOS extremely low level FET
