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PMN50XPNXPN/a33000avaiP-channel TrenchMOS extremely low level FET


PMN50XP ,P-channel TrenchMOS extremely low level FETApplications „ Battery management„ Battery powered portable equipment„ Load Switching„ Low power DC ..
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PMN50XP
P-channel TrenchMOS extremely low level FET
Product profile1.1 General description
Extremely low level P-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package. This product is designed and qualified for use in computing,
communications, consumer and industrial applications only.
1.2 Features

1.3 Applications

1.4 Quick reference data

PMN50XP
P-channel TrenchMOS extremely low level FET
Rev. 02 — 2 October 2007 Product data sheet
Low on-state losses „ Low threshold voltage Battery management „ Battery powered portable equipment Load Switching „ Low power DC to DC converters
Table 1. Quick reference

VDS drain-source voltage Tj≥25 °C; Tj≤ 150°C ---20 V drain current VGS =-4.5 V; Tsp =25 °C;
see Figure 1 and 3
---4.8 A
Dynamic characteristics

QGD gate-drain charge VGS =-4.5 V; ID =-4.7A;
VDS =-10 V; Tj =25 °C;
see Figure 9 and 10
-1.3 -nC
Static characteristics

RDSon drain-source on-state
resistance
VGS =-4.5 V; ID =-2.8A; =25 °C; see Figure 7 and 8 4860mΩ
NXP Semiconductors PMN50XP
P-channel TrenchMOS extremely low level FET Pinning information
Ordering information Limiting values
Table 2. Pinning
D drain D drain G gate S source D drain D drain
Table 3. Ordering information

PMN50XP TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage Tj≥25 °C; Tj≤ 150 °C- -20 V
VDGR drain-gate voltage Tj≥25 °C; Tj≤ 150 °C; RGS =20kΩ --20 V
VGS gate-source voltage -12 12 V drain current Tsp =25 °C; VGS =-4.5V; see Figure 1 and 3 --4.8 A
Tsp =100 °C; VGS =-4.5V - -3 A
IDM peak drain current Tsp =25 °C; tp <10 μs; pulsed; see Figure3 - -19.4 A
Ptot total power dissipation Tsp =25 °C; see Figure2 -2.2 W
Tstg storage temperature -55 150 °C junction temperature -55 150 °C
Source-drain diode
source current Tsp =25 °C- -1.9 A
ISM peak source current Tsp =25 °C; tp≤10 μs; pulsed - -7.5 A
NXP Semiconductors PMN50XP
P-channel TrenchMOS extremely low level FET
NXP Semiconductors PMN50XP
P-channel TrenchMOS extremely low level FET Thermal characteristics
Characteristics
Table 5. Thermal characteristics

Rth(j-sp) thermal resistance
from junction to solder
point
see Figure4 -- 55 K/W
Table 6. Characteristics
Static characteristics

V(BR)DSS drain-source
breakdown voltage =-250 μA; VGS =0V; =25°C
-20 - - V =-250 μA; VGS =0V; =-55°C
-18 - - V
VGS(th) gate-source threshold
voltage= -0.25 mA; VDS = VGS; =25 °C; see Figure 5 and 6
-0.55 -0.75 -0.95 V= -0.25 mA; VDS = VGS; = 150 °C; see Figure 5 and 6
-0.35 - - V= -0.25 mA; VDS = VGS; =-55 °C; see Figure 5 and 6 -1.1 V
IDSS drain leakage current VDS =-20 V; VGS =0V; =25°C -1 μA
VDS =-20 V; VGS =0V; =70°C -5 μA
NXP Semiconductors PMN50XP
P-channel TrenchMOS extremely low level FET

IGSS gate leakage current VGS≤12 V; VDS =0V; Tj =25 °C- -10 -100 nA
VGS≥12 V; VDS =0V; Tj =25 °C- -10 -100 nA
RDSon drain-source on-state
resistance
VGS =-4.5V; ID =-2.8A; =25 °C; see Figure 7 and 8
-48 60 mΩ
VGS =-4.5V; ID =-2.8A; = 150 °C; see Figure 7 and 8
-77 96 mΩ
VGS =-2.5V; ID =-2.3A; =25 °C; see Figure 7 and 8
-65 80 mΩ
Dynamic characteristics

QG(tot) total gate charge ID =-4.7A; VDS =-10V;
VGS =-4.5V; Tj =25 °C;
see Figure 9 and 10
-10 - nC
QGS gate-source charge ID =-4.7A; VDS =-10V;
VGS =-4.5V; Tj =25 °C;
see Figure 9 and 10
-2.2 -nC
QGD gate-drain charge ID =-4.7A; VDS =-10V;
VGS =-4.5V; Tj =25 °C;
see Figure 9 and 10
-1.3 -nC
Ciss input capacitance VDS =-20 V; VGS =0V;
f=1MHz; Tj =25 °C;
see Figure11
-1020 - pF
Coss output capacitance VGS =0V; VDS =-20V;
f=1MHz; Tj =25 °C;
see Figure11
-140 -pF
Crss reverse transfer
capacitance
VDS =-20 V; VGS =0V;
f=1MHz; Tj =25 °C;
see Figure11
-100 -pF
td(on) turn-on delay time RG(ext) =6 Ω; RL =10Ω;
VDS =-10 V; VGS =-4.5V; =25°C
-8.5 -ns rise time RG(ext) =6 Ω; RL =10Ω;
VDS =-10 V; VGS =-4.5V; =25°C
-7.5 -ns
td(off) turn-off delay time VDS =-10 V; RL =10Ω;
VGS =-4.5V; RG(ext) =6Ω; =25°C
-82 - ns fall time RG(ext) =6 Ω; RL =6Ω;
VDS =-10 V; VGS =-4.5V; =25°C
-35 - ns
VGS(pl) gate-source plateau
voltage
VDS =-10 V; ID =-4.7A; =25 °C; see Figure 9 and 10
--1.6 - V
Source-drain diode

VSD source-drain voltage IS =-1.7A; VGS =0V; Tj =25 °C- -0.77 -1.2 V
trr reverse recovery time IS= 3.5 A; dIS/dt= -100 A/μs;
VGS =0V; VDS =20V; Tj =25°C -ns
Table 6. Characteristics …continued
NXP Semiconductors PMN50XP
P-channel TrenchMOS extremely low level FET
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