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SICOFI-2 TE Two Channel Codec Filter ...
ICs for Communications
Two/Four Channel Codec Filter for Terminal Applications
SICOFI®-2/4-TE
PSB2132 Version 1.4
PSB2134 Version 1.4
Delta Sheet1998-04-01
Edition 1998-04-01
Published by Siemens AG,
HL SP,
Balanstraße 73,
81541 München© Siemens AG 1998.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
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Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
Two/Four Channel Codec Filter for
Terminal Applications
SICOFI®-2/4-TE
PSB2132
PSB2134Interrupt HandlingIf all the inputs assigned to channel-pair-1,2 (or 3,4) have been stable for two samples
(i.e. for at least the debounce time), an interrupt on INT12 (or INT34) is generated. The
status information will be read into the XR-registers with the rising edge of INT12 (or
INT34). The status information of the assigned channel-pair-1,2 (or 3,4) will be updated
after the next interrupt INT12 (or INT34) has occurred. The interrupt INT12 (or INT34) of
assigned channel-pair-1,2 (or 3,4) is cleared, if the registers XR0-XR3 are read via a
XOP command.The signaling inputs (SIx_x and SBx_x, if programmed as inputs) are sampled after
the debounce time (refer to XR4)INT12 is assigned to and affected by the signaling inputs of channel-pair-1,2INT34 is assigned to and affected by the signaling inputs of channel-pair-3,4
PSB2132
PSB2134
Interrupt Handling
Figure 1
Example for Channel-pair-1,2If one or more of the signaling input pins for channel-pair-1,2 (input pins and
bi-directional pins programmed as inputs) change, and all these signaling inputs for
channel-pair-1,2 are stable for at least the debounce time specified in Register XR4
INT12 will go from ‘0’ to ‘1’.
The assigned interrupt INT12 is cleared if the appropriate registers (XR0, XR1, XR2 and
XR3, read with command XOP := 3BH) are read via the serial μC-interface.
Note:Pin INT34 provides the same functionality for channel-pair-3,4. Changes at the
signaling inputs assigned to channel-pair-3,4 do not affect INT12 and vice versa!
PSB2132
PSB2134
Interrupt Handling
The following example shows the interrupt functionality of channel-pair-1,2,
SBx_x are programmed as outputs:
Figure 2
Example, Status Information in XR-Registers for Both Channel-pairs 1,2 and 3,4The status information of the appropriate channel-pair-1,2 (or 3,4) will be read into the
XR-registers with the rising edge of INT12 (or INT34) and remains valid until the next
rising edge of INT12 (or INT34) updates the status information.
The assigned interrupt INT12 is cleared if the appropriate registers (XR0, XR1, XR2 and
XR3, read with command XOP := 3BH) are read via the serial μC-interface.
ITD10546
After XOP READ-Command, INT12 is cleared !
(read XR3, XR2, XR1, XR0 within the Interrupt-Handler)
SI1_0
ChangeChange
ChangeChangeChange
StableChangeChangeChangeChange
StableChangeSamples
SI1_1
SI2_0
SI2_1
INT12
Debounce Time,
Adjusted in XR4
PSB2132
PSB2134
Interrupt Handling
Figure 3
