PTN3311D ,High-speed serial logic translatorsGENERAL DESCRIPTIONThe High-Speed Serial Logic Translator provides a point solutionthat addresses t ..
PTN3311D ,High-speed serial logic translatorsINTEGRATED CIRCUITSPTN3310/PTN3311High-speed serial logic translatorsProduct data2001 Jun 19
PTN3310-PTN3310D-PTN3311D
High-speed serial logic translators
Product data
2001 Jun 19
Philips Semiconductors Product data
PTN3310/PTN3311High-speed serial logic translators
FEATURES Meets LVDS EIA-644 and PECL standards 2 pin-for-pin replacement input/output choices:
LVDS in, PECL out (PTN3310)
PECL in, LVDS out (PTN3311) Single +3.3 V supply voltage operation Available in 8-pin SO package Maximum throughput data rate of 800 Mbps typical
APPLICATIONS High-speed networking and telecom applications
ATM
SONET/SDH
Switches
Routers
Add-drop multiplexers
GENERAL DESCRIPTIONThe High-Speed Serial Logic Translator provides a point solution
that addresses the various interface logic requirements of Optical
Transceiver Modules. The product offers a compact translation
between LVDS and PECL high speed serial data lines. This provides
the end users a simple way to mix or match Optical Transceiver ICs
from various vendors to maximize desired performance and reduces
the need to redesign interfaces to accommodate new Optical
Transceiver ICs.
The High-Speed Serial Logic Translator comes in two translation
choices to allow mixing LVDS and PECL input/outputs. The product
is offered in a small, convenient, 8-pin package.
Figure 1 shows the High-Speed Serial Logic Translator Device in a
typical high speed optical module application. Figure 2 shows the
circuit block diagrams.
PIN CONFIGURATIONS
PIN DESCRIPTIONS
8-pin SO package
ORDERING INFORMATION
Philips Semiconductors Product data
PTN3310/PTN3311High-speed serial logic translators
Figure 1. High-Speed Serial Logic Translators in Optical Module Application
Figure 2. High-Speed Serial Logic Translator Block Diagrams
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product data
PTN3310/PTN3311High-speed serial logic translators
DC ELECTRICAL CHARACTERISTICS
NOTES: These values are for VCC = 3.3 V; PECL level specifications are referenced to VCC and will track 1:1 with variation of VCC. Power supply either on or off.
Philips Semiconductors Product data
PTN3310/PTN3311High-speed serial logic translators
AC ELECTRICAL CHARACTERISTICS
LVDS REFERENCE MEASUREMENT CONFIGURATIONThe above diagram shows the test set-up used when evaluating
LVDS outputs. According to the TIA-EIA-644 Standard, the
maximum lumped capacitance test load should be 5 pF. However,
by using probes or cables to observe the signal, additional
capacitance is added, which has an effect on the rise and fall times.
Cprobe represents any capacitance caused by the use of probes or
cables. Assuming balanced loading and balanced output drivers, the
total effective capacitance seen by the part is:
CEff = CLVDS + 1 /2 Cprobe
To correctly account for the effects of Cprobe, the following formula
should be used:�
5pF
CEff �t measured,
Where Δt is the 20%–80% rise/fall time.
To avoid the use of additional calculation of the measured results, a
different approach could be taken; however, the value of Cprobe has
to be known in advance. In that case, the value of CLVDS can be
chosen such that the sum of the capacitances equals 5 pF, i.e.:
CLVDS + 1 /2 Cprobe = 5 pF
Philips Semiconductors Product data
PTN3310/PTN3311High-speed serial logic translators
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
