SCAN18245TSSC ,Non-Inverting Transceiver with 3-STATE OutputsFunctional DescriptionThe SCAN18245 consists of two sets of nine non-inverting HIGH enables data fr ..
SCAN18245TSSC ,Non-Inverting Transceiver with 3-STATE Outputsapplications1149.1 Standard Test Access Port and Boundary ScanArchitecture with the incorporation o ..
SCAN18245TSSCX ,Non-Inverting Transceiver with 3-STATE OutputsFeaturesThe SCAN18245T is a high speed, low-power bidirectional
SCAN18245TSSC-SCAN18245TSSCX
Non-Inverting Transceiver with 3-STATE Outputs
SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs October 1991 Revised May 2000 SCAN18245T Non-Inverting Transceiver with 3-STATE Outputs General Description Features The SCAN18245T is a high speed, low-power bidirectionalIEEE 1149.1 (JTAG) Compliant line driver featuring separate data inputs organized intoDual output enable control signals dual 9-bit bytes with byte-oriented output enable and direc- 3-STATE outputs for bus-oriented applications tion control signals. This device is compliant with IEEE 9-bit data busses for parity applications 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-Reduced-swing outputs source 32 mA/sink 64 mA scan test logic and test access port consisting of Test DataGuaranteed to drive 50Ω transmission line to TTL input Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), levels of 0.8V and 2.0V and Test Clock (TCK). TTL compatible inputs 25 mil pitch SSOP (Shrink Small Outline Package) Includes CLAMP and HIGHZ instructions Member of Fairchild’s SCAN Products Ordering Code: Order Number Package Number Package Description SCAN18245TSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description A1 Side A1 Inputs or 3-STATE Outputs (0–8) B1 Side B1 Inputs or 3-STATE Outputs (0–8) A2 Side A2 Inputs or 3-STATE Outputs (0–8) B2 Side B2 Inputs or 3-STATE Outputs (0–8) G1, G2 Output Enable Pins DIR1, DIR2 Direction of Data Flow Pins © 2000 DS010961
