SN54LS490J ,DUAL DECADE COUNTER
SN54LS490J ,DUAL DECADE COUNTER
SN54LS49J ,BCD-to-Seven-Segment Decoders/Drivers with Open Collector Outputs
SN54LS49J. ,BCD-to-Seven-Segment Decoders/Drivers with Open Collector Outputs
SN54LS540J ,OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS0 TState Outputsprive Bus Lines or SN54LSS40, SN54L8541 . . . J OR w PACKAGEBuffer Memory Address R ..
SN54LS541J ,Octal buffer/line driver with 3-state outputs0 TState Outputsprive Bus Lines or SN54LSS40, SN54L8541 . . . J OR w PACKAGEBuffer Memory Address R ..
SN74HC126PWR ,Quadruple Bus Buffer Gates With 3-State Outputs SCLS103E − MARCH 1984 − REVISED JULY 200 ..
SN74HC126PWT ,Quadruple Bus Buffer Gates With 3-State Outputslogic diagram (positive logic)1 101OE 3OE2 3 9 81A 1Y 3A 3Y4 132OE 4OE5 6 12 112A 2Y 4A 4YPin numbe ..
SN74HC132 ,Quadruple Positive-NAND Gates With Schmitt-Trigger InputsFeatures... 18.4 Device Functional Modes...... 82 Applications..... 19 Application and Implementati ..
SN74HC132D ,Quadruple Positive-NAND Gates With Schmitt-Trigger InputsFeatures 3 DescriptionThe SNx4HC132 device functions as a NAND gate,1• Wide Operating Voltage Range ..
SN74HC132DBR ,Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs SCLS034G–DECEMBER 1982–REVISED JUNE 20165 Pin Configuration and FunctionsD, DB, N, NS, J, W, or PW ..
SN74HC132DR ,Quadruple Positive-NAND Gates With Schmitt-Trigger InputsLogic Diagram (Positive Logic)AYB1An IMPORTANT NOTICE at the end of this data sheet addresses avail ..
SN54LS490J
BCD-to-Seven Segment Decoder Driver(with Open collector outputs)
LOGIC DIAGRAM (ONE HALF SHOWN) -- - - - - - - - -
TRUTH TABLE
DUAL DECADE COUNTERThe SN54/74LS490 contains a pair of high-speed 4-stage ripple counters.
Each half of the SN54/74LS490 has individual Clock, Master Reset and Mas-
ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code. Dual Version of SN54/74LS490 Individual Asynchronous Clear and Preset to 9 for Each Counter Count Frequency — Typically 65 MHz Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)------- -- ---- ----- ---- -- -- -
PIN NAMES LOADING (Note a) Master Set (Set to 9) Input Master Reset Clock Input (Active LOW Going Edge)
Q0–Q3 Counter Outputs (Note b)
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
