SN74FB2031 ,9-Bit TTL/BTL Address/Data Transceiver SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001* Co ..
SN74FB2032RC ,9-BIT TTL/BTL COMPETITION TRANSCEIVER
SN74FB2033ARC ,8-Bit TTL/BTL Registered Transceiver SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 ..
SN74FB2033ARCR ,8-Bit TTL/BTL Registered Transceiver/sc/package.2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANS ..
SN74FB2033KRC ,8-Bit TTL/BTL Registered Transceiver
SN74FB2041ARC ,7-Bit TTL/BTL Transceivers
SN75188 ,Quadruple Line Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V at (o ..
SN75188D ,Quadruple Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75188DR ,Quadruple Line Driver SLLS094C − SEPTEMBER 1983 − REVISED MAY 2004SN55188 ... ..
SN75188DRG4 ,Quadruple Line Driver 14-SOIC 0 to 70maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75188N ,Quadruple Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN75188N. ,Quadruple Line Drivermaximum ratings over operating free-air temperature (unless otherwise noted)Supply voltage, V at (o ..
SN74FB2031
9-Bit TTL/BTL Address/Data Transceiver
100 mA High-Impedance State During Power Up
and Power Down TTL-Input Structures Incorporate Active
Clamping to Aid in Line TerminationGNDA1 OEBTCK
SEL1
LCB LCA
BG GND
SEL0
TDO
GNDA9
GNDB1V
RC PACKAGE
(TOP VIEW)BG V
TMS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BIAS V
OEA V
OEB
TDI
descriptionThe SN74FB2031 is a 9-bit transceiver designed to translate signals between TTL and backplane transceiver
logic (BTL) environments. The device is designed specifically to be compatible with IEEE Std 1194.1-1991.
The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC is less than 2.1 V,
the B port is turned off.
The A port operates at TTL signal levels. The A outputs reflect the inverse of the data at the B port when the
A-port output enable (OEA) is high. When OEA is low or VCC is less than 2.1 V, the A outputs are in the
high-impedance state.
Pins are allocated for the four-wire IEEE Std 1149.1 (JTAG) test bus, although currently there are no plans to
release a JTAG-featured version. TMS and TCK are not connected and TDI is shorted to TDO.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
