ST70135 Fast Delivery |IC PHOENIX CO.,LIMITED

ST70135 ,ASCOTTM DMT TRANSCEIVERGENERAL DESCRIPTIONINTERLEAVEDThe ST70135A is the DMT modem and ATMframer of the STMicroelectronics ..
ST70135A ,ASCOT DMT TRANSCEIVERGENERAL DESCRIPTIONINTERLEAVEDThe ST70135A is the DMT modem and ATMframerof the STMicroelectronics ..
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ST70135
ASCOTTM DMT TRANSCEIVER
1/29April 2000 DMT MODEM FOR CPE ADSL,
COMPATIBLE WITH THE FOLLOWING
STANDARDS: ANSI T1.413 ISSUE2 ITU-T G.992.1 (G.DMT) ITU-T G.992.2 (G.LITE) SUPPORTS EITHER ATM (UTOPIA LEVEL&2) OR BITSTREAM INTERFACE 16 BIT MULTIPLEXED MICROPROCESSOR
INTERFACE (LITTLE AND BIG ENDIAN
COMPATIBILITY) ANALOG FRONT END MANAGEMENT DUAL LATENCY PATHS: FAST AND
INTERLEAVED ATM’S PHY LAYER: CELL PROCESSING
(CELL DELINEATION, CELL INSERTION,
HEC) ADSL’S OVERHEAD MANAGEMENT REED SOLOMON ENCODE/DECODE TRELLIS ENCODE/DECODE (VITERBI) DMT MAPPING/ DEMAPPING OVER 256
CARRIERS FINE (2PPM) TIMING RECOVER USING
ROTOR AND ADAPTATIVE FREQUENCY
DOMAIN EQUALIZING TIME DOMAIN EQUALIZATION FRONT END DIGITAL FILTERS 0.35μm HCMOS6 TECHNOLOGY 144 PIN PQFP PACKAGE POWER CONSUMPTION1 WATT AT 3.3V
APPLICATIONS
Routers at SOHO, stand-alone modems, PC
modems
GENERAL DESCRIPTION
The ST70135Ais the DMT modem and ATM
framerof the STMicroelectronics ASCOT
chipset. When coupled with ST70134 analog
front-end and an external controller running
dedicated firmware, the product fulfills ANSI
T1.413 ”Issue2” DMT ADSL specification.
The chip supports UTOPIA level1 and UTOPIA
level2 interface anda non ATM synchronous
bit-stream interface.
The ST70135A can be split up into two different
sections. The physical one performs the
DMT modulation, demodulation, Reed-Solomon
encoding,bit interleaving and 4D trellis coding.
The ATM section embodies framing functions for
the generic and ATM Transmission Convergence
(TC) layers.
The generic TC consistsof data scrambling and
Reed Solomon error corrections, with and without
interleaving. The ST70135Ais controlled and
programmed by an external controller (ADSL
Transceiver Controller, ATC) that sets the
programmable coefficients.
The firmware controls the initialization phase and
carries out the consequent adaptation operations.
PQFP144
ORDERING NUMBER:
ST70135A
ST70135A
ASCOT TM DMT TRANSCEIVER
ST70135A
2/29
Figure1: Block Diagram
TRANSIENT ENERGY CAPABILITIES
ESD
ESD (Electronic Discharged) tests have been
performedfor the Human Body Model (HBM) and
for the Charged Device Model (CDM). The pinsof
the device areto be ableto withstand minimum
2000V for the HBM and minimum 250V for CDM.
Latch-up
The maximum sinkor source current from any pin limitedto 200mAto prevent latch-up.
ABSOLUTE MAXIMUM RATINGS
TEST MODULE DATASYMBOL TIMINGUNIT VCXO
DSP
FRONT-END
FFT/IFFT
ROTOR
TRELLIS
CODING
GENERIC INTERFACE
MODULE
AFE CONTROL CONTROLLER ATM
TESTSIGNALS CLOCK
AFE
INTERFACE
AFE
CONTROL
CONTROLLER
BUS
GENERAL
PURPOSEI/Os
STM
UTOPIAMAPPER/
DEMAPPER
REED/
SOLOMON
INTERFACE SPECIFICTCINTERFACE
Symbol Parameter Minimum Typical Maximum Unit
VDD Supply Voltage 3.0 3.3 3.6 Vtot Total Power Dissipation 900 1400 mWamb Ambient Temperature 1m/s airflow 0 70 °C
ST70135A
3/29
Figure2: Pin Connection
AFRXD_1AFRXD_0VDDPDOWNGP_OUTTESTSETRSTBVSSTCKVDDTMSTDOTDISLT_FRAME_SSLT_REQ_SVSS
VDD
GP_IN1
VSS
U_RX_REFBU_TX_REFB
VDD
U_RXCLK
U_RXSOC
U_RXCLAV
U_RXENBB
VSS
U_TXCLK
U_TXSOC
U_TX_CLAV
U_TXENBB
VDD
VDD
SLT_REQ_F
SLT_DAT_S0
SLT_DAT_S1
SLT_DAT_F0
SLT_DAT_F1
VSS
SLT_FRAME_F
SLAT_CLOCK
SLR_VAL_F
SLR_DAT_F0
SLR_DAT_F1
SLR_VAL_S
VDD
SLR_DAT_S0
SLR_DAT_S1
VSS
AD_0
AD_1
AD_2
VDD
AD_3
AD_4
VSS
AD_5
AD_6
VDD
AD_7
AD_8
AD_9
VSS
AD_10
ST70135A
AFTXD_1AFTXD_0IDDqVDDAFTXED_3AFTXED_2VSSAFTXED_1AFTXED_0VDDCTRLDATAMCLKCLWDVSSAFRXD_3AFRXD_2
VDDAFTXD_3AFTXD_2VSS
AD_11
VDD
AD_12
VSS
PCLK
VDD
AD_13
AD_14
AD_15
VSS
BE1
ALE
VDD
CSB
WR_RDB
RDYB
OBC_TYPE
INTB
RESETB
VSS
SLR_FRAME_S
VSS
SLR_FRAME_F
U_TX_ADDR_0
U_TX_ADDR_1
U_TX_ADDR_2
VDD
U_TX_ADDR_3
U_TX_ADDR_4
U_TX_DATA_0
U_TX_DATA_1
VDD
U_TX_DATA_2
U_TX_DATA_3
U_TX_DATA_4
U_TX_DATA_5
VDD
U_TX_DATA_6
U_TX_DATA_7
VSS484950515253545556414243444546
U_RXDATA_2U_RXDATA_3
VDD
U_RXDATA_4U_RXDATA_5
VSS
U_RXDATA_6U_RXDATA_7
VDD
U_RX_ADDR_0U_RX_ADDR_1U_RX_ADDR_2U_RX_ADDR_3
VSS
U_RX_ADDR_4
GP_IN0383940
VDD
U_RXDATA_0U_RXDATA_1
VSS
ST70135A
4/29
PIN FUNCTIONS
Pin Name Type Supply Driver BS Function VSS 0V Ground AD_0 B VDD BD8SCR B Data0 AD_1 B VDD BD8SCR B Data1 AD_2 B VDD BD8SCR B Address/ Data2 VDD (VSS+ 3.3V) Power Supply AD_3 B VDD BD8SCR B Address/ Data3 AD_4 B VDD BD8SCR B Address/ Data4 VSS 0V Ground AD_5 B VDD BD8SCR B Address/ Data5 AD_6 B VDD BD8SCR B Address/ Data6 VDD (VSS+ 3.3V) Power Supply AD_7 B VDD BD8SCR B Address/ Data7 AD_8 B VDD BD8SCR B Address/ Data8 AD_9 B VDD BD8SCR B Address/ Data9 VSS 0V Ground AD_10 B VDD BD8SCR B Address/ Data10 AD_11 B VDD BD8SCR B Address/ Data11 VDD (VSS+ 3.3V) Power Supply AD_12 B VDD BD8SCR B Address/ Data12 VSS 0V Ground PCLK I VDD IBUF I Processor clock VDD (VSS+ 3.3V) Power Supply AD_13 B VDD BD8SCR B Address/ Data13 AD_14 B VDD BD8SCR B Address/ Data14 AD_15 B VDD BD8SCR B Address/ Data15 VSS 0V Ground BE1 I VDD IBUF I Address1 ALE I VDD IBUF C Address Latch VDD (VSS+ 3.3V) Power Supply CSB I VDD IBUF I Chip Select WR_RDB I VDD IBUF I Specifies the directionof the access cycle RDYB OZ VDD BT4CR O Controls the ATC bus cycle termination OBC_TYPE I-PD VDD IBUF I ATC Mode Selection(0= i960;1= generic) INTB O VDD IBUF O Requests ATC interrupt service RESETB I VDD IBUF I Hard reset VSS 0V Ground
ST70135A
5/29 VDD (VSS+ 3.3V) Power Supply U_RxData_0 OZ VDD BD8SRC B Utopia RX Data0 U_RxData_1 OZ VDD BD8SRC B Utopia RX Data1 VSS 0V Ground U_RxData_2 OZ VDD BD8SRC B Utopia RX Data2 U_RxData_3 OZ VDD BD8SRC B Utopia RX Data3 VDD (VSS+ 3.3V) Power Supply U_RxData_4 OZ VDD BD8SRC B Utopia RX Data4 U_RxData_5 OZ VDD BD8SRC B Utopia RX Data5 VSS 0V Ground U_RxData_6 OZ VDD BD8SRC B Utopia RX Data6 U_RxData_7 OZ VDD BD8SRC B Utopia RX Data7 VDD (VSS+ 3.3V) Power Supply U_RxADDR_0 I VDD IBUF I Utopia RX Address0 U_RxADDR_1 I VDD IBUF I Utopia RX Address1 U_RxADDR_2 I VDD IBUF I Utopia RX Address2 U_RxADDR_3 I VDD IBUF I Utopia RX Address3 VSS 0V Ground U_RxADDR_4 I VDD IBUF I Utopia RX Address4 GP_IN_0 I-PD VDD IBUFDQ I General purpose input0 VDD (VSS+ 3.3V) Power Supply GP_IN_1 I-PD VDD IBUFDQ I General purpose input1 VSS 0V Ground U_RxRefB O VDD IBUF O 8kHz clockto ATM device U_TxRefB I VDD BT4CR I 8kHz clock from ATM device VDD (VSS+ 3.3V) Power Supply U_Rx_CLK I VDD IBUF Utopia RX Clock U_Rx_SOC OZ VDD BD8SCR Utopia RX Startof Cell U_RxCLAV OZ VDD BD8SCR Utopia RX Cell Available U_RxENBB I VDD IBUF Utopia RX Enable VSS 0V Ground U_Tx_CLK I VDD IBUF UtopiaTX Clock U_Tx_SOC I VDD IBUF UtopiaTX Startof Cell U_TxCLAV OZ VDD BD8SCR UtopiaTX Cell Available U_TxENBB I VDD IBUF UtopiaTX Enable VDD (VSS+ 3.3V) Power Supply
Pin Name Type Supply Driver BS Function
PIN FUNCTIONS (continued)
ST70135A
6/29 VSS 0V Ground U_TxData_7 I VDD IBUF I UtopiaTX Data7 U_TxData_6 I VDD IBUF I UtopiaTX Data6 VDD (VSS+ 3.3V) Power Supply U_TxData_5 I VDD IBUF I UtopiaTX Data5 U_TxData_4 I VDD IBUF I UtopiaTX Data4 U_TxData_3 I VDD IBUF I UtopiaTX Data3 U_TxData_2 I VDD IBUF I UtopiaTX Data2 VDD (VSS+ 3.3V) Power Supply U_TxData_1 I VDD IBUF I UtopiaTX Data1 U_TxData_0 I VDD IBUF I UtopiaTX Data0 U_TxADDR_4 I VDD IBUF I UtopiaTX Address4 U_TxADDR_3 I VDD IBUF I UtopiaTX Address3 VDD (VSS+ 3.3V) Power Supply U_TxADDR_2 I VDD IBUF I UtopiaTX Address2 U_TxADDR_1 I VDD IBUF I UtopiaTX Address1 U_TxADDR_0 I VDD IBUF I UtopiaTX Address0 SLR_ FRAME_F O VDD BT4CR Frame Identifier Fast VSS 0V Ground SLR_FRAME_S O VDD BT4CR Receive Frame Identifier Interleaved SLR_DATA_S_1 O VDD BT4CR Receive Data Interleave1 SLR_DATA_S_0 O VDD BT4CR Receive Data Interleave0 VDD (VSS+ 3.3V) Power Supply SLR_VAL_S O VDD BT4CR Receive Data Valid Indicator Interleaved SLR_DATA_F_1 O VDD BT4CR Receive Data Fast1 SLR_DATA_F_0 O VDD BT4CR Receive Data Fast0 SLR_VAL_F O VDD BT4CR Receive Data Valid Indicator Fast
100 SLAP_CLOCK O VDD BT4CR Clockfor SLAPI/F
101 SLT_FRAME_F O VDD BT4CR Transmit Startof frame Indicator Fast
102 VSS 0V Ground
103 SLT_DATA_F_1 I VDD IBUFDQ Transmit Data Fast1
104 SLT_DATA_F_0 I VDD IBUFDQ Transmit Data Fast0
105 SLT_DATA_S_1 I VDD IBUFDQ Transmit Data Interleave1
106 SLT_DATA_S_0 I VDD IBUFDQ Transmit Data Interleave0
107 SLT_REQ_F O VDD BT4CR Transmit Byte Request Fast
108 VDD (VSS+ 3.3V) Power Supply
Pin Name Type Supply Driver BS Function
PIN FUNCTIONS (continued)
ST70135A
7/29
109 VSS 0V Ground
110 SLT_REQ_S O VDD BT4CR Transmit Byte Request Interleaved
111 STL_FRAME_S O VDD BT4CR Transmit Startof frame Indication Interleaved
112 TDI I-PU VDD IBUFUQ JTAGI/P
113 TDO OZ VDD BT4CR JTAG O/P
114 TMS I-PU VDD IBUFUQ JTAG Made Select
115 VDD (VSS+ 3.3V) Power Supply
116 TCK I-PD VDD IBUFDQ JTAG Clock
117 VSS 0V Ground
118 TRSTB I-PD VDD IBUFDQ JTAG Reset
119 TESTSE I VDD IBUF none Enables scan test mode
120 GP_OUT O VDD BD8SCR O General purpose output
121 PDOWN O VDD BT4CR O Power down analog front end (Reset)
122 VDD (VSS+ 3.3V) Power Supply
123 AFRXD_0 I VDD IBUF I Receive data nibble
124 AFRXD_1 I VDD IBUF I Receive data nibble
125 AFRXD_2 I VDD IBUF I Receive data nibble
126 AFRXD_3 I VDD IBUF I Receive data nibble
127 VSS 0V Ground
128 CLWD I VDD IBUF I Startof word indication
129 MCLK I VDD IBUF C Master clock
130 CTRLDATA O VDD BT4CR O Serial data Transmit channel
131 VDD (VSS+ 3.3V) Power Supply
132 AFTXED_0 O VDD BT4CR O Transmit echo nibble
133 AFTXED_1 O VDD BT4CR O Transmit echo nibble
134 VSS 0V Ground
135 AFTXED_2 O VDD BT4CR O Transmit echo nibble
136 AFTXED_3 O VDD BT4CR O Transmit echo nibble
137 VDD (VSS+ 3.3V) Power Supply
138 IDDq I VDD IBUF none Testpin, active high
139 AFTXD_0 O VDD BT4CR O Transmit data nibble
140 AFTXD_1 O VDD BT4CR O Transmit data nibble
141 VSS 0V Ground
142 AFTXD_2 O VDD BT4CR O Transmit data nibble
143 AFTXD_3 O VDD BT4CR O Transmit data nibble
144 VDD (VSS+ 3.3V) Power Supply
Pin Name Type Supply Driver BS Function
PIN FUNCTIONS (continued)
ST70135A
8/29
I/O DRIVER FUNCTION
PIN SUMMARY
Driver Function
BD4CR CMOS bidirectional, 4mA, slew rate control
BD8SCR CMOS bidirectional, 8mA, slew rate control, Schmitt trigger
IBUF CMOS input
IBUFDQ CMOS input, pull down, IDDq control
IBUFUQ CMOS input, pull up, IDDq control
Mnemonic Type BS Type Signals Function
Power Supply
VDD (VSS+ 3.3V) Power Supply
VSS 0V Ground
ATCINTERFACE
ALE I C 1 Usedto latchthe addressofthe internal registertobe
accessed
PCLK I I 1 Processor clock
CSB I I 1 Chip selectedto respondto bus cycle
BE1 I I 1 Address1 (not multiplexed)
WR_RDB I I 1 Specifies the directionof the access cycle
RDYB OZ O 1 Controls the ATC bus cycle termination
INTB O O 1 Requests ATC interrupt service IO B 16 Multiplexed Address/Data bus
OBC_TYPE I-PD I 1 Select between i960(0)or generic(1) controller interface
TEST ACCESS PART INTERFACE
TDI I-PU 1 Referto section
TDO OZ 1
TCK I-PD 1
TMS I-PU 1
TRSTB I-PD 1
ANALOG FRONT END INTERFACE
AFRXD I I 4 Receive data nibble
AFTXD O O 4 Transmit data nibble
AFTXED O O 4 Transmit echo nibble
CLWD I I 1 Startof word indication
PDOWN O O 1 Power down analog front end
CTRLDATA O O 1 Serial data transmit channel
MCLK I C 1 Master cloc
ST70135A
9/29
ATMUTOPIA INTERFACE
U_RxData OZ B 8 Receive interface Data
U_TxData I I 8 Transmit interface Data
U_RxADDR I I 5 Receive interface Address
U_TxADDR I I 5 Transmit interface Address
U_RxCLAV OZ O 1 Receive interface Cell Available
U_TxCLAV OZ O 1 Transmit interface Cell Available
U_RxENBB I-TTL I 1 Receive interface Enable
U_TxENBB I-TTL I 1 Transmit interface Enable
U_RxSOC OZ O 1 Receive interface Startof Cell
U_TxSOC I-TTL I 1 Transmit interface Startof Cell
U_RxCLK I-TTL C 1 Receive interface Utopia Clock
U_TxCLK I-TTL C 1 Transmit interface Utopia Clock
U_RxRefB O O 1 8kHz reference clockto ATM device
U_TxRefB I-TTL I 1 8kHz reference clock from ATM device
ATMSLAP INTERFACE
SLR_VAL_S O 1
SLR_VAL_F O 1
SLR_DATA_S O 2
SLR_DATA_F O 2
SLT_REQ_S O 1
SLT_REQ_F O 1
SLT_DATA_S I 2
SLT_DATA_F I 2
SLAP_CLOCK O 1
SLR_FRAME_I O 1
SLT_FRAME_I O 1
SLR_FRAME_F O 1
SLT_FRAME_F O 1
MISCELLANEOUS
GP_IN I-PD I 2 General purpose input
GP_OUT O O 1 General purpose output
RESETB I I I Hard reset
TESTSE I none none Enable scan test mode
IDDq I none none Test pin, active high
Mnemonic Type BS Type Signals Function
ST70135A
10/29 = Input, CMOS levels
I-PU = Input with pull-up resistance, CMOS
levels
I-PD = Input with pull-down resistance,
CMOS levels
I-TTL = Input TTL levels = Push-pull output = Push-pull output with high-impedance
state = Input/ Tristate Push-pull output cell= Boundary-Scan cell = Input cell = Output cell = Bidirectional cell = Clock
Main Block Description
The following drawings describe the sequenceof
functions performedby the chip.
DSP Front-End
The DSP Front-End contains4 parts in the
receive direction: the Input Selector, the Analog
Front-End Interface, the Decimator and the Time
Equalizer. The input selectoris used internallyto
enable test loopbacks inside the chip. The Analog
Front-End lnterface transfers 16-bit words,
multiplexed on4 input/output signals. Word
transferis carried outin4 clock cycles.
The Decimator receives 16-bit samplesat 8.8MHz
(as sentby the Analog Front-End chip: ST70134)
and reduces this rateto 2.2MHz.
The Time Equalizer (TEQ) moduleisa FIR filter
with programmable coefficients.Its main purpose to reduce the effect of Inter-Symbol
Interferences (ISI) by shortening the channel
impulse response. Both the Decimator and TEQ
can be bypassed.In the transmit direction, the
DSP Front-End includes: sidelobe filtering,
clipping, delay equalization and interpolation. The
sidelobe filtering and delay equalization are
implementedby IIR Filters, reducing the effectof
echoin FDM systems. Clippingisa statistical
process limiting the amplitudeof the output signal,
optimizing the dynamic rangeof the AFE. The
interpolator receives data at 2.2MHz and
generates samplesata rateof 8.8MHz.
DMT Modem
This moduleisa programmable DSP unit. Its
instruction set enables the basic functionsof the
DMT algorithm like FFT, IFFT, Scaling, Rotor and
Frequency Equalization (FEQ)in compliance with
ANSI T1.413 specifications. the RX path, the 512-point FFT transforms the
time-domain DMT symbol into a frequency
domain representation which can be further
decodedby the subsequent demapping stages. other words, the Fast Fourier Transform process usedto transform from time domainto frequency
domain (receive path). 1024 time samples are
processed. After the first stage time domain
equalization and FFT block an ICI (InterCarrier
Interference) free information stream turns out.
Figure3: DSP Front-End Receive
Figure4: DSP Front-End Transmit
From
Analog
Front-end
SELECT
AFE
I/F DEC TEC
BYPASS DMT
Modem
From
DMT
Modem
FILTERING
CLIPPING AFE
I/F Analog
Front EndDELAY
EQUALIZER
OUT
SELECT
INTER-
POLATOR
ST70135A
11/29
This streamis still affected by carrier specific
channel distortion resultingin an attenuationof
the signal amplitude anda rotationof the signal
phase. To compensate,a Frequency domain
equalizer (FEQ) anda Rotor (phase shifter) are
implemented. The frequency domain equalization
performs an operation on the received vectorin
orderto matchit with the associated pointin the
constellation. The coefficient usedto perform the
equalization are floating point, and may be
updated by hardware or software, usinga
mechanismof active and inactive tableto avoid
DMT synchro problems.In the transmit path, the
IFFT reverses the DMT symbol from frequency
domainto time domain.
The IFFT blockis preceded by Fine Tune Gain
(FTG) and Rotor stages, allowing for a
compensationof the possible frequency mismatch
between the master clock frequency and the
transmitter clock frequency (which maybe locked another reference).
The Inverse Fast Fourier Transform processis
usedto transform from frequency domainto time
domain (transmit path). 256 positive frequencies
are processed, giving 512 samplesin the time
domain.
The FFT moduleisa slave DSP engine controlled the firmware runningon an external controller. works off line and communicates with other
blocks through buffers controlled by the ”Data
Symbol Timing Unit”. The DSP executesa
program storedina RAM area, which constitutes flexible element that allows for future system
enhancements.
DPLL
The Digital PLL module receivesa metricfor the
phase errorof the pilot tone.In general, the clock
frequenciesat the ends (transmitter and receiver) not match exactly. The phase erroris filtered
and integrated bya low pass filter, yielding an
estimation of the frequency offset. Various
processes can use this estimateto deal with the
frequency mismatch. particular, small accumulated phase error can compensatedin the frequency domain bya
rotationof the received code constellation (Rotor).
Larger errors are compensatedin the time domain insertingor deleting clock cyclesin the sample
input sequence.
Eventually that leadsto achieve less than 2ppm
between the two ends.
Mapper/Demapper, Monitor, Trellis Coding,
FEQ Update
The Demapper converts the constellation points
computed by the FFTtoa blockof bits. This
means to identifya point in a 2D QAM
constellation plane. The Demapper supports
Trellis coded demodulation and providesa Viterbi
maximum likelihood estimator. When the Trellisis
active, the Demapper receives an indication for
the most likely constellation subsettobe used.
Figure5: DMT Modem (Rx& Tx)
To/From
DSPFE FFT
IFFT
FEQ
FTG
MAPPER
DEMAPPERROTOR To/From
TREILLIS
CODING
DECODING
MONITORFEQCOEFFICIENTS
FEQ
Update
Monitor
Indications
ST70135A
12/29 the transmit direction, the mapper receivesabit
stream from the Trellis encoder and modulates
thebit stream ona setof carriers (upto 256).It
generates coordinates for 2n QAM constellation,
wheren<15 forall carriers.
The Mapper performs the inverse operation,
mappinga blockof bits into one constellation
point (ina complex x+jy representation) whichis
passed to the IFFT block. The Trellis Encoder
generates redundant bits to improve the
robustness of the transmission, using a
4-Dimensional TrellisCoded Modulation scheme.
This feature can be disabled.The Monitor
computes error parameters for carriers specified the Demapper process.
Those parameters can be used for updatesof
adaptive filters coefficients, clock phase
adjustments, error detection, etc.A series of
valuesis constantly monitored, such as signal
power, pilot phase deviations, symbol erasures
generation, lossof frame, etc.
Generic TC Layer Functions
These functions relate to byte oriented data
streams. They are completely describedin ANSI 1.4 13. Additions describedin the Issue2of this
specification are also supported.
The data received from the demapper may be
split into two paths, one dedicated to an
interleaved data flow the other one fora fast data
flow. No external RAM is needed for the
interleaved path.
The interleaving/deinterleaving is used to
increase the error correcting capabilityof block
codes for error bursts. After deinterleaving(if
applicable), the data flow entersa Reed-Solomon
error correcting code decoder, ableto correcta
number of bytes containing bit errors. The
decoder also uses the information of previous
receiving stages that may have detected the error
bytes and have labelled them with an ”erasure
indication”. Each time the RS decoder detects and
corrects errors ina RS codeword, an RS
correction eventis generated.
The occurrenceof such events canbe signalledto
the management layer.After the RS decoder, the
corrected byte streamis descrambledin the PMD
(Physical Medium Dependent) descramblers. Two
descramblers are used, for interleaved and
non-interleaved data flows.
These are defined in ANSI T1.413. After
descrambling, the data flows enter the Deframer
that extracts and processes bytes to support
Physical layer related functions accordingto ANSI
T1.413. The ADSL frames indeed contain
physical layer-related informationin additionto
the data passedto the higher layers.In particular,
the deframer extracts the EOC (Embedded
Operations Channel), the AOC (ADSL Overhead
Control) and the indicators bits and passes them the appropriate processing unit (e.g. the
transceiver controller).
The deframer also performsa CRC check (Cyclic
Redundancy Check) on the received frame and
generates eventsin caseof error detection.Event
counters canbe readby management processes.
The outputsof the deframer are an interleaved
anda fast data streams. These data streams can
either carry ATM cellsor another typeof traffic.In
the latter case, the ATM specific TC layer
functional block, described hereafter,is bypassed
and the data streamis directly presentedat the
inputof the interface module.
Figure6: Generic TC Layer Functions
DATAPATXMERGER
INTERLEAVER
DE-INTERLEAVER
CODING
PMD
SCRAMBLER
PMD
SCRAMBLER
DECODING
FRAMER
DEFRAMER
ATM
IndicationBits
AOCEOC
To/From
Demapper
FAST
DESCRAMBLER
DESCRAMBLER
ST70135A
13/29
ATM Specific TC Layer Functions
The2 bytes streams (fast and slow) are received
from the byte-based processing unit. When ATM
cells are transported, this block provides basic cell
functions such as cell synchronization, cell
payload descrambling, idle/unassigned cell filter,
cell Header Error Correction (HEC) and detection.
The cell processing happens accordingto ITU-T
I.163 standard. Provisionis also made for BER
measurementsat this ATM cell level. When non
cell oriented byte streams are transported, the cell
processing unitis not active.
The interface module collects cells (from the
cell-based function module) ora Byte stream
(from the deframer). Cells are storedin FIFO’s
(424 bytesor8 cell wide, transmit buffers have the
same size), from which they are extracted by2
interface submodules, one providinga Utopia
level1 interface and the othera Utopia level2
interface.Byte stream are dumped on the SLAP
(Synchronous Link Access Protocol) interface.
Only one typeof interface can be enabledina
specific configuration.
Figure7: ATM Specific TC Layer Functions
Figure8: Interface Module
CELLSCRAMBLER
DESCRAMBLER
SYNCHRONIZER
CELLSCRAMBLER
DESCRAMBLER
SYNCHRONIZER
HEC
HEC
CELL
INSERTION/
FILTER
CELL
INSERTION/
FILTER
BER
BER
FAST
SLOW
Interface
Module
From
Generic
SLAP
LEVELUTOPIA
LEVELUTOPIA
LEVELUTOPIA
LEVELUTOPIA
SLAP
FASTATM
FAST BYTE STREAM
SLOW ATM
SLOWBYTE STREAM
From
ATM
ST70135A
14/29
DMT Symbol Timing Unit (DSTU)
The DSTU interfaces with various modules, like
DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS,
Monitor and Transceiver Controller.It consistsofa
real time anda scheduler modules. The real time
unit generatesa timebase for the DMT symbols
(sample counter), superframes (symbol counter)
and hyper-frames (sync counter). The timebases
can be modifiedby various control features. They
are continuously fine-tunedby the DPLL module.
The DSTU schedulers executea program,
controlled by program opcodes anda set of
variables, the most importantof which are real
time counters. The transmit and receive
sequencers are completely independent and run
different programs. An independent set of
variables is assigned to each of them. The
sequencer programs canbe updatedin real time.
ST70135A interfaces
Overview
See Figure9.
Processor Interface (ATC)
The ST70135Ais controlled and configuredbyan
external processor across the processor interface.
All programmable coefficients and parameters are
loaded through this path.
Data and addresses are multiplexed
ST70135A worksin 16 bits data access, so
address bit0is not used. Address bit1is not
multiplexed with data.It hasits own pin: BE1.
Byte access are not supported. Access cycle read write are alwaysin 16 bits data wide,ie bit
address A0is always zero value.
The interrupt request pinto the processoris INTB,
andisan Open Drain output.
The ST70135A supports both little and big endian.
The default featureis big endian.
Generic Interface
This interface is suitable fora number of
processors usinga multiplexed Address/data bus. this case, synchronizationof the input signals
with PCLK pinis not necessary.
Figure9: ST70135A Interfaces
AFEINTERFACETO ADSLLINE(ST70134)
RESET
JTAG
CLOCK
PROCESSOR
INTERFACE
(ATC)
DIGITALINTERFACEUTOPIA/BITSTREAM INTERFACE
ST70135A
Figure10: Generic Processor Interface Write Timing Cycle
Talew
Twr2cs
Tavsavh ale2cs T wr2d
Twdvddvh
Tcs2rdy
Tcs2wr Twrw
Tmclkcsre T rdy2wr
ALE
CSB
AD(15-0)
WRB
READY
RDB
ST70135A
15/29
Figure11: Generic Processor Interface Read Timing Cycle
Generic processor interface Cycle Timing
All AC characteristics are indicatedfora 100pF capacitive load.
Symbol Parameters Minimum Typical Maximum Unit&tf Rise& Fall time (10%to 90%) 3 ns
Talew ALE pulse width 12 ns
Tavs Address Valid setup time 10 ns
Tavh Address Valid Hold time 10 ns
Tale2cs ALEto CSB 0 ns
Tale2Z ALEto highZ stateof address bus 50 ns
Tcs2rdy CSBto RDYB asserted 60 ns
Tcsre Access Time 900 ms
Tcs2wr CSBto WRB 0 ns
Twr2d WRBto data 15 ns
Trdy2wr RDYBto WRB 0 ns
Tdvs data setup time 10 ns
Tdvh data hold time 1/2Tmclk Tmclk ns
Twr2cs WRBto CSB -10 ns
Tcs2rd CSBto RDB 0 ns
Trdy2rd RDYto RDB 0 ns
Trd2cs RDBto CSB -10 ns
Tmclk Master clock Timing
Talew
Trd2cs
Tavs
Tavh
Tale2cs T wr2d
Twdvd
Tdvh
Tcsrd
Tcsrs
Twrw
Tmclkcsre T rdy2dr
ALE
CSB
AD(15-0)
RDB
READY
WRB
Tale2Z

Partno	Mfg	Dc	Qty	Available	Descript
ST70135	ST	N/a	30	avai	ASCOTTM DMT TRANSCEIVER