ST70235A Fast Delivery |IC PHOENIX CO.,LIMITED

ST70235A ,ASCOT(TM) DMT TRANSCEIVERGENERAL DESCRIPTIONCOMPATIBLE WITH THE FOLLOWINGThe ST70235A is the DMT modem and ATMSTANDARDS: fra ..
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ST70235A
ASCOT(TM) DMT TRANSCEIVER
1/28October 2001 DMT MODEM FOR CPE ADSL,
COMPATIBLE WITH THE FOLLOWING
STANDARDS:
- ANSI T1.413 ISSUE 2
- ITU-T G.992.1 (G.DMT)
- ITU-T G.992.2 (G.LITE) SUPPORTS EITHER ATM (UTOPIA LEVEL
1 & 2) OR BITSTREAM INTERFACE 16 BIT MULTIPLEXED MICROPROCESSOR
INTERFACE (LITTLE AND BIG ENDIAN
COMPATIBILITY) ANALOG FRONT END MANAGEMENT DUAL LATENCY PATHS: FAST AND
INTERLEAVED ATM’S PHY LAYER: CELL PROCESSING
(CELL DELINEATION, CELL INSERTION,
HEC) ADSL’S OVERHEAD MANAGEMENT REED SOLOMON ENCODE/DECODE TRELLIS ENCODE/DECODE (VITERBI) DMT MAPPING / DEMAPPING OVER 256
CARRIERS FINE (2PPM) TIMING RECOVER USING
ROTOR AND ADAPTATIVE FREQUENCY
DOMAIN EQUALIZING TIME DOMAIN EQUALIZATION FRONT END DIGITAL FILTERS 0.25μm HCMOS7 TECHNOLOGY 144 PIN TQFP POWER CONSUMPTION: 0.4 WATT
APPLICATIONS
Routers at SOHO, stand-alone modems, PC
modems.
GENERAL DESCRIPTION
The ST70235A is the DMT modem and ATM
framer of the STMicroelectronics ASCOT™
chipset. When coupled with ST70134 analog
front-end and an external controller running
dedicated firmware, the product fulfills ANSI
T1.413 "Issue 2" DMT ADSL specification. The
chip supports UTOPIA level 1 and UTOPIA level 2
interface.
The ST70235A can be split up into two different
sections. The physical one performs the
DMT modulation, demodulation, Reed-Solomon
encoding, bit interleaving and 4D trellis coding.
The ATM section embodies framing functions for
the generic and ATM Transmission Convergence
(TC) layers. The generic TC consists of data
scrambling and Reed Solomon error corrections,
with and without interleaving.
The ST70235A is controlled and programmed an external controller (ADSL Transceiver Con-
troller, ATC) that sets the programmable coeffi-
cients. The firmware controls the initialization
phase and carries out the consequent adaptation
operations.
ST70235A
ASCOT TM DMT TRANSCEIVER
PRELIMINARY DATA
ST70235A
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Figure 1 : Block Diagram
Transient Energy Capabilities
ESD (Electronic Discharged) tests have been performed for the Human Body Model (HBM) and for the
Charged Device Model (CDM).
The pins of the device are to be able to withstand minimum 2000V for the HBM and minimum 250V for
CDM.
Latch-up
The maximum sink or source current from any pin is limited to 200mA to prevent latch-up.
ABSOLUTE MAXIMUM RATINGS
ST70235A
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Figure 2 : Pin Connection
ST70235A
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PIN FUNCTIONS
ST70235A
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PIN FUNCTIONS (continued)
ST70235A
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PIN FUNCTIONS (continued)
ST70235A
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Note: Compensation cell - The COMP_OUT pin must be connected at GND by a 100KΩ resistor on board.
Specifications of the resistor have to meet the following requirements:
± 5% allowed on the value, ±1% is preferred.
Advice is given to place the resistor so that there will be the shortest path between it and the pin.
Using the DISABLE_COMP signal is possible to disable the slew rate control of IOs, in this mode the IOs are however still functional,
but dynamic performances are affected.
An internal pull-down on DISABLE_COMP pin enables the slew rate control of IOs, an external pull-up resistor (connected at 3.3V)
must be inserted in order to disable the slew rate control.
Table 1 : I/O Driver Function
PIN FUNCTIONS (continued)
ST70235A
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PIN SUMMARY
ST70235A
9/28 = Input, CMOS levels
I-PU = Input with pull-up resistance, TTL
levels
I-PD = Input with pull-down resistance, TTL
levels
I-TTL = Input TTL levels = Push-pull output = Push-pull output with high-impedance
state = Input / Tristate Push-pull output
BS cell= Boundary-Scan cell = Input cell = Output cell = Bidirectional cell Clock
Main Block Description
The following drawings describe the sequence of
functions performed by the chip.
DSP Front-End
The DSP Front-End contains 4 parts in the
receive direction: the Input Selector, the Analog
Front-End Interface, the Decimator and the Time
Equalizer.
The input selector is used internally to enable test
loopbacks inside the chip. The Analog Front-End
lnterface transfers 16-bit words, multiplexed on 4
input/output signals. Word transfer is carried out in
4 clock cycles.
The Decimator receives 16-bit samples at 8.8MHz
(as sent by the Analog Front-End chip: ST70134)
and reduces this rate to 2.2MHz.
The Time Equalizer (TEQ) module is a FIR filter
with programmable coefficients. Its main purpose
is to reduce the effect of Inter-Symbol
Interferences (ISI) by shortening the channel
impulse response.
Both the Decimator and TEQ can be bypassed. In
the transmit direction, the DSP Front-End
includes: sidelobe filtering, clipping, delay
equalization and interpolation. The sidelobe
filtering and delay equalization are implemented
by IIR Filters, reducing the effect of echo in FDM
systems.
Clipping is a statistical process limiting the
amplitude of the output signal, optimizing the
dynamic range of the AFE. The interpolator
receives data at 2.2MHz and generates samples
at a rate of 8.8MHz.
DMT Modem
This module is a programmable DSP unit. Its
instruction set enables the basic functions of the
DMT algorithm like FFT, IFFT, Scaling, Rotor and
Frequency Equalization (FEQ) in compliance with
ANSI T1.413 specifications.
In the RX path, the 512-point FFT transforms the
time-domain DMT symbol into a frequency
domain representation which can be further
decoded by the subsequent demapping stages.
In other words, the Fast Fourier Transform
process is used to transform from time domain to
frequency domain (receive path). 1024 time
samples are processed. After the first stage time
domain equalization and FFT block an ICI
(InterCarrier Interference) free information stream
turns out.
PIN SUMMARY (continued)
ST70235A
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Figure 3 : DSP Front-End Receive
This stream is still affected by carrier specific
channel distortion resulting in an attenuation of
the signal amplitude and a rotation of the signal
phase. To compensate, a Frequency domain
equalizer (FEQ) and a Rotor (phase shifter) are
implemented. The frequency domain equalization
performs an operation on the received vector in
order to match it with the associated point in the
constellation. The coefficient used to perform the
equalization are floating point, and may be
updated by hardware or software, using a
mechanism of active and inactive table to avoid
DMT synchro problems.In the transmit path, the
IFFT reverses the DMT symbol from frequency
domain to time domain.
The IFFT block is preceded by Fine Tune Gain
(FTG) and Rotor stages, allowing for a
compensation of the possible frequency mismatch
between the master clock frequency and the
transmitter clock frequency (which may be locked
to another reference).
The Inverse Fast Fourier Transform process is
used to transform from frequency domain to time
domain (transmit path). 256 positive frequencies
are processed, giving 512 samples in the time
domain.
Figure 4 : DSP Front-End Transmit
Figure 5 : DMT Modem (Rx & Tx)
ST70235A
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The FFT module is a slave DSP engine controlled
by the firmware running on an external controller.
It works off line and communicates with other
blocks through buffers controlled by the "Data
Symbol Timing Unit". The DSP executes a
program stored in a RAM area, which constitutes
a flexible element that allows for future system
enhancements.
DPLL
The Digital PLL module receives a metric for the
phase error of the pilot tone. In general, the clock
frequencies at the ends (transmitter and receiver)
do not match exactly. The phase error is filtered
and integrated by a low pass filter, yielding an
estimation of the frequency offset. Various
processes can use this estimate to deal with the
frequency mismatch.
In particular, small accumulated phase error can
be compensated in the frequency domain by a
rotation of the received code constellation (Rotor).
Larger errors are compensated in the time domain
by inserting or deleting clock cycles in the sample
input sequence.
Eventually that leads to achieve less than 2ppm
between the two ends.
Mapper/Demapper, Monitor, Trellis Coding,
FEQ Update
The Demapper converts the constellation points
computed by the FFT to a block of bits. This
means to identify a point in a 2D QAM
constellation plane. The Demapper supports
Trellis coded demodulation and provides a Viterbi
maximum likelihood estimator. When the Trellis is
active, the Demapper receives an indication for
the most likely constellation subset to be used.
In the transmit direction, the mapper receives a bit
stream from the Trellis encoder and modulates
the bit stream on a set of carriers (up to 256). It
generates coordinates for 2n QAM constellation,
where n < 15 for all carriers.
The Mapper performs the inverse operation,
mapping a block of bits into one constellation
point (in a complex x+jy representation) which is
passed to the IFFT block. The Trellis Encoder
generates redundant bits to improve the
robustness of the transmission, using a
4-Dimensional Trellis Coded Modulation scheme.
This feature can be disabled.The Monitor
computes error parameters for carriers specified
in the Demapper process. Those parameters can
be used for updates of adaptive filters coefficients,
clock phase adjustments, error detection, etc. A
series of values is constantly monitored, such as
signal power, pilot phase deviations, symbol
erasures generation, loss of frame, etc.
Generic TC Layer Functions
These functions relate to byte oriented data
streams. They are completely described in ANSI
T 1.4 13. Additions described in the Issue 2 of this
specification are also supported.
The data received from the demapper may be
split into two paths, one dedicated to an
interleaved data flow the other one for a fast data
flow. No external RAM is needed for the
interleaved path.
The interleaving/deinterleaving is used to
increase the error correcting capability of block
codes for error bursts.
After deinterleaving (if applicable), the data flow
enters a Reed-Solomon error correcting code
decoder, able to correct a number of bytes
containing bit errors.
The decoder also uses the information of previous
receiving stages that may have detected the error
bytes and have labelled them with an "erasure
indication". Each time the RS decoder detects and
corrects errors in a RS codeword, an RS
correction event is generated.
The occurrence of such events can be signalled to
the management layer.After the RS decoder, the
corrected byte stream is descrambled in the PMD
(Physical Medium Dependent) descramblers. Two
descramblers are used, for interleaved and
non-interleaved data flows. These are defined in
ANSI T1.413. After descrambling, the data flows
enter the Deframer that extracts and processes
bytes to support Physical layer related functions
according to ANSI T1.413. The ADSL frames
indeed contain physical layer-related information
in addition to the data passed to the higher layers.
In particular, the deframer extracts the EOC
(Embedded Operations Channel), the AOC
(ADSL Overhead Control) and the indicators bits
and passes them to the appropriate processing
unit (e.g. the transceiver controller). The deframer
also performs a CRC check (Cyclic Redundancy
Check) on the received frame and generates
events in case of error detection.Event counters
can be read by management processes.
The outputs of the deframer are an interleaved
and a fast data streams. These data streams can
either carry ATM cells or another type of traffic. In
the latter case, the ATM specific TC layer
functional block, described hereafter, is bypassed
and the data stream is directly presented at the
input of the interface module.
ST70235A
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Figure 6 : Generic TC Layer Functions
ATM Specific TC Layer Functions
The 2 bytes streams (fast and slow) are received
from the byte-based processing unit. When ATM
cells are transported, this block provides basic cell
functions such as cell synchronization, cell
payload descrambling, idle/unassigned cell filter,
cell Header Error Correction (HEC) and detection.
The cell processing happens according to ITU-T
I.163 standard. Provision is also made for BER
measurements at this ATM cell level. When non
cell oriented byte streams are transported, the cell
processing unit is not active. The interface module
collects cells (from the cell-based function
module). Cells are stored in FIFO’s (424 bytes or
8 cell wide, transmit buffers have the same size),
from which they are extracted by 2 interface
submodules, one providing a Utopia level 1
interface and the other a Utopia level 2 interface.
Figure 7 : ATM Specific TC Layer Functions
Figure 8 : Interface Module
ST70235A
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DMT Symbol Timing Unit (DSTU)
The DSTU interfaces with various modules, like
DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS,
Monitor and Transceiver Controller. It consists of a
real time and a scheduler modules.
The real time unit generates a timebase for the
DMT symbols (sample counter), superframes
(symbol counter) and hyper-frames (sync
counter). The timebases can be modified by
various control features. They are continuously
fine-tuned by the DPLL module.
The DSTU schedulers execute a program,
controlled by program opcodes and a set of
variables, the most important of which are real
time counters.
The transmit and receive sequencers are
completely independent and run different
programs. An independent set of variables is
assigned to each of them. The sequencer
programs can be updated in real time.
ST70235A interfaces
Overview
See Figure 9.
Processor Interface (ATC)
The ST70235A is controlled and configured by an
external processor across the processor interface.
All programmable coefficients and parameters are
loaded through this path.
Data and addresses are multiplexed
ST70235A works in 16 bits data access, so
address bit 0 is not used. Address bit 1 is not
multiplexed with data. It has its own pin : BE1.
Byte access are not supported. Access cycle read
or write are always in 16 bits data wide, ie bit
address A0 is always zero value.
The interrupt request pin to the processor is INTB,
and is an Open Drain output.
The ST70235A supports both little and big endian.
The default feature is big endian.
Generic Interface
This interface is suitable for a number of
processors using a multiplexed Address/data bus.
In this case, synchronization of the input signals
with PCLK pin is not necessary.
Figure 10 : Generic Processor Interface Write Timing Cycle
Figure 9 : ST70235A Interfaces
ST70235A
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Figure 11 : Generic Processor Interface Read Timing Cycle
Generic processor interface Cycle Timing
All AC characteristics are indicated for a 100pF capacitive load.Cycle timing for generic interface.
The timing are generally presented with the write signal, but as shown on the read diagram, they are also
valid for the read signal, so for example the Trdy2wr timing is the same as what can be Trdy2rd.
Table 2 : Cycle timing

Partno	Mfg	Dc	Qty	Available	Descript
ST70235A	ST	N/a	6120	avai	ASCOT(TM) DMT TRANSCEIVER