ST72T311J2-ST72T311J4 Fast Delivery |IC PHOENIX CO.,LIMITED

ST72T311J4 ,8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERSFunctional Description . . . ... .. .. . 784.6.4 Low Power Modes . . . .... . ... .. .. . . .... .. ..
ST72T311J4 ,8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERSGeneral Description . . . . . ... .. .. . 173.1.2 External Clock . . . . . ........ .. .. .. ..... ..
ST72T311J4T3 ,8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERSGeneral Description . 173.1.2 External Clock . . . . . 173.2 RESET 183.2.1 Int ..
ST72T311J4T6 ,8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERSFunctional Description . . . . . . . 795.6.4 Low Power Modes . . 795.6.5 Interrupts ..
ST72T311N4B6 ,8-BIT MICROCONTROLLER (MCU) WITH 8 TO 16K ROM/OTP/EPROM,384 TO 512 BYTES RAM,ADC,WDG,SCI,SPI AND 2 TIMERSfeatures an enhanced instruction set. The device Voltage Detector (LVD) and the following on-chipis ..
ST72T311R6 ,8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACESTable of Contents12.4.5 On-Chip Peripheral . . . . . . . 13712.5 CLOCK AND TIMING CHARACTERI ..
STR7102 , Separate Excitation Switching Type
STR7102 , Separate Excitation Switching Type
STR710FZ1H6 ,ARM-Based Flash microcontrollers with USB and CANAbsolute maximum ratings . . . . 354.3 Operating conditions 374.3.1 Supply current charac ..
STR710FZ2T6 ,STR71x: 144/64-pin ARM7TDMI MCU with up to 256KB FLASH, 64KB RAM and EMIfeatures including CAN, USB and External Memory Interface. The two 64-pin versions do notinclude Ex ..
STR710RZH6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANFeatures■ Core– ARM7TDMI 32-bit RISC CPULQFP6410 x 10– 59 MIPS @ 66 MHz from SRAM LQFP14420 x 20– 4 ..
STR710RZT6 ,ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CANThermal characteristics . . . . 36Table 11. General operating conditions . . . . . . . 37 ..

ST72T311J2-ST72T311J4
8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
September 1999 1/100
ST72E311
ST72T311
8-BIT MCU WITH8 TO 16K OTP/EPROM,
384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND2 TIMERS
DATASHEET User Program Memory (OTP/EPROM):to 16K bytes Data RAM: 384 to512 bytesincluding 256 bytes stack Master Reset and Power-On Reset Low Voltage Detector Reset option Run and Power Saving modes 44or32 multifunctional bidirectional I/O lines: 15or9 programmable interrupt inputs8or4 high sink outputs8or6 analog alternate inputs 13 alternate functions EMI filtering Softwareor Hardware Watchdog (WDG) Two 16-bit Timers, each featuring:2 Input Captures1)2 Output Compares1) External Clock input (on TimerA) PWM and Pulse Generator modes Synchronous Serial Peripheral Interface (SPI) Asynchronous Serial Communications Interface
(SCI) 8-bit ADC with8 channels2) 8-bit Data Manipulation 63 basic Instructions and 17 main Addressing
Modes 8x8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on DOS/
WINDOWSTM Real-Time Emulator Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
Notes: One onlyon TimerA.Six channels onlyfor ST72T311J.
Device Summary
Note: The ROM versions are supportedby the ST72314 family.
TQFP44
PSDIP42
PSDIP56
CSDIP42W
CSDIP56W
TQFP64
(See ordering informationat the endof datasheet)
Features ST72T311J2 ST72T311J4 ST72T311N2 ST72T311N4
Program Memory- bytes 8K 16K 8K 16K
RAM (stack)- bytes 384 (256) 512 (256) 384 (256) 512 (256)
Peripherals Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset
Operating Supply 3to5.5V
CPU Frequency 8MHz max (16MHz oscillator)- 4MHz max over 85°C
Temperature Range - 40°Cto+ 125°C
Package TQFP44- SDIP42 TQFP64- SDIP56
Rev. 1.7
2/100
Table of Contents
100 GENERAL DESCRIPTION...... ..... ......... .... ....... ............ ...........4
1.1 INTRODUCTION............. ...... ..... .............. ....... ...... ......4
1.2 PIN DESCRIPTION.. ..... ....... ...... ..... ......... ....... ........... ...5
1.3 EXTERNAL CONNECTIONS....................................... ..... ....9
1.4 MEMORY MAP.......... ..... ... ...... .... ................... ...... .... 10
1.5 OPTION BYTE....... ........................... ............ ....... ..... 13 CENTRAL PROCESSING UNIT.. ..... ......... .... ....... ............ .......... 14
2.1 INTRODUCTION............. ...... ..... .............. ....... ...... ..... 14
2.2 MAIN FEATURES............................ .... .... ........... ........ 14
2.3 CPU REGISTERS... ....................... ... ............. ............. 14 CLOCKS, RESET, INTERRUPTS& POWER SAVING MODES............. ...... ..... 17
3.1 CLOCK SYSTEM............. ...... ..... .............. ....... ...... ..... 17
3.1.1 General Description...... ...... ..... .............. ....... ...... ..... 17
3.1.2 External Clock................ ............ ....... ............. ..... 17
3.2 RESET..................................... .... .... ........... ........ 18
3.2.1 Introduction... ....................... ... ............. ............. 18
3.2.2 External Reset...... ..... ......... .... ................... ...... .... 18
3.2.3 Reset Operation......................... ........ .... ....... ........ 18
3.2.4 Low Voltage Detector Reset.......................................... 19
3.3 INTERRUPTS.......................................................... 20
3.4 POWER SAVING MODES......................................... ..... ... 23
3.4.1 Introduction... ....................... ... ............. ............. 23
3.4.2 Slow Mode....................... ....... ................ ... ....... 23
3.4.3 Wait Mode................... ....... ..... ....... ...... ....... ..... 23
3.4.4 Halt Mode..... ....................... ... ............. ............. 24
3.5 MISCELLANEOUS REGISTER.............. ............ .... ............... 25 ON-CHIP PERIPHERALS........... ...... ..... .... ....................... ..... 26
4.1 I/O PORTS.................. ...... ..... .............. ....... ...... ..... 26
4.1.1 Introduction... ....................... ... ............. ............. 26
4.1.2 Functional Description.... ...... ..... .............. ....... ...... ..... 26
4.1.3 I/O Port Implementation................... ....... .... ....... ......... 27
4.1.4 Register Description...... ...... ..... .............. ....... ...... ..... 30
4.2 WATCHDOG TIMER (WDG)............................................... 32
4.2.1 Introduction... ....................... ... ............. ............. 32
4.2.2 Main Features...... ..... ......... .... ....... ............ ...... .... 32
4.2.3 Functional Description.... ...... ..... .............. ....... ...... ..... 32
4.2.4 Hardware Watchdog Option.......... ....... ................ .......... 33
4.2.5 Low Power Modes... ..... ......... .... ....... ............ .......... 33
4.2.6 Interrupts........................ ....... ................ ... ....... 33
4.2.7 Register Description...... ...... ..... .............. ....... ...... ..... 33
4.3 16-BIT TIMER..................... ............ ....... ...... ....... ..... 35
4.3.1 Introduction... ....................... ... ............. ............. 35
4.3.2 Main Features...... ..... ......... .... ....... ............ ...... .... 35
4.3.3 Functional Description.... ...... ..... .............. ....... ...... ..... 35
4.3.4 Low Power Modes .. ..... .......... .... ....... ...... ..... ....... ... 46
4.3.5 Interrupts..... .................. ..... .......... .... ............... 46
4.3.6 Register Description...... ...... ..... .............. ....... ...... ..... 47
4.4 SERIAL COMMUNICATIONS INTERFACE (SCI)............................... 52
4.4.1 Introduction... ....................... ... ............. ............. 52
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Table of Contents
4.4.2 Main Features...... ..... ......... .... ....... ............ ...... .... 52
4.4.3 General Description...... ...... ..... .............. ....... ...... ..... 52
4.4.4 Functional Description.... ...... ..... .............. ....... ...... ..... 54
4.4.5 Low Power Modes... ..... ......... .... ....... ............ .......... 59
4.4.6 Interrupts........................ ....... ................ ... ....... 59
4.4.7 Register Description...... ...... ..... .............. ....... ...... ..... 60
4.5 SERIAL PERIPHERAL INTERFACE (SPI)......................... ...... ..... 64
4.5.1 Introduction... ....................... ... ............. ............. 64
4.5.2 Main Features...... ..... ......... .... ....... ............ ...... .... 64
4.5.3 General description................................................. 64
4.5.4 Functional Description.... ...... ..... .............. ....... ...... ..... 66
4.5.5 Low Power Modes... ..... ......... .... ....... ............ .......... 73
4.5.6 Interrupts..... .................. ..... .......... .... ............... 73
4.5.7 Register Description...... ...... ..... .............. ....... ...... ..... 74
4.6 8-BIT A/D CONVERTER (ADC).................. .... .... .... ....... ........ 77
4.6.1 Introduction... ....................... ... ............. ............. 77
4.6.2 Main Features...... ..... ......... .... ....... ............ ...... .... 77
4.6.3 Functional Description.... ...... ..... .............. ....... ...... ..... 78
4.6.4 Low Power Modes... ..... ......... .... ....... ............ .......... 78
4.6.5 Interrupts........................ ....... ................ ... ....... 78
4.6.6 Register Description...... ...... ..... .............. ....... ...... ..... 79 INSTRUCTION SET..................... ....... ..... ....... ...... ....... ..... 80
5.1 ST7 ADDRESSING MODES............................................... 80
5.1.1 Inherent........... ..... ......... .... ................... ...... .... 81
5.1.2 Immediate........................................................ 81
5.1.3 Direct. .... .... .... ....... ....... .... ......... .... ................ 81
5.1.4 Indexed (No Offset, Short, Long)............ ....... .... ....... ......... 81
5.1.5 Indirect (Short, Long)................................................ 81
5.1.6 Indirect Indexed (Short, Long).... ..... .............. ....... ...... ..... 82
5.1.7 Relative mode (Direct, Indirect)........................................ 82
5.2 INSTRUCTION GROUPS................ ....................... ...... .... 83 ELECTRICAL CHARACTERISTICS................... .... .... ........... ........ 86
6.1 ABSOLUTE MAXIMUM RATINGS...... ..... .............. ....... ...... ..... 86
6.2 RECOMMENDED OPERATING CONDITIONS...... .... .... ........... ........ 87
6.3 DC ELECTRICAL CHARACTERISTICS........................... ...... ..... 88
6.4 RESET CHARACTERISTICS............. ..... ....... ........... ....... ... 89
6.5 OSCILLATOR CHARACTERISTICS........... ...... ....... ..... ....... ..... 89
6.6 PERIPHERAL CHARACTERISTICS.......... ............ .... ............... 89 GENERAL INFORMATION.......... ...... ..... .............. ....... ...... ..... 95
7.1 EPROM ERASURE........................... ..... ... ........... ........ 95
7.2 PACKAGE MECHANICAL DATA................. ........ .... ....... ........ 96
7.3 ORDERING INFORMATION............. ..... ......... .................... 99 SUMMARY OF CHANGES.................................................... 100
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ST72E311 ST72T311 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST72T311 HCMOS Microcontroller Unit
(MCU)isa memberof the ST7 family. The device based on an industry-standard 8-bit core and
features an enhanced instruction set. The device normally operatedata 16 MHz oscillator fre-
quency. Under software control, the ST72T311
may be placedin either Wait, Slowor Halt modes,
thus reducing power consumption. The enhanced
instruction set and addressing modes afford real
programming potential.In additionto standard
8-bit data management, the ST72T311 features
truebit manipulation, 8x8 unsigned multiplication
and indirect addressing modeson the whole mem-
ory. The device includesa low consumption and
fast start on-chip oscillator, CPU, program memo- (OTP/EPROM versions), RAM, 44
(ST72T311N)or 32 (ST72T311J) I/O lines,a Low
Voltage Detector (LVD) and the following on-chip
peripherals: Analog-to-Digital converter (ADC)
with8 (ST72T311N)or6 (ST72T311J) multiplexed
analog inputs, industry standard synchronous SPI
and asynchronous SCI serial interfaces, digital
Watchdog, two independent 16-bit Timers, one
featuringan External Clock Input, and both featur-
ing Pulse Generator capabilities,2 Input Captures
and2 Output Compares (only1 Input Capture and Output Compareon Timer A).
Figure1. ST72T311 Block Diagram
8-BIT CORE
ALU
ADDRESS
AND
DATA
BUS
OSCIN
OSCOUT
RESET PORTB
TIMERB
PORTC
SPI
PORTE
SCI
PORTD
8-BIT ADC
WATCHDOG
PB0-> PB7
PC0-> PC7
PE0-> PE7
PD0-> PD7
OSC
Internal
CLOCK
CONTROL
RAM
(384 -512 Bytes)
PORTFPF0-> PF2,4,6,7
TIMERA
PORTA PA0-> PA7
VSSA
VDDAbitsfor ST72T311N)(6 bits)
AND LVDbitsfor ST72T311J) bitsfor ST72T311N)bitsfor ST72T311J) bitsfor ST72T311N)bitsfor ST72T311J) bits) bitsfor ST72T311N)bitsfor ST72T311J)
VSS
VDD POWER
SUPPLY
PROGRAM- 16K Bytes)
MEMORY
5/100
ST72E311 ST72T311
1.2 PIN DESCRIPTION
Figure2. 64-Pin Thin QFP Package Pinout
Figure3. 56-Pin Shrink DIP Package Pinout
Figure4. 44-Pin Thin QFP Package Pinout
Figure5. 42-Pin Shrink DIP Package Pinout
646362 616059585756 55545352515049
1718192021 222324 29 30313225262728
PE4
PE5
PE6
PE7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
VSS_1
VDD_1
PA3
PA2
PA1
PA0
PC7/SS
PC6/SCK
PC5/MOSI
PC4/MISO
PC3/ICAP1_B
PC2/ICAP2_B
PC1/OCMP1_B
PC0/OCMP2_B
VSS_0
VDD_0
AIN4/PD4AIN5/PD5AIN6/PD6AIN7/PD7
DDA
SSA
DD_3
SS_3
CLKOUT/PF0
PF1PF2
OCMP1_A/PF4
ICAP1_A/PF6
EXTCLK_A/PF7NCPE1/RDIPE0/TDOV
DD_2
OSCINOSCOUTV
SS_2NCRESETTEST/V
PA7PA6PA5PA4
(EI0)
(EI0)
(EI0)
(EI0)
(EI2)
(EI2)
(EI2)
(EI2)
(EI3)
(EI3)
(EI3)
(EI3)
(EI1)(EI1)(EI1)
1.V EPROM/OTPonly (EI1) (EI1) (EI1) 29
(EI0)31
(EI0)32
(EI0)33
(EI0)34
CLKOUT/PF0
PF1
PF2
OCMP1_A/PF4
ICAP1_A/PF6
PC1/OCMP1_B
PC2/ICAP2_B
EXTCLK_A/PF7
VDD_0
VSS_0
RESET
TEST/VPP1)
PA7
PA6
PA5
PA2
PA1
PA0
PC7/SS
PC6/SCK
PC0/OCMP2_B
PC3/ICAP1_B
PC4/MISO
PC5/MOSI
PA4
VSS_1
VDD_1
PA3 (EI3) (EI3) (EI3) (EI3) 43
PB4
PB5
PB6
PB7
AIN0/PD0
AIN5/PD5
AIN6/PD6
AIN1/PD1
AIN2/PD2
AIN3/PD3
PB3
PB2
PB1
PB0
PE7
PE0/TD0
VDD_2
OSCIN
OSCOUT
VSS_2
(EI2)56
(EI2)55
(EI2)54
(EI2)53
AIN4/PD4
AIN7/PD7VDDA
VSSA
PE6
PE5
PE4
PE1/RDI
1.VPPon EPROM/OTPonly4342414039383736353413141516171819
(EI1)(EI1)(EI1)2122
CLKOUT/PF0
PF1PF2
OCMP1_A/PF4
ICAP1_A/PF6
PC1/OCMP1_B
PC2/ICAP2_B
EXTCLK_A/PF7
DD_0
SS_0
PC0/OCMP2_B
PC3/ICAP1_B
PC4/MISO
PC5/MOSIPB4
AIN0/PD0
AIN5/PD5
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
DDA
SSA
RESETTEST/V
PA7PA6PA5
PC7/SS
PC6/SCK
PA4
VSS_1
VDD_1
PA3
PB3
PB2
PB1
PB0
PE0/TD0V
DD_2
OSCINOSCOUTV
SS_2
PE1/RDI
(EI3)
(EI2)
(EI2)
(EI2)
(EI2)
(EI0)
1.VPPon EPROM/OTPonly
CLKOUT/PF0
PF1
PF2
OCMP1_A/PF4
ICAP1_A/PF6
PC1/OCMP1_B
PC2/ICAP2_B
EXTCLK_A/PF7
RESET
TEST/VPP1)
PA7
PA6
PA5
PC7/SS
PC6/SCK
PC0/OCMP2_B
PC3/ICAP1_B
PC4/MISO
PC5/MOSI
PA4
VSS_1
VDD_1
PA3 29
PB4
AIN0/PD0
AIN5/PD5
AIN1/PD1
AIN2/PD2
AIN3/PD3
PB3
PB2
PB1
PB0
PE0/TD0VDD_2
OSCIN
OSCOUT
VSS_2
AIN4/PD4
VDDA
VSSA
PE1/RDI
(EI3)
(EI1)
(EI1)
(EI1)
(EI0)
(EI2)
(EI2)
(EI2)
(EI2)
1.VPPon EPROM/OTPonly
6/100
ST72E311 ST72T311
Table1. ST72T311Nx Pin Description
Pinn°
QFP64
Pinn°
SDIP56 Pin Name Type Description Remarks 49 PE4 I/O PortE4 High Sink 50 PE5 I/O PortE5 High Sink 51 PE6 I/O PortE6 High Sink 52 PE7 I/O PortE7 High Sink 53 PB0 I/O PortB0 External Interrupt: EI2 54 PB1 I/O PortB1 External Interrupt: EI2 55 PB2 I/O PortB2 External Interrupt: EI2 56 PB3 I/O PortB3 External Interrupt: EI2 1 PB4 I/O PortB4 External Interrupt: EI3 2 PB5 I/O PortB5 External Interrupt: EI3 3 PB6 I/O PortB6 External Interrupt: EI3 4 PB7 I/O PortB7 External Interrupt: EI3 5 PD0/AIN0 I/O PortD0or ADC Analog Input0 6 PD1/AIN1 I/O PortD1or ADC Analog Input1 7 PD2/AIN2 I/O PortD2or ADC Analog Input2 8 PD3/AIN3 I/O PortD3or ADC Analog Input3 9 PD4/AIN4 I/O PortD4or ADC Analog Input4 10 PD5/AIN5 I/O PortD5or ADC Analog Input5 11 PD6/AIN6 I/O PortD6or ADC Analog Input6 12 PD7/AIN7 I/O PortD7or ADC Analog Input7 13 VDDA S Power Supplyfor analog peripheral (ADC) 14 VSSA S Groundfor analog peripheral (ADC) V DD_3 S Main power supply VSS_3 S Ground 15 PF0/CLKOUT I/O PortF0or CPU Clock Output External Interrupt: EI1 16 PF1 I/O PortF1 External Interrupt: EI1 17 PF2 I/O PortF2 External Interrupt: EI1 NC Not Connected 18 PF4/OCMP1_A I/O PortF4or TimerA Output Compare1 NC Not Connected 19 PF6/ICAP1_A I/O PortF6or TimerA Input Capture1 20 PF7/EXTCLK_A I/O PortF7or External Clockon TimerA 21 VDD_0 S Main power supply 22 VSS_0 S Ground 23 PC0/OCMP2_B I/O PortC0or TimerB Output Compare2 24 PC1/OCMP1_B I/O PortC1or TimerB Output Compare1 25 PC2/ICAP2_B I/O PortC2or TimerB Input Capture2 26 PC3/ICAP1_B I/O PortC3or TimerB Input Capture1 27 PC4/MISO I/O PortC4or SPI MasterIn/ Slave Out Data 28 PC5/MOSI I/O PortC5or SPI Master Out/ SlaveIn Data 29 PC6/SCK I/O PortC6or SPI Serial Clock 30 PC7/SS I/O PortC7or SPI Slave Select 31 PA0 I/O PortA0 External Interrupt: EI0 32 PA1 I/O PortA1 External Interrupt: EI0
7/100
ST72E311 ST72T311
Note1: VPPon EPROM/OTP only.
Table2. ST72T311Jx Pin Description 33 PA2 I/O PortA2 External Interrupt: EI0 34 PA3 I/O PortA3 External Interrupt: EI0 35 V DD_1 S Main power supply 36 VSS_1 S Ground 37 PA4 I/O PortA4 High Sink 38 PA5 I/O PortA5 High Sink 39 PA6 I/O PortA6 High Sink 40 PA7 I/O PortA7 High Sink 41 TEST/VPP1) S
Test mode pin.In the EPROM programming
mode, thispin actsasthe programming voltage
inputVPP.
Thispin mustbe tied
lowin user mode 42 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt. NC Not Connected NC Not Connected 43 VSS_2 S Ground 44 OSCOUT O Input/Output Oscillator pin. These pins connecta parallel-resonant
crystal,oran external sourceto the on-chip oscillator.59 45 OSCIN I 46 VDD_2 S Main power supply 47 PE0/TDO I/O PortE1or SCI Transmit Data Out 48 PE1/RDI I/O PortE1or SCI Receive DataIn NC Not Connected NC Not Connected
Pinn°
QFP64
Pinn°
SDIP56 Pin Name Type Description Remarks
Pinn°
QFP44
Pinn°
SDIP42 Pin Name Type Description Remarks 38 PE1/RDI I/O PortE1or SCI Receive DataIn 39 PB0 I/O PortB0 External Interrupt: EI2 40 PB1 I/O PortB1 External Interrupt: EI2 41 PB2 I/O PortB2 External Interrupt: EI2 42 PB3 I/O PortB3 External Interrupt: EI2 1 PB4 I/O PortB4 External Interrupt: EI3 2 PD0/AIN0 I/O PortD0or ADC Analog Input0 3 PD1/AIN1 I/O PortD1or ADC Analog Input1 4 PD2/AIN2 I/O PortD2or ADC Analog Input2 5 PD3/AIN3 I/O PortD3or ADC Analog Input3 6 PD4/AIN4 I/O PortD4or ADC Analog Input4 7 PD5/AIN5 I/O PortD5or ADC Analog Input5 8 VDDA S Power Supplyfor analog peripheral (ADC) 9 VSSA S Groundfor analog peripheral (ADC) 10 PF0/CLKOUT I/O PortF0or CPU Clock Output External Interrupt: EI1 11 PF1 I/O PortF1 External Interrupt: EI1 12 PF2 I/O PortF2 External Interrupt: EI1 13 PF4/OCMP1_A I/O PortF4or TimerA Output Compare1
8/100
ST72E311 ST72T311
Note1: VPPon EPROM/OTP only. 14 PF6/ICAP1_A I/O PortF6or TimerA Input Capture1 15 PF7/EXTCLK_A I/O PortF7or External Clockon TimerA VDD_0 S Main power supply VSS_0 S Ground 16 PC0/OCMP2_B I/O PortC0or TimerB Output Compare2 17 PC1/OCMP1_B I/O PortC1or TimerB Output Compare1 18 PC2/ICAP2_B I/O PortC2or TimerB Input Capture2 19 PC3/ICAP1_B I/O PortC3or TimerB Input Capture1 20 PC4/MISO I/O PortC4or SPI MasterIn/ Slave Out Data 21 PC5/MOSI I/O PortC5or SPI Master Out/ SlaveIn Data 22 PC6/SCK I/O PortC6or SPI Serial Clock 23 PC7/SS I/O PortC7or SPI Slave Select 24 PA3 I/O PortA3 External Interrupt: EI0 25 VDD_1 S Main power supply 26 VSS_1 S Ground 27 PA4 I/O PortA4 High Sink 28 PA5 I/O PortA5 High Sink 29 PA6 I/O PortA6 High Sink 30 PA7 I/O PortA7 High Sink 31 TEST/VPP1) S
Test mode pin.In the EPROM programming
mode, thispin actsasthe programming
voltage inputVPP.
Thispin mustbe tied
lowin user mode 32 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt. 33 VSS_2 S Ground 34 OSCOUT O Input/Output Oscillator pin. These pins connecta parallel-resonant
crystal,oran external sourceto the on-chip oscillator.42 35 OSCIN I 36 VDD_2 S Main power supply 37 PE0/TDO I/O PortE0or SCI Transmit Data Out
Pinn°
QFP44
Pinn°
SDIP42 Pin Name Type Description Remarks
9/100
ST72E311 ST72T311
1.3 EXTERNAL CONNECTIONS
The following figure shows the recommended ex-
ternal connectionsfor the device.
TheVPP pinis only used for programming OTP
and EPROM devices and mustbe tiedto groundin
user mode.
The 10 nF and 0.1 μF decoupling capacitors on
the power supply lines area suggested EMC per-
formance/cost tradeoff.
The external reset networkis intendedto protect
the device against parasitic resets, especiallyin
noisy environments.
Unused I/Os shouldbe tied highto avoid any un-
necessary power consumption on floating lines. alternative solutionisto program the unused
portsas inputs with pull-up.
Figure6. Recommended External Connections
VPP
VDDSS
OSCIN
OSCOUT
RESET
VDD
0.1μF+
See
Clocks
Section
VDD
0.1μF
0.1μF
EXTERNAL RESET CIRCUIT configure unusedI/O ports
UnusedI/O
10nF
4.7K
10K softwareas input with pull-up
VDD
VDDA
VSSA
See
A/D Converter
Section
Detector (LVD)is usedOptionalif Low Voltage
10/100
ST72E311 ST72T311
1.4 MEMORY MAP
Figure7. Program Memory Map
Table3. Interrupt Vector Map
Vector Address Description Remarks
FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h
FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh
FFEE-FFEFh
FFF0-FFF1h
FFF2-FFF3h
FFF4-FFF5h
FFF6-FFF7h
FFF8-FFF9h
FFFA-FFFBh
FFFC-FFFDh
FFFE-FFFFh
Not Used
Not Used
Not Used
SCI Interrupt Vector
TIMERB Interrupt Vector
TIMERA Interrupt Vector
SPI interrupt vector
Not Used
External Interrupt Vector EI3
External Interrupt Vector EI2
External Interrupt Vector EI1
External Interrupt Vector EI0
Not Used
Not Used
TRAP (software) Interrupt Vector
RESET Vector
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
External Interrupt
External Interrupt
External Interrupt
External Interrupt
CPU Interrupt
0000h
Interrupt& Reset Vectors Registers
027Fh
0080h
Short Addressing
RAM (zero page)
16-bit Addressing
RAM
007Fh
0200h /0280h
Reserved
0080h
(see Table4)
FFDFh
FFE0h
FFFFh (see Table3)
027Fh
C000h
BFFFh
00FFh
0100h
01FFh
0200h BytesE000h
16K Bytes
Program
Short Addressing
RAM (zero page)
0080h
00FFh
01FFh
01FFh
384 Bytes RAM
512 Bytes RAM
256 Bytes Stack/
16-bit Addressing RAM
256 Bytes Stack/
16-bit Addressing RAM
0100h
Memory
Program
Memoryl
11/100
ST72E311 ST72T311
Table4. Hardware Register Memory Map
Address Block Register
Label Register Name Reset
Status Remarks
0000h
0001h
0002h
PortA
PADR
PADDR
PAOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W1)
0003h Reserved Area(1 byte)
0004h
0005h
0006h
PortC
PCDR
PCDDR
PCOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W
0007h Reserved Area(1 byte)
0008h
0009h
000Ah
PortB
PBDR
PBDDR
PBOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W1)
000Bh Reserved Area(1 byte)
000Ch
000Dh
000Eh
PortE
PEDR
PEDDR
PEOR
Data Register
Data Direction Register
Option Register
00h
00h
0Ch
R/W
R/W
R/W1)
000Fh Reserved Area(1 byte)
0010h
0011h
0012h
PortD
PDDR
PDDDR
PDOR
Data Register
Data Direction Register
Option Register
00h
00h
00h
R/W
R/W
R/W1)
0013h Reserved Area(1 byte)
0014h
0015h
0016h
PortF
PFDR
PFDDR
PFOR
Data Register
Data Direction Register
Option Register
00h
00h
28h
R/W
R/W
R/W1)
0017hto
001Fh Reserved Area(9 bytes)
0020h MISCR Miscellaneous Register 00h
0021h
0022h
0023h
SPI
SPIDR
SPICR
SPISR
SPI DataI/O Register
SPI Control Register
SPI Status Register
xxh
xxh
00h
R/W
R/W
Read Only
0024hto
0029h Reserved Area(6 bytes)
002Ah
002Bh WDG
WDGCR
WDGSR
Watchdog Control Register
Watchdog Status Register
7Fh
00h
R/W
R/W3)
002Chto
0030h Reserved Area(5 bytes)
12/100
ST72E311 ST72T311
Notes: The bits correspondingto unavailable pins are forcedto1by hardware, this affectsthe reset status value. Externalpin not available. Not usedin versions without Low Voltage Detector Reset.
0031h
0032h
0033h
0034h-0035h
0036h-0037h
0038h-0039h
003Ah-003Bh
003Ch-003Dh
003Eh-003Fh
TimerA
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only2)
Read Only2)
R/W2)
R/W2)
0040h Reserved Area(1 byte)
0041h
0042h
0043h
0044h-0045h
0046h-0047h
0048h-0049h
004Ah-004Bh
004Ch-004Dh
004Eh-004Fh
TimerB
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
SCI
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register1
SCI Control Register2
SCI Extended Receive Prescaler Register
Reserved
SCI Extended Transmit Prescaler Register
C0h
xxh
00x----xb
xxh
00h
00h
00h
Read Only
R/W
R/W
R/W
R/W
R/W
Reserved
R/W
0058hto
006Fh Reserved Area (24 bytes)
0070h
0071h ADC ADCDR
ADCCSR
ADC Data Register
ADC Control/Status Register
00h
00h
Read Only
R/W
0072hto
007Fh Reserved Area (14 bytes)
Address Block Register
Label Register Name Reset
Status Remarks
13/100
ST72E311 ST72T311
1.5 OPTION BYTE
The user has the optionto select software watch-
dogor hardware watchdog (see descriptionin the
Watchdog chapter). When programming EPROM OTP devices, this optionis selectedina menu the userof the EPROM programmer before
burning the EPROM/OTP. The Option Byteis lo-
catedina non-user map. No address hasto be
specified. The Option Byteis atFFh after UVeras-
ure and must be properly programmedto set de-
sired options.
OPTBYTE
Bit 7:4= Not used
Bit3= Reserved, mustbe cleared.
Bit2= Reserved, mustbe seton ST72T311N de-
vices and mustbe clearedon ST72T311J devices.
Bit1= Not used
Bit0= WDG Watchdog disable The Watchdogis enabled after reset (Hardware
Watchdog). The Watchdogis not enabled after reset (Soft-
ware Watchdog). - - - b3 b2 - WDG
14/100
ST72E311 ST72T311 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
This CPU hasa full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
2.2 MAIN FEATURES 63 basic instructions Fast 8-bitby 8-bit multiply 17 main addressing modes (with indirect
addressing mode) Two 8-bit index registers 16-bit stack pointer 8 MHz CPU internal frequency Low power modes Maskable hardware interrupts Non-maskable software interrupt
2.3 CPU REGISTERS
The6 CPU registers shownin Figure8 are not
presentin the memory mapping and are accessed specific instructions.
Accumulator (A)
The Accumulatorisan 8-bit general purpose reg-
ister usedto hold operands and the resultsof the
arithmetic and logic calculations andto manipulate
data.
Index Registers(X andY) indexed addressing modes, these 8-bit registers
are usedto create either effective addressesor
temporary storage areas for data manipulation.
(The Cross-Assembler generatesa precede in-
struction (PRE)to indicate that the following in-
struction refersto theY register.)
TheY registeris not affectedby the interrupt auto-
matic procedures (not pushedto and popped from
the stack).
Program Counter (PC)
The program counterisa 16-bit register containing
the addressof the next instructiontobe executed the CPU.Itis madeof two 8-bit registers PCL
(Program Counter Low whichis the LSB) and PCH
(Program Counter High whichis the MSB).
Figure8. CPU Registers
ACCUMULATOR INDEX REGISTER INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER11HI NZ
RESET VALUE= RESET VECTOR@ FFFEh-FFFFh715 8PCH PCL 87 0
RESET VALUE= STACK HIGHER ADDRESS
RESET VALUE= 1X11X 1XX
RESET VALUE= XXh
RESET VALUE= XXh
RESET VALUE= XXh= Undefined Value
15/100
ST72E311 ST72T311
CENTRAL PROCESSING UNIT (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
The 8-bit Condition Code register contains thein-
terrupt mask and four flags representativeof the
resultof the instruction just executed. This register
can alsobe handledby the PUSH and POP in-
structions.
These bits canbe individually tested and/or con-
trolledby specific instructions.
Bit4=H Half carry.
Thisbitis setby hardware whena carry occurs be-
tween bits3 and4of the ALU during an ADDor
ADC instruction.Itis resetby hardware during the
same instructions. No half carry has occurred.A half carry has occurred.
This bitis tested using the JRHor JRNH instruc-
tion. TheHbitis usefulin BCD arithmetic subrou-
tines.
Bit3=I Interrupt mask.
Thisbitis setby hardware when enteringin inter-
ruptorby softwareto disableall interrupts except
the TRAP software interrupt. Thisbitis clearedby
software. Interrupts are enabled. Interrupts are disabled.
Thisbitis controlledby the RIM, SIM and IRETin-
structions andis testedby the JRM and JRNMin-
structions.
Note: Interrupts requested whileIis set are
latched and can be processed whenIis cleared. defaultan interrupt routineis not interruptable
because theIbitis setby hardware when you en-
terit and resetby the IRET instructionat the endof
the interrupt routine.If theIbitis clearedby soft-
warein the interrupt routine, pending interrupts are
serviced regardlessof the priority levelof the cur-
rent interrupt routine.
Bit2=N Negative.
Thisbitis set and clearedby hardware.Itis repre-
sentativeof the result signof the last arithmetic,
logicalor data manipulation.Itisa copyof the7th
bitof the result. The resultof the last operationis positiveor null. The resultof the last operationis negative
(i.e. the most significantbitisa logic1).
Thisbitis accessedby the JRMI and JRPL instruc-
tions.
Bit1=Z Zero.
Thisbitis set and clearedby hardware. Thisbitin-
dicates that the resultof the last arithmetic, logical data manipulationis zero. The resultof the last operationis different from
zero. The resultof the last operationis zero.
Thisbitis accessedby the JREQ and JRNE test
instructions.
Bit0=C Carry/borrow.
Thisbitis set and clearedby hardware and soft-
ware.It indicatesan overfloworan underflow has
occurred during the last arithmetic operation. No overflowor underflow has occurred. An overflowor underflow has occurred.
Thisbitis drivenby the SCF and RCF instructions
and testedby the JRC and JRNC instructions.Itis
also affectedby the “bit test and branch”, shift and
rotate instructions.
111 H I N Z C
16/100
ST72E311 ST72T311
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01FFh
The Stack Pointerisa 16-bit register whichisal-
ways pointingto the next free locationin the stack.is then decremented after data has been pushed
onto the stack and incremented before datais
popped from the stack (see Figure9).
Since the stackis 256 bytes deep, the 8th most
significant bits are forced by hardware. Following MCU Reset,or aftera Reset Stack Pointerin-
struction (RSP), the Stack Pointer containsits re-
set value (the SP7to SP0 bits are set) whichis the
stack higher address.
The least significant byteof the Stack Pointer
(called S) can be directly accessed bya LD in-
struction.
Note: When the lower limitis exceeded, the Stack
Pointer wraps aroundto the stack upper limit, with-
out indicating the stack overflow. The previously
stored informationis then overwritten and there-
fore lost. The stack also wrapsin caseof anunder-
flow.
The stackis usedto save the return address dur-
inga subroutine call and the CPU context during interrupt. The user may also directly manipulate
the stackby meansof the PUSH and POP instruc-
tions.In the caseofan interrupt, the PCLis stored the first location pointedtoby the SP. Then the
other registers are storedin the next locationsas
shownin Figure9. Whenan interruptis received, the SPis decre-
mented and the contextis pushedon the stack. On return from interrupt, the SPis incremented
and the contextis popped from the stack. subroutine call occupies two locations andanin-
terrupt five locationsin the stack area.
Figure9. Stack Manipulation Example 8 00000 1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
PCH
PCL
PCH
PCL
PCL
PCH
PCH
PCL
PCL
PCH
PCH
PCL
PCL
PCH
PCH
PCL
CALL
Subroutine
Interrupt
Event
PUSHY POPY IRET RET RSP 01FFh 0100h
Stack Higher Address= 01FFh
Stack Lower Address= 0100h
17/100
ST72E311 ST72T311 CLOCKS, RESET, INTERRUPTS& POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
The MCU accepts eithera crystalor ceramic reso-
nator,oran external clock signalto drive the inter-
nal oscillator. The internal clock(f CPU)is derived
from the external oscillator frequency(f OSC). The
external Oscillator clockis first divided by2, and additional division factorof2,4,8,or16 canbe
applied,in Slow Mode,to reduce the frequencyof
the fCPU; this clock signalis also routedto the on-
chip peripherals. The CPU clock signal consistsof square wave witha duty cycleof 50%.
The internal oscillatoris designedto operate with AT-cut parallel resonant quartz crystal resona-
torin the frequency range specified for fosc.The
circuit shownin Figure11is recommended when
usinga crystal, and Table5 lists the recommend- capacitance and feedback resistance values.
The crystal and associated components shouldbe
mounted as closeas possibleto the input pinsin
orderto minimize output distortion and start-up
stabilisation time.
Use of an external CMOS oscillatoris recom-
mended when crystals outside the specified fre-
quency ranges aretobe used.
3.1.2 External Clock externalclock maybe appliedto the OSCINin-
put with the OSCOUT pin not connected, as
shown on Figure 10.
Table5 Recommended Values for 16 MHz
Crystal Resonator(C0< 7pF) SMAX: Parasitic series resistanceof the quartz
crystal (upper limit).0: Parasitic shunt capacitanceof the quartz crys-
tal (upper limit 7pF). OSCOUT,C OSCIN: Maximum total capacitanceon
pins OSCIN and OSCOUT (the value includes the
external capacitance tiedto the pin plus the para-
sitic capacitanceof the board andof the device).
Figure 10. External Clock Source Connections
Figure 11. Crystal/CeramicResonator
Figure 12. Clock Prescaler Block Diagram
RSMAX 40Ω 60Ω 150Ω
COSCIN 56pF 47pF 22pF
COSCOUT 56pF 47pF 22pF
OSCIN OSCOUT
EXTERNAL
CLOCK
OSCIN OSCOUT
COSCIN COSCOUT
OSCIN OSCOUT
COSCIN COSCOUT %2,4,8,16
fCPU CPUand
Peripherals
18/100
ST72E311 ST72T311
3.2 RESET
3.2.1 Introduction
There are four sourcesof Reset: RESET pin (external source) Power-On Reset (Internal source) WATCHDOG (Internal Source) Low Voltage Detection Reset (internal source)
The Reset Service Routine vectoris locatedat ad-
dress FFFEh-FFFFh.
3.2.2 External Reset
The RESET pinis bothan input andan open-drain
output with integrated pull-up resistor. When one the internal Reset sourcesis active, the Reset
pinis driven lowfora durationof tRESETto reset
the whole application.
3.2.3 Reset Operation
The durationof the Reset stateisa minimumof
4096 internal CPU Clock cycles. During the Reset
state,all I/Os take their reset value. Reset signal originating froman external source
must havea durationofat least tPULSEin orderto recognised. This detectionis asynchronous
and therefore the MCU can enter Reset state even Halt mode. the endof the Reset cycle, the MCU may be
heldin the Reset stateby an External Reset sig-
nal. The RESET pin may thusbe usedto ensureDD has risentoa point where the MCU can oper-
ate correctly before the user programis run. Fol-
lowinga Reset event,or after exiting Halt mode,a
4096 CPU Clock cycle delay periodis initiatedin
orderto allow the oscillatorto stabilise andto en-
sure that recovery has taken place from the Reset
state. the high state, the RESET pinis connected in-
ternallytoa pull-up resistor (RON). This resistor
canbe pulled lowby external circuitryto reset the
device.
The RESET pinis an asynchronous signal which
playsa major rolein EMS performance.Ina noisy
environment,itis recommendedto use the exter-
nal connections shownin Figure6.
Figure 13. Reset Block Diagram
INTERNAL
RESET
WATCHDOG RESET
OSCILLATOR
SIGNAL
COUNTER
RESET ST7
RESET
POWER-ON RESET
VDD
LOW VOLTAGE DETECTOR RESET
RON
19/100
ST72E311 ST72T311
RESET (Cont’d)
3.2.4 Low Voltage Detector Reset
The on-chip Low Voltage Detector (LVD) gener-
atesa static reset when the supply voltageis be-
lowa reference value. The LVD functions both
during power-onas wellas when the power supply
drops (brown-out). The reference value fora volt-
age dropis lower than the reference valuefor pow-
er-onin orderto avoida parasitic reset when the
MCU starts running and sinks currenton the sup-
ply (hysteresis).
The LVD Reset circuitry generatesa reset whenDDis below: LVDUP whenVDDis rising
VLVDDOWN when VDDis falling
Provided the minimunVDD value (guaranteed for
the oscillator frequency)is above VLVDDOWN, the
MCU can onlybein two modes: under full software controlorin static safe reset this condition, secure operationis always en-
sured for the application without the need for ex-
ternal reset hardware.
Duringa Low Voltage Detector Reset, the RESET
pinis held low, thus permitting the MCUto reset
other devices. noisy environments, the power supply may drop
for short periods and cause the Low Voltage De-
tectorto generatea Reset too frequently.In such
cases,itis recommendedto use devices without
the LVD Reset option andto relyon the watchdog
functionto detect application runaway conditions.
Figure14. LowVoltage Detector ResetFunction
Figure 15. Low Voltage Detector Reset Signal
Note: See electrical characteristics for valuesof LVDUP andV LVDDOWN
Figure 16. Temporization timing diagram afteran internal Reset
LOW VOLTAGE
DETECTOR RESET
VDD
FROM
WATCHDOG
RESET
RESET
RESET
VDD
VLVDUP
VLVDDOWN
VDD
Addresses $FFFE
Temporization (4096 CPU clock cycles)
VLVDUP
20/100
ST72E311 ST72T311
3.3 INTERRUPTS
The ST7 core maybe interruptedby oneof two dif-
ferent methods: maskable hardware interruptsas
listedin the Interrupt Mapping Table anda non-
maskable software interrupt (TRAP). The Interrupt
processing flowchartis shownin Figure 17.
The maskable interrupts mustbe enabled clearing
theIbitin ordertobe serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
Whenan interrupt hastobe serviced: Normal processingis suspendedat the endof
the current instruction execution. The PC,X,A and CC registers are saved onto
the stack. TheIbitof the CC registeris setto prevent addi-
tional interrupts. ThePCis then loaded with the interrupt vectorof
the interruptto service and the first instructionof
the interrupt service routineis fetched (referto
the Interrupt Mapping Tablefor vector address-
es).
The interrupt service routine should finish with the
IRET instruction which causes the contentsof the
saved registerstobe recovered from the stack.
Note: Asa consequenceof the IRET instruction,
theIbit willbe cleared and the main program will
resume.
Priority management default,a servicing interrupt can not be inter-
rupted because theIbitis setby hardware enter-
ingin interrupt routine. the case several interrupts are simultaneously
pending, an hardware priority defines which one
willbe serviced first (see the Interrupt Mapping Ta-
ble).
Non Maskable Software Interrupts
This interruptis entered when the TRAP instruc-
tionis executed regardlessof the stateof theI bit. will be serviced accordingto the flowchart on
Figure 17.
Interrupts and Low power mode
All interrupts allow the processorto leave the Wait
low power mode. Only external and specific men-
tioned interrupts allow the processorto leave the
Halt low power mode (referto the “Exit from HALT“
columnin the Interrupt Mapping Table).
External Interrupts
External interrupt vectors canbe loadedin the PC
registerif the corresponding external interrupt oc-
curred andif theIbitis cleared. These interrupts
allow the processorto leave the Halt low power
mode.
The external interrupt polarityis selected through
the miscellaneous registeror interrupt register(if
available).
External interrupt triggeredon edge willbe latched
and the interrupt request automatically cleared
upon entering the interrupt service routine. several input pins, connectedto the same inter-
rupt vector, are configuredas interrupts, their sig-
nals are logically ANDed before entering the edge/
level detection block.
Warning: The typeof sensitivity definedin the
Miscellaneousor Interrupt register(if available)
appliesto theEI source.In caseof an ANDed
source (as describedon the I/O ports section),a
low levelonan I/O pin configuredas input with in-
terrupt, masks the interrupt request evenin case rising-edge sensitivity.
Peripheral Interrupts
Different peripheral interrupt flagsin the status
register are ableto causean interrupt when they
are activeif both: TheIbitof the CC registeris cleared. The corresponding enablebitis setin the control
register. anyof these two conditionsis false, the interrupt latched and thus remains pending.
Clearingan interrupt requestis done by: writing “0”to the correspondingbitin the status
registeroran accessto the status register while the flagis
set followedbya reador writeof an associated
register.
Note: the clearing sequence resets the internal
latch.A pending interrupt (i.e. waitingfor being en-
abled) will thereforebe lostif the clear sequenceis
executed.
21/100
ST72E311 ST72T311
INTERRUPTS (Cont’d)
Figure 17. Interrupt Processing Flowchart
BITI SET
IRET
FROM RESET
LOADPC FROM INTERRUPT VECTOR
STACK PC,X,A,CC
SETIBIT
FETCH NEXT INSTRUCTION
EXECUTE INSTRUCTION
THIS CLEARS IBITBY DEFAULT
RESTORE PC,X, A,CC FROM STACK
BITI SET
22/100
ST72E311 ST72T311
Table6. Interrupt Mapping
Source
Block Description Register
Label Flag
Exit
from
HALT
Vector
Address
Priority
Order
RESET Reset N/A N/A yes FFFEh-FFFFh
TRAP Software N/A N/A no FFFCh-FFFDh
NOT USED FFFAh-FFFBh
NOT USED FFF8h-FFF9h
EI0 Ext. Interrupt (Ports PA0:PA3) N/A N/A
yes
FFF6h-FFF7h
EI1 Ext. Interrupt (Ports PF0:PF2) N/A N/A FFF4h-FFF5h
EI2 Ext. Interrupt (Ports PB0:PB3) N/A N/A FFF2h-FFF3h
EI3 Ext. Interrupt (Ports PB4:PB7) N/A N/A FFF0h-FFF1h
NOT USED FFEEh-FFEFh
SPI Transfer Complete SPISR SPIF
FFECh-FFEDhMode Fault MODF
TIMERA
Input Capture1
TASR
ICF1_A
FFEAh-FFEBh
Output Compare1 OCF1_A
Input Capture2 ICF2_A
Output Compare2 OCF2_A
Timer Overflow TOF_A
TIMERB
Input Capture1
TBSR
ICF1_B
FFE8h-FFE9h
Output Compare1 OCF1_B
Input Capture2 ICF2_B
Output Compare2 OCF2_B
Timer Overflow TOF_B
SCI
Transmit Buffer Empty
SCISR
TDRE
FFE6h-FFE7h
Transmit Complete TC
Receive BufferFull RDRF
Idle Line Detect IDLE
Overrun OR
NOT USED FFE4h-FFE5h
NOT USED FFE2h-FFE3h
NOT USED FFE0h-FFE1h
Highest
Priority
Priority
Lowest
23/100
ST72E311 ST72T311
3.4 POWER SAVING MODES
3.4.1 Introduction
There are three Power Saving modes. Slow Mode selectedby setting the relevant bitsin the Mis-
cellaneous register. Wait and Halt modes maybe
entered using the WFI and HALT instructions.
3.4.2 Slow Mode Slow mode, the oscillator frequency can bedi-
vided bya value definedin the Miscellaneous
Register. The CPU and peripherals are clockedat
this lower frequency. Slow modeis usedto reduce
power consumption, and enables the userto adapt
clock frequencyto available supply voltage.
3.4.3 Wait Mode
Wait mode places the MCUina low power con-
sumption modeby stopping the CPU.All peripher-
als remain active. During Wait mode, theIbit (CC
Register)is cleared,soasto enableall interrupts.
All other registers and memory remain unchanged.
The MCU will remainin Wait mode untilan Inter-
ruptor Reset occurs, whereupon the Program
Counter branchesto the starting addressof theIn-
terruptor Reset Service Routine.
The MCU will remainin Wait mode untila Resetor Interrupt occurs, causingitto wake up.
Referto Figure18 below.
Figure 18. WAIT Flow Chart
WFI INSTRUCTION
RESET
INTERRUPT Y
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
CLEARED
OFF
Note: Before servicingan interrupt,the CC registeris
pushedon the stack. The I-Bitisset during the inter-
rupt routine and cleared when the CC registeris
popped.
4096 CPU CLOCK
FETCH RESET VECTOR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
SET
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
SET
24/100
ST72E311 ST72T311
POWER SAVING MODES (Cont’d)
3.4.4 Halt Mode
The Halt modeis the MCU lowest power con-
sumption mode. The Halt modeis enteredby exe-
cuting the HALT instruction. The internal oscillator then turned off, causingall internal processingto stopped, including the operationof the on-chip
peripherals. The Halt mode cannot be used when
the watchdogis enabled,if the HALT instructionis
executed while the watchdog systemis enabled,a
watchdog resetis generated thus resetting the en-
tire MCU.
When entering Halt mode, theIbitin the CC Reg-
isteris clearedsoasto enable External Interrupts.an interrupt occurs, the CPU becomes active.
The MCU canexit the Halt mode upon receptionof interruptora reset. Referto the Interrupt Map-
ping Table. The oscillatoris then turned on anda
stabilization timeis provided before releasing CPU
operation. Thestabilization timeis 4096 CPUclock
cycles.
After the startup delay, the CPU continues oper-
ation byservicing the interrupt which wakesitupor fetching the reset vectorifa reset wakesit up.
Figure 19. HALT Flow Chart
EXTERNAL
INTERRUPT1)
RESET
HALT INSTRUCTION
4096 CPU CLOCK
FETCH RESET VECTOR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK2)
I-BIT
OFF
SET
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
OFF
OFF
CLEARED
OFF
WDG
ENABLED
RESET
WATCHDOGor some specific interrupts
Note: Before servicingan interrupt, the CC registeris
pushedon the stack. The I-Bitisset during the inter-
rupt routine and cleared when the CC registeris
popped.
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
SETif reset PERIPH. CLOCK= ON;if interrupt
PERIPH. CLOCK= OFF
25/100
ST72E311 ST72T311
3.5 MISCELLANEOUS REGISTER
The Miscellaneous register allowsto select the
SLOW operating mode, the polarityof externalin-
terrupt requests andto output the internal clock.
Register Address: 0020h — Read/ Write
Reset Value: 0000 0000 (00h)
Bit 7:6= PEI[3:2] External Interrupt EI3 and EI2
Polarity Options.
These bits are set and clearedby software. They
determine which eventon EI2 and EI3 causes the
external interrupt accordingto Table7.
Table7. EI2 and EI3 External Interrupt Polarity
Options
Note: Any modificationof oneof these two bits re-
sets the interrupt request relatedto this interrupt
vector.
Bit5= MCO Main Clock Out
Thisbitis set and clearedby software. When set,it
enables the outputof the Internal Clock on the
PPF0 I/O port.- PF0isa general purpose I/O port.- MCO alternate function (fCPUis outputon PF0
pin).
Bit 4:3= PEI[1:0] External Interrupt EI1 and EI0
Polarity Options.
These bits are set and clearedby software. They
determine which eventon EI0 and EI1 causes the
external interrupt accordingto Table8.
Table8. EI0 and EI1 External Interrupt Polarity
Options
Note: Any modificationof oneof these two bitsre-
sets the interrupt request relatedto this interrupt
vector.
Bit 2:1= PSM[1:0] Prescaler for Slow Mode
These bits are set and cleared by soft-
ware. They determine the CPU clock
when the SMSbitis set accordingto the
following table.
Table9.f CPU Valuein Slow Mode
Bit0= SMS Slow Mode Select
Thisbitis set and clearedby software. Normal Mode-f CPU=f OSC/2
(Reset state) Slow Mode- thef CPU valueis determinedby the
PSM[1:0] bits.
PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS
MODE PEI3 PEI2
Falling edge and low level
(Reset state) 00
Falling edge only 1 0
Rising edge only 0 1
Rising and falling edge 1 1
MODE PEI1 PEI0
Falling edge and low level
(Reset state) 00
Falling edge only 1 0
Rising edge only 0 1
Rising and falling edge 1 1
fCPU Value PSM1 PSM0
fOSC/4 0 0
fOSC /16 0 1
fOSC/8 1 0
fOSC /32 1 1
26/100
ST72E311 ST72T311 ON-CHIP PERIPHERALS
4.1 I/O PORTS
4.1.1 Introduction
The I/O ports offer different functional modes: transferof data through digital inputs and outputs
and for specific pins: analog signal input (ADC) alternate signal input/output for the on-chip pe-
ripherals. external interrupt generation I/O portis composedofupto8 pins. Each pin
canbe programmed independentlyas digital input
(withor without interrupt generation)or digital out-
put.
4.1.2 Functional Description
Each portis associatedto2 main registers: Data Register (DR) Data Direction Register (DDR)
and someof themtoan optional register: Option Register (OR)
Each I/O pin maybe programmed using the corre-
sponding register bitsin DDR and OR registers:bit correspondingto pinXof the port. The same cor-
respondenceis used for the DR register.
The following description takes into account the register,for specific ports whichdo not provide
this register referto the I/O Port Implementation
Section 4.1.3. The generic I/O block diagramis
shown on Figure 21.
4.1.2.1 Input Modes
The input configurationis selectedby clearing the
corresponding DDR register bit. this case, reading the DR register returns the
digital value appliedto the external I/O pin.
Different input modes canbe selectedby software
through the OR register.
Notes:All the inputs are triggeredbya Schmitt trigger. When switching from input mode to output
mode, the DR register should be written firstto
output the correct valueas soonas the portis con-
figuredasan output.
Interrupt function
When an I/Ois configuredin Input with Interrupt, event on this I/O can generatean external In-
terrupt requestto the CPU. The interrupt polarityis
given independently accordingto the description
mentionedin the Miscellaneous registerorin the
interrupt register (where available).
Each pin can independently generatean Interrupt
request.
Each external interrupt vectoris linkedtoa dedi-
cated groupof I/O port pins (see Interrupts sec-
tion).If several input pins are configuredas inputs the same interrupt vector, their signals are logi-
cally ANDed before entering the edge/level detec-
tion block. For this reasonif oneof the interrupt
pinsis tied low,it masks the other ones.
4.1.2.2 Output Mode
The pinis configuredin output modeby setting the
corresponding DDR register bit. this mode, writing “0”or “1”to the DR register
applies this digital valueto the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Note:In this mode, the interrupt functionis disa-
bled.
4.1.2.3 Digital Alternate Function
Whenan on-chip peripheralis configuredto usea
pin, the alternate functionis automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signalis
coming froman on-chip peripheral, the I/O pinis
automatically configuredin output mode (push-pull open drain accordingto the peripheral).
When the signalis goingtoan on-chip peripheral,
the I/O pin hastobe configuredin input mode.In
this case, the pin’s stateis also digitally readable addressing the DR register.
Notes: Input pull-up configuration can cause an unex-
pected valueat the inputof the alternate peripher- input. When the on-chip peripheral usesa pinas input
and output, this pin mustbe configuredasan input
(DDR=0).
Warning: The alternate function must not be acti-
vatedas longas the pinis configuredas input with
interrupt,in orderto avoid generating spurious in-
terrupts.
27/100
ST72E311 ST72T311
I/O PORTS (Cont’d)
4.1.2.4 Analog Alternate Function
When the pinis usedasan ADC input the I/O must configuredas input, floating. The analog multi-
plexer (controlledby the ADC registers) switches
the analog voltage present on the selected pinto
the common analog rail whichis connectedto the
ADC input.is recommended notto change the voltage level loading on any port pin while conversionisin
progress. Furthermoreitis recommended notto
have clocking pins located closetoa selected an-
alog pin.
Warning: The analog input voltage level mustbe
within the limits statedin the Absolute Maximum
Ratings.
4.1.3 I/O Port Implementation
The hardware implementationon each I/O port de-
pendson the settingsin the DDR and OR registers
and specific featureof the I/O port suchas ADCIn-
put (see Figure 21)or true open drain. Switching
these I/O ports from one stateto another should doneina sequence that prevents unwanted
side effects. Recommended safe transitions areil-
lustratedin Figure 20. Other transitions are poten-
tially risky and should be avoided, since they are
likelyto present unwanted side-effects such as
spurious interrupt generation.
Figure 20. Recommended I/O State Transition Diagram
with interrupt
INPUT OUTPUT interrupt
INPUT
push-pullopen-drain
OUTPUT
28/100
ST72E311 ST72T311
I/O PORTS (Cont’d)
Figure 21. I/O Block Diagram
Table 10. Port Mode Configuration
Legend:- present, not activated- present and activated
Notes:No OR Registeron some ports (see register map). ADC Switchon ports with analog alternate functions.
DDR
LATCH
LATCH
DATA
BUS SEL
DDR SEL
VDD
PAD
ANALOG
SWITCH
ANALOG ENABLE
(ADC)X
ALTERNATE
ALTERNATE
ALTERNATE ENABLE
COMMON
ANALOG
RAIL
ALTERNATEUX
ALTERNATE INPUT
PULL-UP
OUTPUT
P-BUFFER
(SEE TABLE BELOW)
N-BUFFER
LATCH SEL
FROM
OTHER
BITS
EXTERNAL
PULL-UP
CONDITION
ENABLE
ENABLE
GND
(SEE TABLE BELOW)
(SEE NOTE BELOW)
CMOS
SCHMITT TRIGGER
SOURCE (EIx)
INTERRUPT
POLARITY
SEL
GND
VDD
DIODE
(SEE TABLEBELOW)
Configuration Mode Pull-up P-buffer VDD Diode
Floating 0 0 1
Pull-up 1 0 1
Push-pull 0 1 1
True Open Drain not present not present not present
Open Drain (logic level) 0 0 1
29/100
ST72E311 ST72T311
I/O PORTS (Cont’d)
Table 11. Port Configuration
Notes: ST72T311N only For OTP/EPROM version, when OR=0: floating& when OR=1: reserved For OTP/EPROM version, when OR=0: open-drain, high sink capability& when OR=1: reserved Reset state (The bits correspondingto unavailable pins areforcedto1by hardware, this affects the reset status value).
Warning:All bitsof the DDR register which correspondto unconnected I/Os mustbe leftat their reset val-
ue. They must notbe modifiedby the user otherwisea spurious interrupt maybe generated.
Port Pin name Input (DDR=0) Output (DDR=1)=0 OR=1 OR=0 OR=1
PortA
PA0:PA21) floating* pull-up with interrupt open-drain push-pull
PA3 floating* pull-up with interrupt open-drain push-pull
PA4:PA7 floating* true open drain, high sink capability
PortB
PB0:PB4 floating* pull-up with interrupt open-drain push-pull
PB5:PB71) floating* pull-up with interrupt open-drain push-pull
PortC PC0:PC7 floating* pull-up open-drain push-pull
PortD
PD0:PD5 floating* pull-up open-drain push-pull
PD6:PD71) floating* pull-up open-drain push-pull
PortE
PE0:PE1 floating* pull-up open-drain push-pull
PE4:PE71) floating*2) true open drain,
high sink capability3)
PortF
PF0:PF2 floating* pull-up with interrupt open-drain push-pull
PF4, PF6, PF7 floating* pull-up open-drain push-pull
30/100
ST72E311 ST72T311
I/O PORTS (Cont’d)
4.1.4 Register Description
4.1.4.1 Data registers
PortA Data Register (PADR)
PortB Data Register (PBDR)
PortC Data Register (PCDR)
PortD Data Register (PDDR)
PortE Data Register (PEDR)
PortF Data Register (PFDR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0= D7-D0 Data Register8 bits.
The DR register hasa specific behaviour accord-
ingto the selected input/output configuration. Writ-
ing the DR registeris always takenin account
evenif the pinis configuredas an input. Reading
the DR register returns either the DR register latch
content (pin configuredas output)or the digital val- appliedto the I/O pin (pin configuredas input).
4.1.4.2 Data direction registers
PortA Data Direction Register (PADDR)
PortB Data Direction Register (PBDDR)
PortC Data Direction Register (PCDDR)
PortD Data Direction Register (PDDDR)
PortE Data Direction Register (PEDDR)
PortF Data Direction Register (PFDDR)
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
Bit 7:0= DD7-DD0 Data Direction Register8 bits.
The DDR register gives the input/output direction
configurationof the pins. Each bitsis set and
clearedby software. Input mode Output mode
4.1.4.3 Option registers
PortA Option Register (PAOR)
PortB Option Register (PBOR)
PortC Option Register (PBOR)
PortD Option Register (PBOR)
PortE Option Register (PBOR)
PortF Option Register (PFOR)
Read/Write
Reset Value: see Register Memory Map Table4
Bit 7:0= O7-O0 Option Register8 bits.
The OR register allowto distinguishin input mode the interrupt capabilityor the floating configura-
tionis selected. output modeit select push-pullor open-drain
capability.
Eachbitis set and clearedby software.
Input mode: floating input input pull-up with interrupt
Output mode: open-drain configuration push-pull configuration D6 D5 D4 D3 D2 D1 D0
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 O6 O5 O4 O3 O2 O1 O0
31/100
ST72E311 ST72T311
I/O PORTS (Cont’d)
Table 12. I/O Port Register Map
Address
(Hex.)
Register
Label 765 4 321 0
0000h PADR D7 D6 D5 D4 D3 D2 D1 D0
0001h PADDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
0002h PAOR O7 O6 O5 O4 O3 O2 O1 O0
0004h PCDR D7 D6 D5 D4 D3 D2 D1 D0
0005h PCDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
0006h PCOR O7 O6 O5 O4 O3 O2 O1 O0
0008h PBDR D7 D6 D5 D4 D3 D2 D1 D0
0009h PBDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
000Ah PBOR O7 O6 O5 O4 O3 O2 O1 O0
000Ch PEDR D7 D6 D5 D4 D3 D2 D1 D0
000Dh PEDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
000Eh PEOR O7 O6 O5 O4 O3 O2 O1 O0
0010h PDDR D7 D6 D5 D4 D3 D2 D1 D0
0011h PDDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
0012h PDOR O7 O6 O5 O4 O3 O2 O1 O0
0014h PFDR D7 D6 D5 D4 D3 D2 D1 D0
0015h PFDDR DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
0016h PFOR O7 O6 O5 O4 O3 O2 O1 O0
32/100
ST72E311 ST72T311
4.2 WATCHDOG TIMER (WDG)
4.2.1 Introduction
The Watchdog timeris usedto detect the occur-
renceofa software fault, usually generatedby ex-
ternal interferenceorby unforeseen logical condi-
tions, which causes the application programto
abandonits normal sequence. The Watchdog cir-
cuit generatesan MCU reset on expiryofa pro-
grammed time period, unless the program refresh- the counter’s contents before the T6 bit be-
comes cleared.
4.2.2 Main Features Programmable timer (64 incrementsof 12288
CPU cycles) Programmable reset Reset (if watchdog activated) aftera HALT
instructionor when the T6bit reaches zero Hardware Watchdog selectableby option byte Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)
4.2.3 Functional Description
The counter value storedin the CR register (bits
T[6:0]),is decremented every 12,288 machine cy-
cles, and the lengthof the timeout period can be
programmedby the userin64 increments. the watchdogis activated (the WDGAbitis set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40hto 3Fh (T6 becomes cleared),it initiates reset cycle pulling low the reset pin for typically
500ns.
Figure 22. Watchdog Block Diagram
RESET
WDGA
7-BIT DOWNCOUNTER CPU T0
CLOCK DIVIDER
WATCHDOG CONTROL REGISTER (CR)
÷12288T2T3T4T5
33/100
ST72E311 ST72T311
WATCHDOG TIMER (Cont’d)
The application program must writein the CR reg-
isterat regular intervals during normal operationto
prevent an MCU reset. The valuetobe storedin
the CR register must be between FFh and C0h
(see Table 13): The WDGAbitis set (watchdog enabled) TheT6bitis setto prevent generatingan imme-
diate reset The T[5:0] bits contain the numberof increments
which represents the time delay before the
watchdog producesa reset.
Table 13.Watchdog Timing(f CPU=8 MHz)
Notes: Followinga reset, the watchdogis disa-
bled. Once activatedit cannotbe disabled, excepta reset.
TheT6bit canbe usedto generatea software re-
set (the WDGAbitis set and theT6bitis cleared). the watchdogis activated, the HALT instruction
will generatea Reset.
4.2.4 Hardware Watchdog Option Hardware WatchdogIs selectedby option byte,
the watchdogis always active and the WDGAbitin
the CRis not used.
Referto the device-specific Option Byte descrip-
tion.
4.2.5 Low Power Modes
4.2.6 Interrupts
None.
4.2.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit7= WDGA Activation bit.
This bitis set by software and only cleared by
hardware aftera reset. When WDGA=1, the
watchdog can generatea reset. Watchdog disabled Watchdog enabled
Note: Thisbitis not usedif the hardware watch-
dog optionis enabledby option byte.
Bit 6:0= T[6:0] 7-bit timer (MSBto LSB).
These bits contain the decremented value.A reset produced whenit rolls over from 40hto 3Fh (T6
becomes cleared).
STATUS REGISTER (SR)
Read/Write
Reset Value*: 0000 0000 (00h)
Bit0= WDOGF Watchdog flag.
Thisbitis setbya watchdog reset and clearedby
softwareora power on/off reset. Thisbitis useful
for distinguishing power/on offor external reset
and watchdog reset. No Watchdog reset occurred Watchdog reset occurred Onlyby software and power on/off reset
Note: This registeris not usedin versions without
LVD Reset. Register
initial value
WDG timeout period
(ms)
Max FFh 98.304
Min C0h 1.536
Mode Description
WAIT No effecton Watchdog.
HALT
Immediate resetgenerationas soonas
the HALT instructionis executedif the
Watchdogis activated (WDGAbitis
set).
WDGA T6 T5 T4 T3 T2 T1 T0 - - - - - - WDOGF
34/100
ST72E311 ST72T311
Table 14. WDG Register Map
Address
(Hex.) Register Label 76543210 WDGCR
Reset Value
WDGA WDGSR
Reset Value
WDOGF
35/100
ST72E311 ST72T311
4.3 16-BIT TIMER
4.3.1 Introduction
The timer consistsofa 16-bit free-running counter
drivenbya programmable prescaler. maybe used fora varietyof purposes, including
pulse length measurementofupto two input sig-
nals (input capture)or generationofupto two out-
put waveforms (output compare and PWM).
Pulse lengths and waveform periods canbe mod-
ulated froma few microsecondsto several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
4.3.2 Main Features Programmable prescaler:fCPU dividedby2, 4or8. Overflow status flag and maskable interrupt External clock input (must beat least4 times
slower thanthe CPUclock speed) withthe choice active edge Output compare functions with2 dedicated 16-bit registers2 dedicated programmable signals2 dedicated status flags1 dedicated maskable interrupt Input capturefunctions with2 dedicated 16-bit registers2 dedicated active edge selection signals2 dedicated status flags1 dedicated maskable interrupt Pulse width modulation mode (PWM) One pulse mode 5 alternate functionson I/Oports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagramis shownin Figure 23.
*Note: Some external pins are not availableonall
devices. Referto the device pin out description.
When reading an input signal whichis not availa-
bleonan external pin, the value will alwaysbe ‘1’.
4.3.3 Functional Description
4.3.3.1 Counter
The principal blockof the Programmable Timeris 16-bit free running increasing counter andits as-
sociated 16-bit registers:
Counter Registers Counter High Register (CHR)is the most sig-
nificant byte (MSB). Counter Low Register (CLR)is the least sig-
nificant byte (LSB).
Alternate Counter Registers Alternate Counter High Register (ACHR)is the
most significant byte (MSB). Alternate Counter Low Register (ACLR)is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOFbit (overflow
flag), (see noteat the endof paragraph titled 16-bit
read sequence).
Writingin the CLR registeror ACLR register resets
the free running counterto the FFFCh value.
The timer clock dependson the clock control bits the CR2 register,as illustratedin Table 15. The
value in the counter register repeats every
131.072, 262.144or 524.288 internal processor-
clock cycles dependingon the CC1 and CC0 bits.
36/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
Figure 23. Timer Block Diagram
MCU-PERIPHERAL INTERFACE
COUNTER
ALTERNATE
REGISTER
OUTPUT
COMPARE
REGISTER
OUTPUT COMPARE EDGE DETECTOVERFLOW
DETECT
CIRCUIT
1/2
1/4
1/8
8-bit
buffer
ST7 INTERNAL BUS
LATCH1 OCMP1
ICAP1EXTCLK
fCPU
TIMER INTERRUPT
ICF2ICF1 000OCF2OCF1 TOF
PWMOC1E EXEDGIEDG2CC0CC1OC2E OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE
ICAP2
LATCH2 OCMP2 8 low high 16 16
CR1 CR2 8888
high low high high highlow low lowEXEDG
TIMER INTERNAL BUS
CIRCUIT1
EDGE DETECT
CIRCUIT2
CIRCUIT
OUTPUT
COMPARE
REGISTER
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
REGISTER
CC1 CC0 BIT
FREE RUNNING
COUNTER
37/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
16-bit read sequence: (from either the Counter
Registeror the Alternate Counter Register).
The user must read the MSB first, then the LSB
valueis buffered automatically.
This buffered value remains unchanged until the
16-bit read sequenceis completed, evenif the
user reads the MSB several times.
Aftera complete reading sequence,if only the
CLR registeror ACLR register are read, they re-
turn the LSBof the count valueat the timeof the
read.
Whatever the timer mode used (input capture, out-
put compare, one pulse modeor PWM mode)an
overflow occurs when the counter rolls over from
FFFFhto 0000h then: The TOFbitof the SR registeris set.A timer interruptis generatedif: TOIEbitof the CR1 registeris set andIbitof the CC registeris cleared. oneof these conditionsis false, the interrupt re-
mains pendingto be issued as soonas they are
both true.
Clearing the overflow interrupt requestis donein
two steps: Reading the SR register while the TOFbitis set.An access (reador write)to the CLR register.
Notes: The TOFbitis not clearedby accessesto
ACLR register. This feature allows simultaneous
useof the overflow function and readsof the free
running counterat random times (for example,to
measure elapsed time) without the riskof clearing
the TOFbit erroneously.
The timeris not affectedby WAIT mode. HALT mode, the counter stops counting until the
modeis exited. Counting then resumes from the
previous count (MCU awakenedbyan interrupt)or
from the reset count (MCU awakenedbya Reset).
4.3.3.2 External Clock
The external clock (where available)is selectedif
CC0=1 and CC1=1in CR2 register.
The statusof the EXEDGbit determines the type level transitionon the external clock pin EXT-
CLK that will trigger the free running counter.
The counteris synchronised with the falling edge the internal CPU clock. least four falling edgesof the CPU clock must
occur between two consecutive active edgesof
the external clock; thus the external clock frequen- must be less thana quarterof the CPU clock
frequency.
LSBis bufferedRead MSBAtt0
Read LSB
Returns the buffered
LSB valueatt0Att0 +Δt
Other
instructions
Beginningof the sequence
Sequence completed
38/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
Figure 24. Counter Timing Diagram, internal clock dividedby2
Figure 25. Counter Timing Diagram, internal clock dividedby4
Figure 26. Counter Timing Diagram, internal clock dividedby8
CPU CLOCK
FFFD FFFE FFFF 0000 0001 0002 0003
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
OVERFLOW FLAG TOF
FFFC FFFD 0000 0001
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
OVERFLOW FLAG TOF
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
OVERFLOW FLAG TOF
FFFC FFFD 0000
39/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture this section, the index,i, maybe1or2.
The two input capture 16-bit registers (IC1R and
IC2R) are usedto latch the valueof the free run-
ning counter aftera transition detected by the
ICAPi pin (see figure5).
ICi registerisa read-only register.
The active transitionis software programmable
through theIEDGibitof the Control Register (CRi).
Timing resolutionis one countof the free running
counter:(f CPU /(CC1.CC0)).
Procedure: use the input capture function select the follow-
ingin the CR2 register: Select the timer clock (CC1-CC0) (see Table
15). Select the edgeof the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
mustbe configuredas floating input).
And select the followingin the CR1 register: Set the ICIEbitto generatean interrupt afteran
input capture coming from both the ICAP1 pinor
the ICAP2 pin Select the edgeof the active transition on the
ICAP1 pin with theIEDG1 bit(the ICAP1pin must configuredas floating input).
Whenan input capture occurs: ICFibitis set. The ICiR register contains the valueof the free
running counter on the active transition on the
ICAPi pin (see Figure 28).A timer interruptis generatedif the ICIEbitis set
and theIbitis clearedin the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt requestis
donein two steps: Reading the SR register while the ICFibitis set. An access (reador write)to the ICiLR register.
Notes: After reading the ICiHR register, transferof
input capture datais inhibited until the ICiLR
registeris also read. The ICiR register always contains the free run-
ning counter value which correspondsto the
most recent input capture. The2 input capture functions can be used
together evenif the timer also uses the output
compare mode.In One pulse Mode and PWM mode only the
input capture2 canbe used. The alternate inputs (ICAP1& ICAP2) are
always directly connectedto the timer. So any
transitionson these pins activate the input cap-
ture process. Moreoverif oneof the ICAPi pinis configured an input and the second oneas an output, interrupt can be generatedif the user toggle
the output pin andif the ICIEbitis set. The TOFbit canbe used with interruptin order measure event that go beyond the timer
range (FFFFh). Byte LS Byte
ICiR ICiHR ICiLR
40/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
Figure 27. Input Capture Block Diagram
Figure 28. Input Capture Timing Diagram
ICIE
CC0CC116-BIT FREE RUNNING
COUNTER
IEDG1
(Control Register1) CR1
(Control Register2) CR2
ICF2ICF1 000
(Status Register)SR
IEDG2
ICAP1
ICAP2
EDGE DETECT
CIRCUIT2
16-BIT
IC1R RegisterIC2R Register
EDGE DETECT
CIRCUIT1
pin
pin
FF01 FF02 FF03
FF03
TIMER CLOCK
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
ICAPi REGISTER
Note: Active edgeis rising edge.
41/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare this section, the index,i, maybe1or2.
This function can be usedto control an output
waveformor indicating whena periodof time has
elapsed.
Whena matchis found between the Output Com-
pare register andthe free running counter, the out-
put compare function: Assigns pins witha programmable valueif the
OCIEbitis set Setsa flagin the status register Generatesan interruptif enabled
Two 16-bit registers Output Compare Register1
(OC1R) and Output Compare Register2 (OC2R)
contain the valuetobe comparedto the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affectedby the timer hardware.A reset event
changes the OCiR valueto 8000h.
Timing resolutionis one countof the free running
counter:(f CPU/(CC1.CC0)).
Procedure: use the output compare function, select the fol-
lowingin the CR2 register: Set the OCiEbitifan outputis needed then the
OCMPi pinis dedicatedto the output comparei
function. Select the timer clock (CC1-CC0) (see Table
15).
And select the followingin the CR1 register: Select theOLVLibitto appliedto theOCMPi pins
after the match occurs. Set the OCIEbitto generate an interruptifitis
needed.
Whena matchis found: OCFibitis set. The OCMPi pin takes OLVLibit value (OCMPi
pin latchis forced low during reset and stays low
until valid compares changeittoa high level).A timer interruptis generatedif the OCIEbitis
setin the CR2 register and theIbitis clearedin
the CC register (CC).
The OCiR register value requiredfora specific tim-
ing application canbe calculated using the follow-
ing formula:
Where: = Desired output compare period(in sec-
onds) CPU = Internal clock frequency
PRESC= Timer prescaler factor (2,4or8 de-
pending on CC1-CC0 bits, see Table
15)
Clearing the output compare interrupt requestis
done by: Reading the SR register while the OCFi bitis
set. An access (reador write)to the OCiLR register.
The following procedureis recommendedto pre-
vent the OCFibit from being set between the timeis read and the writeto the OCiR register: Writeto the OCiHR register (further compares
are inhibited). Read the SR register (first stepof the clearance the OCFi bit, which maybe already set). Writeto the OCiLR register (enables the output
compare function and clears the OCFi bit).
Notes: Aftera processor write cycleto the OCiHR reg-
ister, the output compare functionis inhibited
until the OCiLR registeris also written.If the OCiE bitis not set, the OCMPi pinisa
general I/O port and the OLVLi bit will not
appear whena matchis found butan interrupt
could be generatedif the OCIEbitis set. When the clockis divided by2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see Figure 30, on
page 43). This behaviouris the samein OPM PWM mode.
When the clockis dividedby4,8orin external
clock mode, OCFi and OCMPi are set while the
counter value equals the OCiR register value
plus1 (see Figure 31,on page 43). The output compare functions canbe used both
for generating external events on the OCMPi
pins evenif the input capture modeis also
used. The valuein the 16-bit OCiR register and the
OLVi bit should be changed after each suc-
cessful comparisonin orderto controlan output
waveformor establisha new elapsed timeout. Byte LS Byte
OCiROCiHR OCiLR OCiR= Δt*f CPU
PRESC
42/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
Figure 29. Output Compare Block Diagram
Figure 30. Output Compare Timing Diagram, Internal Clock Dividedby2
Figure 31. Output Compare Timing Diagram, Internal Clock Dividedby4
OUTPUT COMPARE
16-bit
CIRCUIT
OC1R Register BIT FREE RUNNING
COUNTER
OC1E CC0CC1OC2E
OLVL1OLVL2OCIE
(Control Register1) CR1
(Control Register2) CR200OCF2OCF1
(Status Register)SR
16-bit
16-bit
OCMP1
OCMP2
Latch
Latch
OC2R Register
Pin
Pin
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER
OUTPUT COMPARE REGISTER
OUTPUT COMPARE FLAG (OCFi)
OCMPi PIN (OLVLi=1)
2ED3
2ED0 2ED1 2ED2 2ED3 2ED42ECF
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER
OUTPUT COMPARE REGISTER
COMPARE REGISTER LATCH
OCFi AND OCMPi PIN (OLVLi=1)
2ED3
2ED0 2ED1 2ED2 2ED3 2ED42ECF
43/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
4.3.3.5 Forced Compare this sectioni may represent1or2.
The following bitsof the CR1 register are used:
When the FOLVibitis setby software, the OLVLi
bitis copiedto the OCMPi pin. The OLVibit hasto toggledin orderto toggle the OCMPi pin whenis enabled (OCiE bit=1). The OCFibitis then not
setby hardware, and thusno interrupt requestis
generated.
FOLVLi bits haveno effectin both one pulse mode
and PWM mode.
4.3.3.6 One Pulse Mode
One Pulse mode enables the generationofa
pulse whenan external event occurs. This modeis
selected via the OPMbitin the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure: use one pulse mode: Load the OC1R register with the value corre-
spondingto the lengthof the pulse (see the for-
mulain Section 4.3.3.7). Select the followingin the CR1 register: Using the OLVL1 bit, select the leveltobe ap-
pliedto the OCMP1 pin after the pulse. Using the OLVL2 bit, select the leveltobe ap-
pliedto the OCMP1 pin during the pulse. Select the edgeof the active transitionon the
ICAP1 pin with the IEDG1bit (the ICAP1 pin
mustbe configuredas floating input). Select the followingin the CR2 register: Set the OC1E bit, the OCMP1 pinis then ded-
icatedto the Output Compare1 function. Set the OPM bit. Select the timer clock CC1-CC0 (see Table
15).
Then,ona valid eventon the ICAP1 pin, the coun-
teris initializedto FFFCh and OLVL2bitis loaded the OCMP1 pin, the ICF1bitis set and the val- FFFDhis loadedin the IC1R register.
When the valueof the counteris equalto the value the contentsof the OC1R register, the OLVL1
bitis outputon the OCMP1 pin, (See Figure 32).
Notes: The OCF1bit cannotbe setby hardwarein one
pulse mode but the OCF2 bit can generate an
Output Compare interrupt. The ICF1bitis set whenan active edge occurs
and can generate an interruptif the ICIE bitis
set. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM modeis the only active one.If OLVL1=OLVL2a continuous signal will be
seenon the OCMP1 pin. The ICAP1 pin can notbe usedto perform input
capture. The ICAP2 pin canbe usedto perform
input capture (ICF2 canbe set and IC2R canbe
loaded) but the user must take care that the
counteris reset each timea valid edge occurs the ICAP1 pin and ICF1 can also generates
interruptif ICIEis set. When the one pulse modeis used OC1Ris
dedicatedto this mode. Nevertheless OC2R
and OCF2 can be usedto indicatea periodof
time has been elapsed but cannot generate an
output waveform because the level OLVL2is
dedicatedto the one pulse mode.
FOLV2 FOLV1 OLVL2 OLVL1 event occurs
Counter OC1R OCMP1= OLVL1
When
When ICAP1
One pulse mode cycle
OCMP1= OLVL2
Counteris reset FFFCh
ICF1bitis set
44/100
ST72E311 ST72T311
Figure 32. One Pulse Mode Timing Example
Figure 33. Pulse Width Modulation Mode Timing Example
COUNTER .... FFFC FFFD FFFE 2ED0 2ED1 2ED2
2ED3
FFFC FFFD
OLVL2 OLVL2OLVL1
ICAP1
OCMP1 compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
COUNTER 34E2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 34E2 FFFC
OLVL2 OLVL2OLVL1OCMP1
compare2 compare1 compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2=1
45/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
4.3.3.7 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generationofa signal witha frequency and pulse
length determined by the valueof the OC1R and
OC2R registers.
The pulse width modulation mode uses the com-
plete Output Compare1 function plus the OC2R
register, and so these functionality can not be
used when the PWM modeis activated.
Procedure use pulse width modulation mode: Load the OC2R register with the value corre-
spondingto the periodof the signal. Load the OC1R register with the value corre-
spondingto the lengthof the pulseif (OLVL1=0
and OLVL2=1). Select the followingin the CR1 register: Using the OLVL1 bit, select the leveltobe ap-
pliedto the OCMP1 pin aftera successful
comparison with OC1R register. Using the OLVL2 bit, select the leveltobe ap-
pliedto the OCMP1 pin aftera successful
comparison with OC2R register. Select the followingin the CR2 register: Set OC1E bit: the OCMP1 pinis then dedicat-to the output compare1 function. Set the PWM bit. Select the timer clock (CC1-CC0) (see Table
15). OLVL1=1 and OLVL2=0 the lengthof the posi-
tive pulseis the difference between the OC2R and
OC1R registers. OLVL1=OLVL2a continuous signal willbe seen the OCMP1 pin.
The OCiR register value requiredfora specific tim-
ing application canbe calculated using the follow-
ing formula:
Where: = Desired output compare period(in sec-
onds) CPU = Internal clock frequency
PRESC= Timer prescaler factor (2,4or8 de-
pending on CC1-CC0 bits, see Table
15)
The Output Compare2 event causes the counterbe initializedto FFFCh (See Figure 33).
Notes: Aftera write instructionto the OCiHR register,
the output compare functionis inhibited until the
OCiLR registeris also written.
Therefore the Input Capture1 functionis inhib-
ited but the Input Capture2is available. The OCF1 and OCF2 bits cannot be set by
hardwarein PWM mode therefore the Output
Compare interruptis inhibited. The ICF1bitis setby hardware when the coun-
ter reaches the OC2R value and can producea
timer interruptif the ICIEbitis set and theIbitis
cleared.In PWM mode the ICAP1 pin can notbe used perform input capture becauseitis discon-
nectedto the timer. The ICAP2 pin canbe used perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counteris reset each period and
ICF1 can also generates interruptif ICIEis set. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM modeis the only active one.
OCiR Value= t*f CPU
PRESC
Counter
OCMP1= OLVL2
Counter OC2R
OCMP1= OLVL1
When
When OC1R
Pulse Width Modulation cycle
Counteris reset FFFCh
ICF1bitis set
46/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
4.3.4 Low Power Modes
4.3.5 Interrupts
Note: The 16-bit Timer interrupt events are con-
nectedto the same interrupt vector (see Interrupts
chapter).
These events generate an interruptif the corre-
sponding Enable Control Bitis set and the I-bitin
the CC registeris reset (RIM instruction).
Mode Description
WAIT No effecton 16-bit Timer.
Timer interrupts cause the deviceto exit from WAIT mode.
HALT
16-bit Timer registers are frozen. HALT mode, the counter stops counting until Halt modeis exited. Counting resumes from the previous
count when the MCUis wokenupbyan interrupt with “exit from HALT mode” capabilityor fromthe counter
reset value when the MCUis wokenupbya RESET.an input capture event occursonthe ICAPi pin, the input capture detection circuitryis armed. Consequent-
ly, when the MCUis wokenupbyan interrupt with “exit from HALT mode” capability, the ICFibitis set, and
the counter value present when exiting from HALT modeis captured intothe ICiR register.
Interrupt Event Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Input Capture1 event/Counter resetin PWM mode ICF1 ICIE Yes No
Input Capture2 event ICF2 Yes No
Output Compare1 event (not availablein PWM mode) OCF1 OCIE Yes No
Output Compare2 event (not availablein PWM mode) OCF2 Yes No
Timer Overflow event TOF TOIE Yes No
47/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
4.3.6 Register Description
Each Timeris associated with three control and
status registers, and withsix pairsof data registers
(16-bit values) relatingto the two input captures,
the two output compares, the counter and theal-
ternate counter.
CONTROL REGISTER1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bit7= ICIE Input Capture Interrupt Enable. Interruptis inhibited.A timer interruptis generated whenever the
ICF1or ICF2bitof the SR registeris set.
Bit6= OCIE Output Compare Interrupt Enable. Interruptis inhibited.A timer interruptis generated whenever the
OCF1or OCF2bitof the SR registeris set.
Bit5= TOIE Timer Overflow Interrupt Enable. Interruptis inhibited.A timer interruptis enabled whenever the TOF
bitof the SR registeris set.
Bit4= FOLV2 Forced Output Compare2.
Thisbitis set and clearedby software. No effecton the OCMP2 pin. Forces the OLVL2 bit to be copied to the
OCMP2 pin,if the OC2E bitis set and evenif
thereisno successful comparison.
Bit3= FOLV1 Forced Output Compare1.
Thisbitis set and clearedby software. No effecton the OCMP1 pin. Forces OLVL1tobe copiedto the OCMP1 pin,if
the OC1Ebitis set and evenif thereisno suc-
cessful comparison.
Bit2= OLVL2 Output Level2.
Thisbitis copiedto the OCMP2 pin whenevera
successful comparison occurs with the OC2R reg-
ister and OCxEis setin the CR2 register. This val-is copiedto the OCMP1 pinin One Pulse Mode
and Pulse Width Modulation mode.
Bit1= IEDG1 Input Edge1.
Thisbit determines which typeof level transition the ICAP1 pin will trigger the capture.A falling edge triggers the capture.A rising edge triggers the capture.
Bit0= OLVL1 Output Level1.
The OLVL1bitis copiedto the OCMP1 pin when-
evera successful comparison occurs with the
OC1R register and the OC1Ebitis setin the CR2
register.
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
48/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
CONTROL REGISTER2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit7= OC1E Output Compare1 Pin Enable.
Thisbitis used onlyto output the signal from the
timer on the OCMP1 pin (OLV1in Output Com-
pare mode, both OLV1 and OLV2in PWM and
one-pulse mode). Whatever the valueof the OC1E
bit, the Output Compare1 functionof the timer re-
mains active. OCMP1 pin alternate function disabled (I/O pin
freefor general-purpose I/O). OCMP1 pin alternate function enabled.
Bit6= OC2E Output Compare2 Enable.
Thisbitis used onlyto output the signal from the
timer on the OCMP2 pin (OLV2in Output Com-
pare mode). Whatever the valueof the OC2E bit,
the Output Compare2 functionof the timer re-
mains active. OCMP2 pin alternate function disabled (I/O pin
freefor general-purpose I/O). OCMP2 pin alternate function enabled.
Bit5= OPM One Pulse Mode. One Pulse Modeis not active. One Pulse Mode isactive, the ICAP1 pin canbe
used totrigger one pulseon the OCMP1 pin;the
active transitionis givenby the IEDG1 bit. The
lengthof the generated pulse depends on the
contentsof the OC1R register.
Bit4= PWM Pulse Width Modulation. PWM modeis not active. PWM modeis active, the OCMP1 pin outputsa
programmable cyclic signal; the lengthof the
pulse depends on the valueof OC1R register;
the period dependson the valueof OC2R regis-
ter.
Bit3,2= CC1-CC0 Clock Control.
The valueof the timer clock dependson these bits:
Table 15. Clock Control Bits
Bit1= IEDG2 Input Edge2.
Thisbit determines which typeof level transition the ICAP2 pin will trigger the capture.A falling edge triggers the capture.A rising edge triggers the capture.
Bit0= EXEDG External Clock Edge.
Thisbit determines which typeof level transition the external clock pin EXTCLK will trigger the
free running counter.A falling edge triggers the free running counter.A rising edge triggers the free running counter.
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Timer Clock CC1 CC0
fCPU/4 0 0 CPU/2 0 1
fCPU/8 1 0
External Clock (where
available) 11
49/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
Bit7= ICF1 Input Capture Flag1. No input capture (reset value). An input capture has occurredor the counter
has reached the OC2R valuein PWM mode. To
clear this bit, first read the SR register, then read write the low byteof the IC1R (IC1LR) regis-
ter.
Bit6= OCF1 Output Compare Flag1. No match (reset value). The contentof the free running counter has
matched the contentof the OC1R register. To
clear this bit, first read the SR register, then read write the low byteof the OC1R (OC1LR) reg-
ister.
Bit5= TOF Timer Overflow. No timer overflow (reset value). The free running counter rolled over from FFFFh 0000h. To clear this bit, first read the SR reg-
ister, then reador write the low byteof the CR
(CLR) register.
Note: Readingor writing the ACLR register does
not clear TOF.
Bit4= ICF2 Input Capture Flag2. No input capture (reset value). An input capture has occurred.To clear this bit,
first read the SR register, then reador write the
low byteof the IC2R (IC2LR) register.
Bit3= OCF2 Output Compare Flag2. No match (reset value). The contentof the free running counter has
matched the contentof the OC2R register. To
clear this bit, first read the SR register, then read write the low byteof the OC2R (OC2LR) reg-
ister.
Bit 2-0= Reserved, forcedby hardwareto0.
INPUT CAPTURE1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
Thisisan 8-bit read only register that contains the
high partof the counter value (transferredby the
input capture1 event).
INPUT CAPTURE1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
Thisisan 8-bit read only register that contains the
low partof the counter value (transferredby thein-
put capture1 event).
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
Thisisan 8-bit register that contains the high part the valuetobe comparedto the CHR register.
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
Thisisan 8-bitregister that contains the low partof
the valuetobe comparedto the CLR register.
ICF1 OCF1 TOF ICF2 OCF2 0 0 0
MSB LSB
MSB LSB
MSB LSB
MSB LSB
50/100
ST72E311 ST72T311
16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
Thisisan 8-bit register that contains the high part the valuetobe comparedto the CHR register.
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
Thisisan 8-bit register that contains the low partof
the valuetobe comparedto the CLR register.
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
Thisisan 8-bit register that contains the high part the counter value.
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
Thisisan 8-bit register that contains the low partof
the countervalue.A writeto this register resets the
counter. An accessto this register after accessing
the SR register clears the TOF bit.
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
Thisisan 8-bit register that contains the high part the counter value.
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
Thisisan 8-bitregister that contains the low partof
the counter value.A writeto this register resets the
counter. An accessto this register afteran access SR register does not clear the TOFbitin SR
register.
INPUT CAPTURE2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
Thisisan 8-bit read only register that contains the
high partof the counter value (transferredby the
Input Capture2 event).
INPUT CAPTURE2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
Thisisan 8-bit read only register that contains the
low partof the counter value (transferredby theIn-
put Capture2 event).
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB
MSB LSB

Partno	Mfg	Dc	Qty	Available	Descript
ST72T311J4		N/a	960	avai	8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
ST72T311J2	ST	N/a	73	avai	8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
ST72T311J4	ST	N/a	554	avai	8-BIT MCU WITH 8 TO 16K OTP/EPROM, 384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS