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ST7554TQF7
V.90 USB WORLD MODEM CONTROLLER
ST7554V.90 USB WORLD MODEM CONTROLLER
January 1999
SUMMARY DATA
GENERAL. USB HOT PLUG & PLAY INTERFACE. DIRECT INTERFACE TO ST MAFE+DAA
CHIP-SET ST75951/ST952 FOR WORLD-
WIDE DAA DESIGN OR TO STLC7550 FOR
TRADITIONAL DAA DESIGN. WINDOWS 98 AND NT 5.0 SUPPORT. TAPI 2.0 COMPLIANT. SOFTWARE UPGRADABLE. MINIMUM SYSTEM REQUIREMENTS: . USB MOTHERBOARD, 166MHz PENTIUM
PROCESSOR WITH MMX TECHNOLOGY,
WINDOWS 98 AND 16MBYTES RAM OR
WINDOWS NT 5.0 AND 32MBYTES RAM
DEVICE FEATURES. SINGLE 9.216MHz CRYSTAL OSCILLATOR. INTEGRATED ANALOG AND DIGITAL 3.3V
REGULATORS. DEDICATED PINS FOR RING, OFF-HOOK,
CLID, LOOP CURRENT SENSE. 0.5μm CMOS PROCESS. TQFP48 (7 x 7 mm) PACKAGE
DATA MODEM / FAX / VOICE. V.90. V.34BIS, V.34, V.32BIS, V.32, V.22BIS, V.22, .23, V.21. BELL 103 AND BELL 212A.V .17, V.27TER, V.29, FAX CLASS 1 SUPPORT. V.42, V.42BIS, MNP 2, 3, 4, 5. V.80. V.8 AND AUTO MODE. VOICE / FAX / MODEM DISTINCTION. ADPCM VOICE COMPRESSION/DECOM-
PRESSION. VOICE DETECTION (SILENCE DETECTION)
OTHER FEATURES. VIRTUAL UART (460.8Kbps). AT HAYES COMMAND COMPATIBLE. TIME INDEPENDENT ESCAPE SEQUENCE
(TIES) COMMAND. CALLER ID DTMF DETECTION AND GENERATION. WAKE UP ON RING. WORLD-WIDE PROGRAMMABLE SILICON
DAA SUPPORT FOR ST75951/ST952
MAFE+DAA CHIP-SET
UNIVERSAL SERIAL BUS. SPECIFICATION 1.0, 12MBps FULL SPEED. ON-CHIP USB TRANSCEIVER WITH DIGITAL PLL. COMMUNICATION DEVICE CLASS AND
VENDOR REQUESTS. BUS OR SELF POWERED APPLICATION
(PIN-PROGRAMMABLE). ONNOW POWER MANAGEMENT (D0, D2, D3). LOW POWER CONSUMPTION (SUSPEND
MODE D2), WHOLE APPLICATION BELOW
500μA
DESCRIPTIONThe ST7554 is a single chip host signal processing
Modem/fax/voice controller that supports data rates
up to 56Kbps. All data pump and protocol functions
are executed on the host PC’s processor. This
product has been developed in cooperation with
Smart Link Ltd, who ported "USB-Modio", its host
based Modem and system software into ST system
and hardware platform. The ST7554 directly con-
nects to ST high performance Modem analog front-
end (MAFE) STLC7550 or to the highly integrated
MAFE+DAA chip-set ST75951/ST952. The ST7554
also features an Universal Serial Bus (USB) inter-
face for direct connection to the host PC for maxi-
mum flexibility and real plug & play operation.
1/11
PIN CONNECTIONS
ST75542/11
PIN LIST
Note 1 : Analog and digital ground pins must be tied together to USB ground GNDBUS.
ST75543/11
PIN DESCRIPTION
1 - Power Supply (7 pins)
1.1 - Regulator Input Power Supply (VBUS)This pin must be connected to USB VBUS (+5V).
It supplies the integrated analog USB transceiver.
It is also the positive regulator power supply input
(5V) when ST7554 is in bus-powered mode
(PSM = 1) and it is used to internally generate the
3.3V supply for the digital and analog circuitry.
1.2 - Regulated Analog VDD Supply (VREGA)This pin is the analog power supply input (PSM = 0)
or analog 3.3V power supply output (PSM = 1).
This pin is the positive analog power supply for the
external Codec and DAA.
It is recommended to add a 1μF capacitor between
VREGA and GNDA as close as possible to the
IC pins.
1.3 - Regulated VDD Supply (VREGD)This pin is the digital power supply input (PSM = 0)
or digital 3.3V power supply output (PSM = 1).
This pin is the positive digital power supply for the
external Codec and DAA.
It is recommended to add a 1μF capacitor between
VREGA and GNDA as close as possible to the
IC pins.
1.4 - Power Supply Mode (PSM)This pin controls the VREGD and VREGA power
supply mode.
When PSM = 1, the application is bus-powered.
The 3.3V power supply is generated internally from
VBUS. In this case VREGD and VREGA are out-
puts which can be used to supply 3.3V to external
devices (see Figure 1).
When PSM = 0, the application is self-powered.
VBUS must be still connected to the VBUS Pin of
the USB connector in order to supply the integrated
USB transceiver. Anyway in this case VREGD and
VREGA must be fed by a 3.3V externally regulated
digital and analog power supplies (see Figure 2).
1.5 - Ground (DGND, AGND and GNDBUS)DGND, AGND and GNDBUS are the digital, analog
and USB ground return pins respectively.
They should be connected together outside the
chip to the GND pin of the USB plug.
Figure 1 : ST7554 in Bus-Powered mode
(PSM = 1)
Figure 2 : ST7554 in Self Powered mode
(PSM = 0)
2 - USB Interface (D+ , D-)These pins are the positive and negative USB
differential data lines. They shall be both connected
to the USB plug or USB protection circuit via 27Ω
series resistors for line impedance matching.
ST75544/11
3 - Reset, Powerdown (RESET, PDOWN)RESET Pin initialises the internal counters and
control registers to their default value. A minimum
low pulse of 1ms is required to reset the chip.
In a typical application RESET is connected to
VBUS through a R, C network. This ensures that
the chip is reset at each connection / disconnection
to the USB bus (see Figure 3).
PDOWN Pin shall be connected to the powerdown
inputs of the external codec used on the SSI.
When ST7554 is in Suspend mode, PDOWN is
forced low so that the external codec is in
powerdown.
PIN DESCRIPTION (continued)
Figure 3 : RC network for RESET
Figure 4 : Application schematic for the
9.216MHz external crystal
4 - Serial Synchronous InterfaceST7554 has a Serial Syncronous Interface (SSI)
dedicated to the connection of the STLC7550 or
ST75951, ST high performance Modem Analog
Front-End (MAFE).
4.1 - Data (DIN, DOUT)Digital data word input/output of SSI, to be con-
nected to the data word pins of STLC7550 or
ST75951.
4.2 - Master Clock (MCLK)This pin is the master clock output.
4.3 - Frame Synchronization (FS)The frame synchronization is used to synchronize data
transfer between ST7554 and the external Codec.
4.4 - Hardware Control (HC1)HC1 must be connected to the corresponding pin of
STLC7550 or ST75951, while their HC0 Pin shall be
tied to the 3.3V VREGD digital supply. This pin
selects data or control modes for the Modem Codec.
4.5 - DAA Selection (DAASEL)Connect to VREGD when using silicon DAA chipset
based on ST75951 + ST952. Connect to DGND
when using STLC7550 with discrete interface.
5 - DAA Control Pins (IMP, DC, BUZEN,PULSE, DISHS, RFC, LED, CLID, HO, HSDT, RI)
These pins control the World Wide software
programmable DAA through ST75951/ST952.
6 - Crystal (XTALIN, XTALOUT)These pins must be tied to the 9.216MHz external
crystal.
It is recommended to use a ±50ppm fundamental
parallel resonator crystal. It is recommended to
insert a 1.8kΩ resistor between XTALOUT and the
crystal to limit its energy to 100μW for a 20Ω
resonator (see Figure 4).
For a SMD crystal the load capacitor is typically
CLOAD = 12pF and this leads to an ideal value of
C = 24pF for the capacitors between the crystal
and analog ground (AGND). Anyway, in practice
these capacitors shall be reduced down to
C = 18pF each by considering parasitic capacitors
on PCB and package (see Figure 4).
After a reset or when leaving the suspend state,
the 9.216MHz is asserted inside ST7554 only
3.5ms later in order to wait for it to be stable.
7 - PLL Output Filter (FLTPLL)This pin must be connected to the analog ground
(AGND) through a 33pF capacitor.
8 - Reserved Pins (18 pins)These pins must be left not connected except
Pin 47 which should be connected to the digital
ground DGND.
ST75545/11
ELECTRICAL SPECIFICATIONSUnless otherwise stated, electrical characteristics are specified over the operating range.
Typical values are given for VBUS = +5V, VREGA = 3.3V, VREGD = 3.3V, Tamb = 25°C.
Absolute Maximum Rating (AGND = DGND = USB GND = 0V, all voltages with respect to 0V)Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranted at these extremes.
Nominal DC Characteristics (Tamb = 0 to 70°C unless otherwise specified)POWER SUPPLY AND COMMON MODE VOLTAGE
DIGITAL INTERFACE (except XTALIN, XTALOUT, PSM and RESET) (these inputs have hysteresis)
PSM, RESET (these inputs have hysteresis)
CRYSTAL OSCILLATOR (XTALIN, XTALOUT)
ST75546/11
