ST75951 ,V.34/56K ANALOG FRONT END
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ST75951
V.34/56K ANALOG FRONT END
ST75951 .34/56K ANALOG FRONT END
February 1999V .34/56K MODEM ANALOG FRONT-END (AFE). 16 BITS OVERSAMPLING SIGMA DELTA A/D
AND D/A CONVERTERS. 85dB DYNAMIC RANGE. PROGRAMMABLE SAMPLING FREQUENCY. AUXILIARY ANALOG INPUT. MODEM SIDE OF SILICON DATA ACCESS AR-
RANGEMENT (DAA) INTEGRA TED WITH AFE. KRYPTON ISOLATION INC. PATENTED
TECHNOLOGY ELIMINATE TRANSFORMER
OR LINEAR OPTO-COUPLERS. RING DETECT, LINE IN USE, CLID AND
OVER LOOP CURRENT DETECT. 4 GPIO ASSOCIATED WITH 1 GENERAL
PURPOSE INTERRUPT OUTPUT. ANALOG AND DIGITAL LOOP-BACK MODE. SYNCHRONOUS SERIAL INTERFACE FOR
PROCESSORS DATA EXCHANGE. ON CHIP REFERENCE VOLTAGE. SINGLE POWER SUPPLY RANGE :
2.7V TO 5.25V. LOW POWER CONSUMPTION : 40mW @ 3.3V. TQFP48 PACKAGE. 0.5μM CMOS PROCESS
DESCRIPTIONST75951 is an analog front-end designed to im-
plement modems application up to 56Kbps.
ST75951 interfaces between DSP or HSP signals
and capacitive isolation barrier.
A complete D.A.A. is made with ST952 which inter-
faces between capacitive isolation barrier and the
telephone line.
It integrates a high resolution A/D and D/A
converter and incorporates Krypton Isolation
Inc. patented silicon D.A.A. technology.
Figure 11/21
PIN CONNECTIONS
ST759512/21
PIN LIST
Note 1 : Digital and Analog ground must be connected externally together.
ST759513/21
PIN DESCRIPTION
1 - Power Supply (5 Pins)
1.1 - Power Supply (AVDD, DVDD)These pins are the positive analog and digital
power supply input (2.7 to 5.25V).
In any case, the AVDD voltage must always be higher
or equal to the DVDD voltage (AVDD ≥ DVDD).
1.2 - Analog Ground ( AGND1, AGND2)These pins are the ground return of the DAC and
ADC analog section.
1.3 - Digital ground (DGND)This pin is the ground return of the digital circuitry.
Note : In order to obtain published performances,
the analog AVDD and digital DVDD should be decou-
pled with respect to analog ground and digital
ground, respectively. Decoupling capacitors should
be as close as possible to the supplies pins. All
ground must be tied together. In the following sec-
tion the ground is referred as : GND.
2 - Serial Synchronous Interface (4 Pins)
2.1 Data (DIN, DOUT)Digital data word input/output of the SSI (16 bits
data).
2.2 - Frame Synchronization (FS)The frame synchronization is used to indicate that
the device is ready to send and receive data.
The data transfer begins on the falling edge of
frame-sync signal. The frame-SYNC can be gener-
ated internally or externally.
2.3 Serial Bit Clock (SCLK)Clocks the digital data into DIN and out of DOUT
during the frame synchronization interval. The se-
rial bit clock is generated internally and equal to
MCLK/R (R programmed value in register 3). The
serial bit clock is a multiple of FS.
3 - Control Pins (10 Pins)
3.1 - Reset (RESET)This pin initializes the internal counters and control
registers to their default value. A minimum low
pulse of 100ns is required to reset the chip.
3.2 - Power-Down (PWRDWN)This input powers down the entire chip. In power
down mode the existing internally programmed
state is maintained. When power down is driven
high, full operation resumes after 1ms.
A software powerdown with wake-up on ring detect
is also provided with bit 4 in control register 3.
3.3 - Hardware Control (HC0, HC1)These pins are used for hardware/software control
programmation of the device.
3.4 - Hardware Control (HM)This pin is used for hardware/software control of
CLID/OFFHOOK function.
3.5 - Master/Slave (M/S)When M/S = " 1 " the device is in master mode and
FS is generated internally otherwise the device is
in slave mode and Fs must be provided externally
and equal to SCLK*R / OVER.
3.6 - Timeslot Control (TS)When TS = " 0 " the data are assigned to the
first timeslot (1st 16 bits after falling edge of FS)
otherwise the data are on the second timeslot
(bits 17 to 32).
3.7 - Control (D5, D6)These pins transmit the control signals trough iso-
lation capacitors to ST952 which converts and
outputs the appropriate control signals.
3.8 - Master Clock Mode (MCM)When MCM = " 1 ", we have
FS = Master Clock/[M ⋅ Q ⋅ OVER] otherwise we
have FS = Master Clock/OVER and the M, Q
dividers are bypassed.
4 - General Purpose Input/Output Circuitry
4.1 - GPIO (4 Pins)ST75951 offers 4 general purpose Input/Output
pins. The setting of the GPIO configuration is done
through the control register 1 and the signal level
of the GPIO are reflected in the feedback register 2.
At power on the GPIO are programmed as inputs.
In order to take into account the evolution of ST952,
thanks to the control register we will be able to send
a clock signal equal to F0/N (N programmed in
register 2) on GPIO0 and F0 on GPIO3.
When in DAA control hardware mode HM = 1, the
CLID and OFF-HOOK control is done by Pin GPIO1
(CLID) and GPIO2 (OFF-HOOK), otherwise when
HM = 0 then the CLID/OFF-HOOK control is done
by programming the adequate bit in the control
register 3 (Bit 2 , Bit 3, see Table 7).
ST759514/21
4.2 - General Purpose Interrupt System (GPI)The GPI will reflect any change of the GPIO’S
inputs or RING output when non-masked, so the
processor does not need to read the output control
word continuously. GPI level change tells the proc-
essor, one of the non-masked input pins level has
changed and he can read the control word. So
GPIO could extend the number of interrupt pins of
the processor.
5 - RingThis pin is used for the Ring detect but also reports
the Line status, current limit.
6 - Digital Test Pin (TSTD1)This pin is reserved for digital test purpose.
7 - Crystal (XTALIN , XTALOUT)These pins must be tied to an external crystal or a
master clock generator (MCLK).
8 - Analog Interface (12 Pins)
8.1 - DAC and ADC Reference Voltage Output(VREFP, VREFN )
These pins provide the positive and negative
reference Voltage used by the 16-bit converters.
The reference voltage, VREF, is the voltage difference
between the VREFP and VREFN outputs.
VREFP and VREFN should be externally decoupled
with respect to VCM.
8.2 - Common Mode Voltage Output (VCM)This output pin is the common mode voltage
(AVDD - AGND)/2 . This output must be decoupled
with respect to GND.
8.3 - Common Mode Voltage Input (VCMP, VCMS)These input pins are the common mode voltage for
internal circuitry. They have to be connected exter-
nally to VCM.
8.4 - Analog Transmit Output (D1 ,D2)These pins are the output of the fully differential
converted analog signal, modulated at F0
(1MHz < F0 < 1.7MHz).
The digital data IN signal is converted in analog
signals (with (Sin X)/X compensation). Two ranges
of signal amplitude have to be considered ; modem
application with dynamic up to 2.5VPP with maxi-
mum performances SNDR = 83dB, voice applica-
tion with dynamic up to 3.2VPP differential
(SNDR = 75dB).
The transmit output stage can be programmed to
+2dB gain, 0db gain, 6dB or infinite attenuation.
8.5 - Analog Receive Inputs (D3, D4)These pins are the differential analog inputs. These
analog inputs are presented to the F0 demodulator
and the sigma-delta modulator. The analog input
peak-to-peak differential signal range must be less
than 2.5 VPP. The gain of the receive stage is
programmable to 0dB or 6dB.
8.6. - Analog Test Pin (TSTA1, TSTA2)These pins are reserved for analog test purpose.
8.7 Analog Auxiliary Receive Inputs (AUXIN)This pin is the auxiliary analog input. This analog
input is presented to the analog modulator. The
analog input peak-to-peak signal range must be
less than 1.25 VPP. The gain of the receive stage
is 0dB.
PIN DESCRIPTION (continued)
ST759515/21
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTIONST75951 is a modem AFE front-end integrating the
modem side of Krypton K951 and fully compatible
to work with ST952.
1 - Transmit Section The functions included in the transmit section are : D/A converter, F0 modulator, Programmable stage +2dB gain, 0dB gain, 6dB
attenuation or infinite attenuation, Transmit Filter including noise shaper and Sinx/x
correction.
The digital base Band data (DIN) are converted and
modulated at F0 and send differentially (D1, D2) to
ST952 through capacitive connection.
2 - Receive Section The functions included in the receive section are : Main and Aux inputs, Programmable gain 0/6dB, A/D converter, F0 demodulator, Receive filter.
The analog differential Main input signal (D3, D4)
coming from ST952 is demodulated at F0, goes to
the multiplexer and gain receive block then is digi-
tally converted and output on DOUT which is the
base band data.
Thanks to the multiplexer, we can also process
base band analog signal on AUXIN.
3 - Clock GeneratorST75951 generates all clocks from either a Master
clock input on XTALIN (MCLK) or a crystal oscillator
connected between XTALIN and XTALOUT.
The bypass of the divider M and Q is selected by
setting the MCM input pin to ’0’.
To be able to provide externally the sampling fre-
quency (Slave mode), M/S input pin must be set
to ’0’ (see Figure 2).
ST759516/21
Figure 2
4 - Power Down ModeTwo PowerDown modes are available in ST75951
thanks to bit 4 in control register 3.
4.1 - PowerDown Mode 0If bit 4 is set to ’0’ then when PWRDWN is set to ’0’
the entire chip is in powerdown mode 0.
FUNCTIONAL DESCRIPTION (continued)
Figure 3
4.2 - PowerDown Mode 1 (100μW)When bit 4 is set to ’1’ then when PWRDWN is set
to ’0’ the chip is in powerdown except the Ring detect
circuitry (wake-up on Ring = powerdown mode 1).
The general purpose interrupt is also working in
order to wake-up the system for dedicated cus-
tomer feature associated with a defined GPIO (pro-
grammed as input and non-masked).
4.2.1 - Ring Bit and GPIO Bit Masked In this configuration the processor relies on the
Ring output pin to process the wake-up of the
system and does not need the SSI to be powered-
on. The SSI will be put back in operative mode
when PWRDWN is set to ’1’ (see Figure 4).
4.2.2 - Ring Bit or GPIO Bit Non-Masked In this configuration the processor relies on the SSI
to process the wake-up of the system and needs
the SSI to be powered-on.
On an incoming Ring signal or an interrupt coming
thanks to the GPIO, ST75951 will generate an
interrupt on GPI output pin and power-up the SSI,
the processor will be able to read the control regis-
ter 2 and find out the origine of the interrupt.
After a reading of the register 2, if the processor
does not set high PWRDWN ST75951 puts back
the SSI off in order to save energy (see Figure 5).
ST759517/21
Figure 5
FUNCTIONAL DESCRIPTION (continued)
Figure 4
5 - Mode of OperationThanks to MCM and M/S programmation pins we
can get the following configuration.
Configuration 1 : MCM = M/S = ’1’.ST75951 is in master mode and we have :
FS = FQ / (M x Q x OVER). FS is an output.
(see Figure 6).
Configuration 2 : MCM = ’1’, M/S = ’ 0 ’.ST75951 is in slave mode and the processor pro-
vides FS = (R x SCLK) OVER. FS is an input
(see Figure 7).
Configuration 3 : MCM = ’0’, M/S = ’1’.ST75951 is in master mode and we have :
FS = FQ / (OVER). FS is an output (see Figure 8).
Configuration 4 : MCM = ’0’, M/S = ’ 0 ’.The configuration 4 is equivalent to configuration 3
but the processor generates the FS and control the
phase.
ST75951 is in slave mode and the processor pro-
vides FS = (R x SCLK)/OVER. FS is an input
(see Figure 9).
Configuration 5 : Master codec 1 : MCM = ’0’,
M/S = ’ 1 ’. Slave codec 2 : MCM = ’0’, M/S = ’ 0 ’.
This is a dual codec application running on the
same SSI. The master codec has his data in times-
lot 0 ( bit 0 to bit15 ) and the slave codec has his
data in timeslot 1 (bit 16 to bit 31) thanks to the
programmation of TS (see Figure 10).
ST759518/21
Figure 8
Figure 7
FUNCTIONAL DESCRIPTION (continued)
Figure 9
Figure 6
Figure 10
6 - General Purpose Input / OutputST75951 features 4 GPIO. The GPIO0..3 are tradi-
tional inputs/outputs programmed and set thanks to
the control register 1 (mask, input/output) and control
register 2 (output value, static or modulated).
GPIO0 output is dedicated to output F0/N clocks
instead of a static ’1’ if bit 6 in control register 2 is
set. GPIO3 is dedicated to output F0 clock instead
of a static ’1’ if bit 10 in control register 2 is set (see
Figure 11 and 12).
ST759519/21
Figure 12 : GPIO3 When bit10 = ’1’ in REG2
FUNCTIONAL DESCRIPTION (continued)
Figure 11 : GPIO0 When bit6 = ’1’ in REG2GPIO1 and GPIO2 are dedicated input and control
CLID and OFF-HOOK function respectively if the
control input Pin HM is set to ’1’.
Table 2CL, OH : Bit 2, 3 Reg 3.
Depending of the setting of the Mask bit in control
register 1, any change of non-masked GPIO can
generate an interrupt to the processor thanks to
GPI (General purpose Interrupt).
7 - Operating ModesThree operating modes controlled either by the
GPIO1 and 2 or by the control register 3 are imple-
mented : ON-HOOK, OFF-HOOK, CLID (Caller ID).
Figure 14
7.1 - ON-HOOKDuring ON-HOOK state no signal is sent by D5, D6.
D5 = D6 = VDD.
RingWhen in ON-HOOK state, the ST952 sends a
1MHz differential signal on D3, D4 when it re-
ceives an incoming ringing signal from Tip/Ring.
ST75951 will output on RING Pin the image of the
ring signal (RING Pin is also duplicated in the read
register 2 bit 5) (see Figure 15).
7.2 - OFF-HOOKDepending on Pin HM status (see Table 2), 2 pos-
sibilities are offered to control the device to go in
OFF-HOOK state.
D5 and D6 send F0 clock in opposite phase to
ST952.
ST7595110/21
FUNCTIONAL DESCRIPTION (continued)
Figure 15D5 = D6 = VDD.
7.3 - Caller IDDepending on Pin HM status (see Table 2), 2 pos-
sibilities are offered to control the device to go in
caller ID state.
F0 clock is send to D5, in caller ID mode the
modulation frequency of ST952 is equal to F0/2, so
the demodulation on the receive signal at D3, D4
is at F0/2 in caller ID mode.
Figure 16D6 = VDD.
Figure 17
8 - Phone Line Monitoring FeaturesThis chipset is intended to be used for a wide range
of application such as modem, answering machine,
telephony on PC, so because the home PSTN
phone line will be shared by several terminals,
information concerning the line status has to be
sent to the host.
As long as there is an alerting signal at D3, D4 Pins,
the ADC converter is saturated and outputs 7FFF
or 8000 at DOUT Pin.
8.1 - Line In Use CheckingBefore going OFF-HOOK the modem software can
check that the line is free by setting the CLID mode
and check that the RING Pin/bit output a low pulse.
When in CLID mode if the line is free the ST952 will
output a F0/2, 5VPP differential signal on D3, D4
(see Figure 18).
8.2 - Digital Phone Line or Over Loop Current
Limit DetectWhen portable modem plug into digital line, it will cause
over loop current during modem off-hook state.
The modem controller should know this condition
and go onhook to avoid the DAA being damaged.
ST952 when OFF-HOOK will determine if the loop
current exceeds the current limit or not (160mA).
If we have overcurrent ST952 will continuously
output a low level on RING output Pin.
ST7595111/21
