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STCF03PNR
HIGH POWER WHITE LED DRIVER
February 2011 Doc ID 13169 Rev 7 1/35
STCF03High power white LED driver with I²C interface
Features Buck-boost DC-DC converter Drives one power white LED up to 800 mA from
2.7 V to 5.5 V in QFN Drives one power white LED up to 800 mA from
3.3 V to 5.5 V in BGA Efficient up to 92% Output current control 1.8 MHz typ. fixed frequency PWM Synchronous rectification Full I²C control Operational modes: Shutdown mode Shutdown + NTC Ready mode + auxiliary red LED Flash mode: up to 800 mA Torch mode: up to 200 mA Soft and hard triggering of flash Flash and torch dimming with 16 exponential
values Dimmable red LED indicator auxiliary output Internally or externally timed flash operation Digitally programmable safety time-out in flash
mode LED overtemperature detection and protection
with external NTC resistor Opened and shorted LED failure detection and
protection Chip over temperature detection and protection < 1 µA shutdown current Packages:
–QFN20 (4 x 4) TFBGA25 (3 x 3)
Applications Cell phone and smart phone Camera flashes/strobe PDAs and digital still cameras
DescriptionThe STCF03 is a high efficiency power supply
solution to drive a single flash LED in camera
phone, PDAs and other hand-held devices. It is a
buck - boost converter to guarantee a proper LED
current control over all possible conditions of
battery voltage and output voltage; the output
current control ensure a good current regulation
over the forward voltage spread characteristics of
the flash LED. Thanks to the high efficiency of the
converter allows having the input current taken
from the battery remain under 1.5 A.
Table 1. Device summary
Contents STCF032/35 Doc ID 13169 Rev 7
Contents Description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.1 Buck-boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Logic pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.1 SCL, SDA pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.2 TRIG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.3 ATN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.4 ADD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2.5 TMSK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.4 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.5 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.6 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.7 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.8 Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.9 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10 Writing to multiple registers with incremental addressing . . . . . . . . . . . . 18
7.11 Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.12 Reading from multiple registers with incremental addressing . . . . . . . . . 19
Description of internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208.1 PWR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STCF03 ContentsDoc ID 13169 Rev 7 3/35
8.2 TRIG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.3 TCH_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.4 NTC_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.5 FTIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.6 TDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.7 FDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.8 AUXI_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.9 AUXT_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.10 F_RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.11 LED_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.12 NTC_W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.13 NTC_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.14 OT_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.15 VOUTOK_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259.1 PowerON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2 Shutdown, shutdown with NTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.3 Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.4 Single or multiple Flash using external (microprocessor) temporization . 25
9.5 External (microprocessor) temporization using TRIG_EN bit . . . . . . . . . 26
9.6 Single Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . 26
9.7 Multiple Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . 26
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
List of tables STCF03
4/35 Doc ID 13169 Rev 7
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. List of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. I²C register mapping function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Dimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Auxiliary LED dimming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Torch mode and flash mode dimming registers settings . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Status register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. QFN20 (4 x 4 mm.) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STCF03 List of figures
Doc ID 13169 Rev 7 5/35
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Procedure for assigning a non-default I²C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Data validity on the I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Timing diagram on I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Acknowledge on I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Writing to multiple register with incremental addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Reading from multiple registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Flash and Torch current vs. dimming value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. VOUTOK_N behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. IOTORCH vs. T_DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. IOFLASH vs. F_DIMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18. IOAUX vs. AUXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 19. IOFLASH vs. temp. VI = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20. VFB2 vs. temp. at IO = 800 mA,VI = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. IQ vs. temp. VI = 5.5 V ready-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. Start-up in flash mode 800 mA at VI = 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Line transient in flash mode 800 mA, change of VI from 2.7 V to 3.3 V in 10 µs . . . . . . . . 28
Figure 24. QFN20 (4 x 4 mm.) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Description (continued) STCF03
6/35 Doc ID 13169 Rev 7
1 Description (continued)
All the functions of the device are controlled through the I²C which helps bus that allows to
reduce logic pins on the package and to save PCB tracks on the board. Hard and soft-
triggering of flash are both supported. The device includes many functions to protect the
chip and the power LED such as: a soft start control, chip over temperature detection and
protection as well as opened and shorted LED detection and protection. Besides, a digital
programmable time out function protects the LED in case of a wrong command from the
microprocessor. An optional external NTC resistor is supported to protect the LED against
over heating.
In mobile phone applications it is possible to reduce immediately the flash LED current
during the signal transmission using the TMSK pin. This saves battery life and gives more
priority to supply RF transmission instead of flash function.
It is possible by I²C to separately program the current intensity in flash and torch mode using
exponential steps. An auxiliary output can control an optional red LED to be used as a
recording indicator.
The device is packaged in QFN (4 x 4 mm) 20L with a height less than 1 mm and in
TFBGA25 (3 x 3 mm).
STCF03 Diagram
Doc ID 13169 Rev 7 7/35
2 Diagram
Figure 1. Block diagram
Pin configuration STCF03
8/35 Doc ID 13169 Rev 7
3 Pin configuration
Figure 2. Pin connections (bottom view)
Table 2. Pin description
STCF03 Maximum ratings
Doc ID 13169 Rev 7 9/35
4 Maximum ratings
Table 3. Absolute maximum ratings (1) Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under
these condition is not implied. Power dissipation is related parameter to used PCB. The recommended PCB design is included in the application note.
Table 4. Thermal data
Application STCF03
10/35 Doc ID 13169 Rev 7
5 Application
**: Connect to VI, or GND or SDA or SCL to choose one of the 4 different I²C Slave Addresses.
***: Optional components to support auxiliary functions.
Note: All of the above listed components refer to typical application. Operation of the STCF03 is
not limited to the choice of these external components.
Figure 3. Application schematic
Table 5. List of external components
STCF03 Electrical characteristics
Doc ID 13169 Rev 7 11/35
6 Electrical characteristics
TJ = 25 °C, VI = 3.6 V, 2 x CI = 10 µF, CO = 1 µF, L = 4.7 µH, RFL = 0.27 Ω, RTR = 1.8 Ω,
RX = 15 kΩ, Typ. values @ 25 °C, unless otherwise specified.
Table 6. Electrical characteristics
Electrical characteristics STCF03
12/35 Doc ID 13169 Rev 7
Note: T ypical value, not production tested.
Table 6. Electrical characteristics (continued)
STCF03 Introduction
Doc ID 13169 Rev 7 13/35
7 Introduction
The STCF03 is a buck-boost converter, dedicated to power and control the current of a
power white LED in a camera cell phone. The device operates at a constant switching
frequency of 1.8 MHz typ. It provides an output voltage down to 2.5 V and up to 5.3 V, from
a 2.7 V to 5.5 V supply voltage. This supply range allows operation from a single cell
Lithium-Ion battery. The I²C bus is used to control the device operation and for diagnostic
purposes. The current in torch mode is adjustable from 15 mA to 200 mA. Flash mode
current is adjustable up to 800 mA, BGA version is able to deliver 600 mA at battery range
2.7 V to 3.3 V. The Aux LED current can be adjusted from 0 to 20 mA. The device uses an
external NTC resistor to sense the temperature of the white LED. These two last functions
may not be needed in all applications, and in these cases the relevant external components
can be omitted.
7.1 Buck-boost converter
The regulation of the PWM controller is done by sensing the current of the LED through
external sensing resistors (RFL and RTR, see application schematic). Depending on the
forward voltage of the flash LED, the device automatically can change the operation mode
between buck (step down) and boost (step up) mode.
Three cases can occur: boost region (VO > VBAT): this configuration is used in most of the
cases, as the output voltage VO = VfLED + ILED x RFL) is higher than VBAT; buck region (VO
< VBAT); buck - boost region (VO ~ VBAT).
7.2 Logic pin description
7.2.1 SCL, SDA pins
These are the standard clock and data pins as defined in the I²C bus specification. External
pull-up is required according to I²C bus specifications. The recommended maximum voltage
of these signals should be 3.0 V.
7.2.2 TRIG pin
This input pin is internally AND-ed with the TRIG_EN bit to generate the internal signal that
activates the flash operation. This gives to the user the possibility to accurately control the
flash duration using a dedicated pin, avoiding the I²C bus latencies (hard-triggering). No
internal pull-up nor pull-down is provided.
7.2.3 ATN pin
This output pin (open-drain, active LOW) is provided to better manage the information
transfer from the STCF03 to the microprocessor. Because of the limitations of a single
master I²C bus configuration, the microprocessor should regularly poll the STCF03 to verify
if certain operations have been completed, or to check diagnostic information. Alternatively,
the microprocessor can use the ATN pin to be advised that new data are available in the
STA T_REG, thus avoiding continuous polling. Then the information can be read in the
STAT_REG by a read operation via I²C that, besides, automatically resets the ATN pin. The
STAT_REG bits affecting the ATN pin status are mapped in Table 16. No internal pull-up is
provided.
Introduction STCF03
14/35 Doc ID 13169 Rev 7
7.2.4 ADD pin
With this pin it is possible to select one of the 4 possible I²C slave addresses. No internal
pull-up nor pull-down is provided. The pin has to be connected either GND, VI, SCL or SDA
to select the desired I²C slave address (see Table6)
When ADD is connected to GND the I²C address is assigned automatically while in the
other three configurations in which ADD pin is connected to VBAT or SDA or SCL, the
following procedure must be activated in order that the right address is assigned.
After applying VBAT to the chip, the VBAT voltage must be pulled down to GND for a time
longer than 100 ms. After that time the right I²C address is assigned to the chip. This
procedure must be repeated every time the VBAT voltage is disconnected (see Figure4
below)
7.2.5 TMSK pin
This pin can be used to implement the TX masking function. This function has effect only for
flash current settings higher than 200 mA (bit FDIM_3 = 1). Under this condition, when this
pin is pulled high by the P , the current flowing in the LED is forced at 200 mA typ. No internal
pull-up nor pull-down is provided: to be externally wired to GND if TX masking function is not
used.
Table 7. Address table
Figure 4. Procedure for assigning a non-default I²C address
STCF03 Introduction
Doc ID 13169 Rev 7 15/35
7.3 I²C bus interface
Data transmission from the main microprocessor STCF03 and vice versa takes place
through the 2 wires I²C bus interface wires, consisting of the two lines SDA and SCL (pull-up
resistors to a positive supply voltage must be externally connected). The recommended
maximum voltage of these signals should be 3.0 V.
7.4 Data validity
As shown in Figure 5, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
7.5 Start and stop conditions
Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 6 a
start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition
must be sent before each START condition.
Figure 5. Data validity on the I²C Bus
Figure 6. Timing diagram on I²C Bus
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7.6 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time will be interpreted as a control signal.
7.7 Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 8). The peripheral (STCF03) that acknowledges has to
pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate an acknowledge pulse after the reception of each byte, otherwise the SDA line
remains at the HIGH level during the ninth clock pulse duration. In this case the master
transmitter can generate the STOP information in order to abort the transfer. The STCF03
won't generate the acknowledge if the VI supply is below the undervoltage lockout threshold.
Figure 7. Bit transfer
Figure 8. Acknowledge on I²C Bus
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7.8 Writing to a single register
Writing to a single register starts with a START bit followed by the 7 bit device address of
STCF03. The 8th bit is the R/W bit, which is 0 in this case. R/W = 1 means a reading
operation. Then the master waits for an acknowledge from STCF03. Then the 8 bit address
of register is sent to STCF03. It is also followed by an acknowledge pulse. The last
transmitted byte is the data that is going to be written to the register. It is again followed by
an acknowledge pulse from STCF03. Then master generates a STOP bit and the
communication is over. See Figure 9 below.
7.9 Interface protocol
The interface protocol is composed: A start condition (START) A Device address + R/W bit (read =1 / write =0) A Register address byte A sequence of data n* (1 byte + acknowledge) A stop condition (STOP)
Table 8. Interface protocol
Figure 9. Writing to a single register
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The register address byte determines the first register in which the read or write operation
takes place. When the read or write operation is finished, the register address is
automatically increased.
7.10 Writing to multiple registers with incremental addressing
It would be unpractical to send several times the device address and the address of the
register when writing to multiple registers. STCF03 supports writing to multiple registers with
incremental addressing. When the data is written to a register, the address register is
automatically increased, so the next data can be sent without sending the device address
and the register address again. See Figure 10 below.
7.11 Reading from a single register
The reading operation starts with a START bit followed by the 7 bit device address of
STCF03. The 8th bit is the R/W bit, which is 0 in this case. STCF03 confirms the receiving of
the address + R/W bit by an acknowledge pulse. The address of the register which should
be read is sent afterwards and confirmed again by an acknowledge pulse of STCF03 again.
Then the master generates a START bit again and sends the device address followed by the
R/W bit, which is 1 now. STCF03 confirms the receiving of the address + R/W bit by an
acknowledge pulse and starts to send the data to the master. No acknowledge pulse from
the master is required after receiving the data. Then the master generates a STOP bit to
terminate the communication. See Figure 11.
Figure 10. Writing to multiple register with incremental addressing
