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STD40NF3LLSTN/a9000avaiN-CHANNEL 30V


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STD40NF3LL
N-CHANNEL 30V
STD40NF3LL
N-CHANNEL 30V- 0.0095W - 40A DPAK
LOW GATE CHARGE STripFET POWER MOSFET
PRELIMINARY DATA
TYPICAL RDS(on)= 0.0115W @ 4.5V OPTIMAL RDS(on) xQg TRADE-OFF@ 4.5V CONDUCTION LOSSES REDUCED SWITCHING LOSSESREDUCED
DESCRIPTION

This application specific Power Mosfetis the third
generationof STMicroelectronics unique ”Single
Feature Size” strip-based process. The resul-
ting transistor shows the best trade-off between
on-resistance and gate charge. When used as
high and low sidein buck regulators,it gives the
best performancein termsof both conduction and
switching losses. Thisis extremely important for
motherboards where fast switching and high effi-
ciency areof paramount importance.
APPLICATIONS
SPECIFICALLYDESIGNED AND
OPTIMISED FOR HIGH EFFICIENCY CPU
CORE DC/DC CONVERTERS
INTERNAL SCHEMATIC DIAGRAM

September 2001
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit

VDS Drain-source Voltage (VGS =0) 30 V
VDGR Drain- gate Voltage (RGS =20kW )30 V
VGS Gate-source Voltage ± 16 V Drain Current (continuous)atTc =25o C40 A Drain Current (continuous)atTc =100o C28 A
IDM(•) Drain Current (pulsed) 160 A
Ptot Total DissipationatTc =25o C55 W
Derating Factor 0.37 W/oC
Tstg Storage Temperature -65to 175 oC Max. Operating Junction Temperature 175 oC
(•) Pulse widthlimitedby safe operating area
TYPE VDSS RDS(on) ID

STD40NF3LL 30V < 0.0115W 40A
ADD SUFFIX ”T4” FOR ORDERINGIN TAPE& REEL
DPAK
TO-252

(Suffix ”T4”)
1/6
THERMAL DATA
Rthj-case
Rthj-amb
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
300 C/W C/WC
ELECTRICAL CHARACTERISTICS
(Tcase =25oC unless otherwisespecified)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source
Breakdown Voltage =250m AVGS =0 30 V
IDSS Zero Gate Voltage
Drain Current (VGS =0)
VDS =Max Rating
VDS =Max Rating Tc =125oCAA
IGSS Gate-body Leakage
Current (VDS =0)
VGS= ± 16 V ± 100 nA(*)
Symbol Parameter Test Conditions Min. Typ. Max. Unit

VGS(th) Gate Threshold Voltage VDS =VGS ID= 250m A1 2.5 V
RDS(on) Static Drain-source On
Resistance
VGS =10V ID =20A
VGS =4.5V ID =10A
ID(on) On State Drain Current VDS >ID(on) xRDS(on)max
VGS =10V
40 A
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit

gfs(* )Forward
Transconductance
VDS >ID(on) xRDS(on)max ID =20 A 40 S
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS= 25Vf= 1MHz VGS= 0 1700
STD40NF3LL
2/6
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit

td(on)
Turn-on Delay Time
Rise Time
VDD =15V ID =20A =4.7 W VGS =4.5V
(Resistive Load, see fig.3)
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD =24VID =40A VGS =10V 43 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit

td(off)
Turn-off Delay Time
Fall Time
VDD =15V ID =20A =4.7 W VGS =4.5V
(Resistive Load, see fig.3)
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit

ISD
ISDM(•)
Source-drain Current
Source-drain Current
(pulsed)
VSD(* )Forward On Voltage ISD =40A VGS =0 1.5 V
trr
Qrr
IRRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
ISD=40A di/dt= 100A/ms
VDD =15V Tj =150oC
(see test circuit, fig.5)
2.4) Pulsed: Pulse duration= 300ms, duty cycle 1.5%
(•) Pulse width limitedby safe operating area
STD40NF3LL

3/6
Fig.1: Unclamped Inductive Load Test Circuit
Fig.3:
Switching Times Test Circuits For
Resistive Load
Fig.2:
Unclamped Inductive Waveform
Fig.4:
Gate Chargetest Circuit
Fig.5:
Test Circuit For Inductive Load Switching
And Diode Recovery Times
STD40NF3LL

4/6
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
2.2 2.4 0.086 0.094 0.9 1.1 0.035 0.043 0.03 0.23 0.001 0.009 0.64 0.9 0.025 0.035 5.2 5.4 0.204 0.212 0.45 0.6 0.017 0.023 0.48 0.6 0.019 0.023 6 6.2 0.236 0.244 6.4 6.6 0.252 0.260 4.4 4.6 0.173 0.181 9.35 10.1 0.368 0.397 0.8 0.031 0.6 1 0.023 0.039L2DETAIL”A”
DETAIL”A”
TO-252 (DPAK) MECHANICAL DATA

0068772-B
STD40NF3LL

5/6
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grantedby implicationor otherwise underany patentor patent rightsof STMicroelectronics. Specification mentionedinthis publicationare
subject tochange withoutnotice. This publication supersedesand replacesall information previously supplied. STMicroelectronics products
arenot authorizedforuseas critical components inlife support devicesor systems without express written approval ofSTMicroelectronics.
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STD40NF3LL

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