TDA9106A ,LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORSTDA9106ALOW COST DEFLECTION PROCESSORFOR MULTISYNC MONITORSPRELIMINARY DATAHORIZONTALCombined with ..
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TDA9106A
LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
TDA9106ALOW COST DEFLECTION PROCESSOR
FOR MULTISYNC MONITORS
November 1997
PRELIMINARY DATA 22 GND
SDA
SCL
H/HVIN
HLOCKOUT
VSYNCOUT
TEST
HOUT
VSYNCIN
VFOCUS
EWOUT
VFLY
VOUT
VDCOUT
VCAP
VREF
VAGCCAP
VGND
VBLKOUT
HBLKOUT
S/G
PLL1INHIB
PLL2C
HREF
HFLY
HGND
FC2
FC1
PLL1F
HLOCKCAP
HPOS
XRAY
HFOCUSCAP
HFOCUS
VCC
GND
HOUTEM
HOUTCOL
MOIRE
106A
1.E
PIN CONNECTIONS
SHRINK42(Plastic Package)
ORDER CODE: TDA9106A
HORIZONTAL. SELF-ADAPTATIVE. DUAL PLL CONCEPT. 150kHz MAXIMUM FREQUENCY. X-RAYPROTECTION INPUT.I2C CONTROLS: HORIZONTAL POSITION,
FREQUENCY GENERATOR FOR BURN-IN
MODE
VERTICAL. VERTICAL RAMP GENERATOR.50 TO 165Hz AGC LOOP. GEOMETRY TRACKINGWITH V-POS& AMP.I2C CONTROLS:
V-AMP, V-POS, S-CORR, C-CORR
2
C GEOMETRYCORRECTIONS. VERTICAL PARABOLA GENERATOR
(Pincushion, Keystone, Corner Correction,
Top/bottomCorner Correction Balance). HORIZONTAL DYNAMIC PHASE
(Side Pin Balance& Parallelogram). HORIZONTAL AND VERTICAL DYNAMIC FO-
CUS (Horizontal Focus Amplitude, Horizontal
Focus Symmetry)
GENERAL. SYNC PROCESSOR. HOR.& VERT. SYNC OUTPUT FOR MCU. HOR.& VERT. BLANKING OUTPUTS. 12V SUPPLY VOLTAGE.8V REFERENCE VOLTAGE. HOR.& VERT. LOCK UNLOCK OUTPUTS. READ/WRITEI2C INTERFACE. HORIZONTAL MOIRE OR DAC OUTPUT
DESCRIPTIONThe TDA9106Aisa monolithic integrated circuit
assembledin 42 pins shrunk dualin line plastic
package.ThisICcontrolsall the functionsrelatedto
the horizontaland vertical deflectionin multimodes multi-frequency computerdisplay monitors.
Theinternalsyncprocessor, combinedwiththevery
powerful geometrycorrection block are making the
TDA9106Asuitablefor veryhighperformancemoni-
tors with very few externalcomponents.is particularly wellsuitedfor high-end15” and 17”
monitors.
Combined with ST7275 Microcontroller family,
TDA9206 (Video preamplifier) and STV942x
(On-Screen Display controller) the TDA9106A
allowsto built fullyI2C bus controlled computer
display monitors, thus reducing the numberof
external componentstoa minimum value.
1/30
PIN CONNECTIONS
Pin Name Function S/G Syncon green input MOIRE Moire output PLL1 INHIB TTL-Compatible inputfor PLL1 inhibition PLL2C Second PLL LoopFilter HREF Horizontal Section Reference Voltage(to filter) HFLY Horizontal Flyback Input (positive polarity) HGND Horizontal Section Ground FC2 VCO Low Threshold filtering Capacitor FC1 VCO High Threshold filtering Capacitor C0 Horizontal Oscillator Capacitor R0 Horizontal Oscillator Resistor PLL1F First PLL Loop Filter HLOCKCAP First PLL Lock/Unlock Time Constant Capacitor HPOS Horizontal Centering Output(to filter) XRAY X-RAY protection input (with internal latch function) HFOCUSCAP Horizontal Dynamic Focus Oscillator Capacitor HFOCUS Horizontal Dynamic Focus Output VCC Supply Voltage (12V Typ) GND General Ground (relatedto VCC) HOUTEM Horizontal Drive Output (internaltransistor emitter) HOUTCOL Horizontal Drive Output (int. trans. open collector) HBLKOUT Horizontal Blanking Output (see activation table) VBLKOUT Vertical Blanking Output (see activation table) VGND Vertical Section Ground VAGCCAP Memory Capacitorfor Automatic Gain Control Loopin Vertical Ramp Generator VREF Vertical Section Reference Voltage(to filter) VCAP Vertical Sawtooth Generator Capacitor VDCOUT Vertical Position ReferenceVoltage Output VOUT Vertical Ramp Output (with frequency independant amplitude and SorC Correctionsif any) VFLY Vertical Flyback Input (positive polarity) EWOUT East/West PincushionCorrection Parabola Output (with Corner correctionsif any) VFOCUS Vertical Dynamic Focus Output VSYNCIN TTL-compatible Vertical Sync Input (for separated H&V) TEST Nottobe used- Testpin VSYNCOUT TTL Vertical Sync Output (ExtractedVSYNCin caseof S/Gor TTL CompositeHV Inputs) HOUT TTL Horizontal Sync Output (To beusedfor frequency measurement) HLOCKOUT First PLL Lock/Unlock Output (5V unlocked-0V locked) H/HVIN TTL-compatible Horizontal Sync Input 5V Supply Voltage (5V Typ.) SCL I2 C-Clock input SDA I2 C-Data input GND Ground (Relatedto 5V)
06A
TDA9106A2/30
QUICK REFERENCE DATA
Parameter Value UnitHorizontal Frequency 15to 150 kHz
Autosynch Frequency (for givenR0 and C0) 1to4.5 FH Horizontal Sync Polarity Input YES
Polarity Detection (on bothHorizontal and Vertical Sections) YES
TTL Composite Synchor Syncon Green YES
Lock/Unlock Identification(on both Horizontal1st PLL and Vertical Section) YES2C Controlfor H-Position ±10 %
XRay Protection YES
Fixed Horizontal Duty Cycle 48 %2C Free Running Adjustment NO F0
Stand-by Function YES
Two Polarities H-Drive Outputs YES
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility YES
Blanking Outputs (both Horizontal and Vertical) YES
Vertical Frequency 35to 200 Hz
Vertical Autosync (for 150nF) 50to 165 Hz
Vertical S-Correction YES
Vertical C-Correction YES
Vertical Amplitude Adjustment YES
Vertical Position Adjustment YES
East/West Parabola Output YES
Pin Cushion Correction Amplitude Adjustment YES
Keystone Adjustment YES
Corner and Corner Balance Adjustments YES
Internal Dynamic Horizontal Phase Control YES
Side Pin Balance Amplitude Adjustment YES
Parallelogram Adjustment YES
Trackingof Geometric Corrections YES
Reference Voltage (bothon Horizontal and Vertical) YES
Dynamic Focus(both Horizontal and Vertical) YES2C Horizontal Dynamic Focus Amplitude Adjustment YES2C Horizontal Dynamic Focus KeystoneAdjustment YES
Typeof Input Sync Detection (suppliedby5V Digital Supply) YES
Horizontal Moiré Output YES2C Controlled H-Moiré Amplitude YES
Frequency Generatorfor Burn-in YES
FastI2C Read/Write 400 kHz
2.T
TDA9106A3/30
REF 1718 36 23 3335
X-RAY
MOIRE
MOIRE
PROCESSOR
BITS
H-FLY
VSYNC
Amp
Keyst
bits
HFOCUSCAP
HFOCUS
GND
HREF
HGND
VFLY
HBLKOUT
VBLKOUT
BLANKING
GENERATOR
VFLY
VSYN
HFLY
LOCK
SYNC
PROCESSOR
SYNC
INPUT
SELECT
bits)
SAFETY
PROCESSOR
LOCK/UNLOCK
IDENTIFICATION
PHASE
COMPARATOR
PHASE
SHIFTER
HOUT
BUFFER
PHASE/FREQUENCY
COMPARATOR
H-PHASE
bits)
VCO
Safe
Freq.
bits
VAMP
bits24 42
RESET
GENERATOR
INTERFACE
REF
VGND
SDA
SCL
GND
REF
AND
CORRECTION
VERTICAL
OSCILLATOR
RAMP
GENERATOR
GEOMETRY
TRACKING
bits
bits
VPOS
bits
bits
bits
Key
Bal
bits
Spin
Bal
bits
TDA9106LL1I
NHIB
LL1F
POSF
ILTE
LOCK
OUT
LOCK
CAP
FLY
LL2C
OUTC
OUTE
CAP
AGCCAP
DCOUT
OUT
VFOC
VSYNCOUT
HOUT
S/G
TEST
VSYNCIN
H/HVIN
EWOUT
CORNER
CORRECTION
bits)
H-SAWTOOTH
GENERATOR
BLOCK DIAGRAM
TDA9106A
4/30
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage (Pin 18) 13.5 V
VDD Supply Voltage (Pin 39) 5.7 V
VIN Max Voltageon Pin6
Pins15, 21,22,23
Pin1
Pin4
Pins3, 33,34,37,38,40,41
Pin16
Pins8,9, 10,11,12, 13,14,25,27,30
VESD ESD susceptibility
Human Body Model,100pF Discharge through 1.5kΩ
EIAJ Norm,200pF Discharge through0Ω
Tstg Storage Temperature -40, +150 oC Junction Temperature +150 oC
Toper Operating Temperature 0, +70 oC
THERMAL DATA
Symbol Parameter Value Unit
Rth(j-a) Junction-ambient Thermal Resistance Max. 65 o C/W
SYNCHRO PROCESSOR
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. Unit
HsVR Horizontal Sync Input Voltage Pin38 0 5 V
MinD Minimum Horizontal Input Pulses Duration Pin38 0.7 μs
Mduty Maximum HorizontalInput Signal Duty Cycle Pin38 25 %
VsVR Vertical Sync Input Voltage Pin33 0 5 V
VSW Minimum Vertical Sync Pulse Width Pin33 5 μs
VSmD Maximum VerticalSync Input Duty Cycle Pin33 15 %
VextM Maximum Ver tical Sync Width on TTL
H/Vcompositeor S/G
Pins1,38 750 μs
Electrical Characteristics(VDD =5V, Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitVSGDC S/G Clamped DC Level Pin1,I1 =-1μA1 V
ISGbias Internal Diode Bias Current Pin1,V1= 1.6V 10 μA
VSGTh Slicing Level (see application design choice) Pin1 0.2 V
VINTH Horizontal and Vertical Input Voltage
(Pins 33,38)
Low Level
High Level 2.2
0.8 V
RIN Horizontal and Vertical Pull-Up Resistor Pins 33,38 200 kΩ
VOut Output Voltage (Pins 35,36,37) Low level
High Level
TfrOut Falling and Rising Output CMOS Buffer Pins 35,36,37
Cout= 20pF
100 ns
VHlock Horizontal1st PLL Lock Output Status (Pin37) Locked
Unlocked
VoutT Extracted Vsync Integration Time(%of TH)on
H/V Composite orS/G
Pin35,C0= 820pF 26 35 %
5.T
TDA9106A5/30
2
C READ/WRITEElectrical Characteristics(VDD =5V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. Unit2C PROCESSOR
Fscl Maximum Clock Frequency Pin40 400 kHz
Tlow Low periodofthe SCL Clock Pin40 1.3 μs
Thigh High periodofthe SCL Clock Pin40 0.6 μs
Vinth SDA andSCL Input Threshold Pins 40,41 2.2 V
VACK Acknowledge Output Voltageon SDA inputwith3mA Pin41 0.4 V
SeealsoI2 CTable ControlandI2C Sub AddressControl
HORIZONTAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. UnitVCO
R0(Min.) Minimum Oscillator Resistor Pin11 6 kΩ
C0(Min.) Minimum Oscillator Capacitor Pin10 390 pF
F(Max.) Maximum Oscillator Frequency 150 kHz
OUTPUT SECTION
I6m Maximum Input Peak Current Pin6 2 mA
HOI1
HOI2
Horizontal Drive Output Maximum Current
Pin20
Pin21
Sourced current
Sunk current
Electrical Characteristics(VCC= 12V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitSUPPLY AND REFERENCE VOLTAGES
VCC Supply Voltage Pin18 10.8 12 13.2 V
VDD Supply Voltage Pin39 4.5 5 5.5 V
ICC Supply Current Pin18 50 mA
IDD Supply Current Pin39 5 mA
VREF-H Horizontal Reference Voltage Pin5,I= 5mA 7.4 8 8.6 V
VREF-V Vertical Reference Voltage Pin5,I= 5mA 7.4 8 8.6 V
IREF-H Max. Sourced Currenton VREF-H Pin5 5 mA
IREF-V Max. Sourced Currenton VREF-V Pin26 5 mA
06A
TDA9106A
6/30
HORIZONTAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit1st PLL SECTION
HpolT Polarity Integration Delay 0.75 ms
VVCO VCO ControlVoltage (Pin12) VREF-H =8V
fH(Max.)
VREF-H/6
Vcog VCO Gain (Pin 12) R0= 6.49kΩ,C0= 820pF,
dF/dV= 1/11R0C0 kHz/V
Hph Horizontal Phase Adjustment %of Horizontal Period ±10 %
Hphmin
Hphtyp
Hphmax
Horizontal Phase Decoupling Output
Minimum Value
Typical Value
Maximum Value
Sub-Address01, Pin14
Byte x1111111
Byte x1000000
Byte x0000000
4.0 FreeRunning Frequency R0= 6.49kΩ,C0= 820pF,= 0.97/8R0C0
22.3 kHz
dF0/dT FreeRunning Frequency Thermal Drift
(No drifton external components)
-150 ppm/C PLL1 Capture Range R0= 6.49kΩ,C0= 820pF,
from f0+0.5kHzto 4.5F0
fH(Min.)
fH(Max.) 100
23.5 kHz
kHz
PLLinh PLL1 Inhibition (Pin3) Typ Threshold= 1.6V
PLL ON
PLL OFF 2
0.8 V
SFF Safe Forced Frequency
SF1 Byte 11xxxxxx
SF2 Byte 10xxxxxx
Sub-Address02
2F0
3F0
FC1
FC2
VCO SawtoothLevel
High FC1=(4.VREF-H)/5
Low FC2=(VREF-H)/5
Pin9To filter
Pin8To filter
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth Flyback Input Threshold Voltage (Pin6) 0.65 0.75 V
Hjit Horizontal Jitter (see Pins8-9 filtering) TBD ppm
Horizontal Drive Output Duty-Cycle
(Pin20or21) (see Note1) %
XRAYth X-RAY Protection Input Threshold Voltage Pin15 8 V
Vphi2 Internal Clamping Levelson 2nd PLL Loop
Filter (Pin4)
Low Level
High Level
VSCinh Threshold Voltage To Stop H-Out,V-Out
when VCC< VSCinh
Pin18 7.5 V
IHblk Maximum Horizontal Blanking Output
Current
I22 10 mA
VHblk Horizontal Blanking Output Low Level
(Blanking ON)
V22 withI22= 10mA 0.25 0.5 V
HDvd
HDem
Horizontal Drive Output
Low Level (Pin20to GND)
High Level (Pin21to VCC=12V)
V21-V20,IOUT= 20mA
V20,IOUT= 20mA 9.5
1.7 V
Notes:1. DutyCycleis theratioof power transistor OFF timeto period. Power transistoris OFF when output transistoris OFF. Initial Conditionfor Safe Operation StartUp (Max. duty cycle).
TDA9106A
7/30
HORIZONTAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. UnitHORIZONTAL DYNAMIC FOCUS SECTION
HDFst Horizontal Dynamic Focus Sawtooth
Minimum Level
Maximum Level
HfocusCap=C0= 820pF,= 90kHz, Pin16 2
HDFdis Horizontal Dynamic Focus Sawtooth
Discharge Width
Drivenby Hfly 500 ns
HDFDC Bottom DC Output Level RLOAD= 10kΩ, Pin17 2 V
TDHDF DC Output VoltageThermal Drift 200 ppm/C
HDFamp Horizontal Dynamic Focus Amplitude
Min Byte xxx11111
Typ Byte xxx10000
Max Byte xxx00000
Sub-Address 03, Pin 17,= 90kHz, Keystone Typ 1
VPP
VPP
VPP
HDFKeyst Horizontal Dynamic Focus Keystone
Min A/B Byte xxx11111
Typ Byte xxx10000
Max A/B Byte xxx00000
Sub-Address04,= 90kHz, Typ Amp
B/A
A/B
A/B
MOIRE OUTPUT
RMOIRE Minimum OutputResistor Pin2 2 kΩ
VMOIRE Output Voltage (moire off),
Subaddress0F
Pin2, RMOIRE =2kΩ
Byte 0xx00000
Byte 0xx10000
Byte 0xx11111
TDA9106A
8/30
VERTICAL SECTION
Operating Conditions
Symbol Parameter Test Conditions Min. Typ. Max. UnitOUTPUTS SECTION
VEWM Maximum EW Output Voltage Pin31 6.5 V
VEWm MinimumEW Output Voltage Pin31 1.8 V
VDFm MinimumVertical Dynamic Focus Output Voltage Pin32 1.8 V
RLOAD MinimumLoadfor less than 1% Vertical Amplitude Drift Pin25 65 MΩ
Electrical Characteristics(VCC= 12V,Tamb =25oC)
Symbol Parameter Test Conditions Min. Typ. Max. UnitVERTICAL RAMP SECTION
VRB Voltageat Ramp BottomPoint VREF-V=8V, Pin27 2 V
VRT Voltageat Ramp Top Point (with Sync) VREF-V Pin27 5 V
VRTF Voltageat Ramp Top Point (withoutSync) Pin27 VRT-
VSTD Vertical Sawtooth Discharge Time Duration
(Pin27)
With 150nF Cap 80 μs
VFRF Vertical Free Running Frequency
(see Notes3&4)
COSC (Pin27)= 150nF
Measuredon Pin27,
100 Hz
ASFR AUTO-SYNC Frequency C27= 150nF ±5%
See Note5 165 Hz
RAFD Ramp Amplitude Drift Versus Frequencyat
Maximum Vertical Amplitude
C27= 150nF
50Hz
200 TBD ppm/Hz
Rlin Ramp Linearityon Pin27 (see Notes3&4) 2.5< V27 andV27< 4.5V 0.5 %
Vpos Vertical Position Adjustment Voltage (Pin28) Sub Address06
Byte x0000000
Byte x1000000
Byte x1111111 3.65
3.3 V
IVPOS Max Currenton Vertical Position Output Pin28 ±2mA
VOR Vertical Output Voltage
(peak-to-peakon Pin 29)
Sub Address05
Byte x0000000
Byte x1000000
Byte x1111111 3.5
2.5 V
VoutDC DC Voltageon Vertical Output See Note6, Pin29 3.5 V
VOI Vertical Output Maximum Current (Pin29) ±5mA
dVS Max Vertical S-Correction Amplitude
x0xxxxxx inhibits S-CORR
x1111111 gives max S-CORR
Subaddress07ΔV/VPPat T/4
ΔV/VPPat 3T/4
Ccorr Vertical C-Corr Amplitude
x0xxxxxx inhibits C-CORR
SubAddress08
Byte x1000000
Byte x1100000
Byte x1111111
VflyTh Vertical Flyback Threshold Pin30 1 V
VflyInh Inhibitionof Vertical Flyback Input See Note7, Pin30 7.5 V
Notes:3. With Register07at Bytex0xxxxxx (VerticalS-Correction Control) thentheS correctionis inhibited, consequentlythe sawtoothhas linearshape. With Register08at Byte x0xxxxxx (VerticalC- Correction Control)thentheC correctionis inhibited, consequentlythe sawtooth
hasa linearshape.It isthe frequency rangefor whichthe VERTICAL OSCILLATORwill automaticallysynchronize, usinga single capacitor valueon
Pin27and with aconstantramp amplitude. VOUTDC= (7/16).VREF-V. Typically 3.5VforVertical reference voltage typical value (8V). WhenPin30( VREF-V) -0.5V,Vfly inputis inhibitedand vertical blankingon verticalblanking outputis replacedby verticalsawtooth
discharge time.
TDA9106A
9/30
VERTICAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
EAST/WEST FUNCTION
EWDC DC Output Voltage with Typ Vpos,Keystone,
Corner and Corner Balance Inhibited
Pin31, see Figure1 2.5 V
TDEWDC DC Output VoltageThermal Drift See Note8 100 ppm/C
EWpara Parabola Amplitude with Vamp Max, V-Pos Typ,
Keystone, Corner and Corner Balance Inhibited
Subaddress09
Byte 1x111111
Byte 1x100000
Byte 1x000000
EWtrack Parabola Amplitude Functionof V-AMP Control
(tracking between V-AMP and E/W) with Typ
Vpos, Keystone, Corner and Corner Balance
Inhibited, EW Typ Amplitude
(see Note9)
Subaddress05
Byte 10000000
Byte 11000000
Byte 11111111
KeyAdj Keystone Adjustment Capability with Typ Vpos,
Corner and Corner Balance Inhibited, EW
Inhibited and Vertical Amplitude Max
(see Note9 and Figure4)
Subaddress0A
Byte 10000000
Byte 11111111
VPP
VPP
KeyTrack Intrinsic Keystone Functionof V-POS Control
(tracking between V-POS and EW) with Corner
and Corner Balance Inhibited,EW Max Amplitude
and VerticalAmplitude Max (see Note9)
A/B Ratio
B/A Ratio
Subaddress06
Byte x0000000
Byte x1111111
Corner
Max
Max CornerCorrectionAmplitude withVamp Max,
V-POS Typ, EWamp, Keystone and Corner
Balance Inhibited (see Note9)
Subaddress0BΔEWoutat T/6, 5T/6
Byte x1111111
Byte x1000000
+0.2
Corner
BalMax
Max Corner Balance Correction Amplitude with
Vamp Max, V-POS Typ, EWamp, Keystone and
Corner Inhibited
Subaddress0C (see Note9)
Byte 01111111
ΔEWoutat T/4
ΔEWoutat 3T/4
+0.2
Byte 01000000
ΔEWoutat T/4
ΔEWoutat 3T/4
+0.2
INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION
SPBpara Side Pin Balance Parabola Amplitude (Figure2)
with Vamp Max, V-POS Typ and Parallelogram
Inhibited (see Notes9& 10)
Subaddress0D
Byte x1111111
Byte x1000000
%TH
%TH
SPBtrack Side Pin Balance Parabola Amplitude functionof
Vamp Control (tracking between Vamp and SPB)
with SPB Max, V-POS Typ and Parallelogram
Inhibited (see Notes9& 10)
Subaddress05
Byte 10000000
Byte 11000000
Byte 11111111
%TH
%TH
%TH
ParAdj Parallelogram Adjustment Capability with Vamp
Max, V-POS Typ and SPB Inhibited
(see Notes9,10& 11)
Subaddress0E
Byte x1111111
Byte x1000000
%TH
%TH
Partrack Intrinsic Parallelogram Functionof Vpos Control
(tracking between V-Pos and DHPC) with Vamp
Max, SPB Max and Parallelogram Inhibited
(see Notes9& 10)
A/B Ratio
B/A Ratio
Subaddress06
Byte x0000000
Byte x1111111
Notes:8. These parametersarenot testedon each unit.Theyare measured duringour internal qualification Refersto Notes3&4 fromlast section.
10.THisthe Horizontal PLL PeriodDuration.
11.Figure2 isrepresenting effectof dynamic horizontalphase control.
9106A
5.T
TDA9106A
10/30
VERTICAL SECTION (continued)
Electrical Characteristics(VCC= 12V,Tamb =25oC) (continued)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VERTICAL DYNAMIC FOCUS FUNCTION
VDFDC DC Output Voltagewith V-Pos Typ See Figure3 6 V
TDVDFDC DC Output VoltageThermal Drift See Note12 100 ppm/C
VDFAMP Parabola Amplitude Functionof Vamp (tracking
between Vamp and VDF)
with V-Pos Typ
(see Figure3) (see Note 13)
Subaddress05
Byte 10000000
Byte 11000000
Byte 11111111
VDFKEY Parabola Assymetry Functionof VPos Control
(tracking between V-Pos and VDF) with Vamp
Max. (see Note13)
Subaddress06
Byte x0000000
Byte x1111111
Notes:12. Parameternot testedon each unitbutmeasured duringourinternal qualificationprocedure including batches coming fromcornersour process and also temperature characterization.
13.SandC correctionsare inhibitedso theoutput sawtooth hasa linear shape.
DHPCDC
SPBPARA
Figure2: Dynamic Horizontal Phase Control
Output
VDFDCVDFAMP
06A
Figure3: Vertical Dynamic Focus Function
EWDC
EWPARA
Figure1: E/W Output
Keyadj
Figure4: Keystone Effecton E/W Output
(PCC Inhibited)
TDA9106A
11/30
TYPICALVERTICAL OUTPUT WAVEFORMS
Function Sub
Address Pin Byte Specification Picture Image
Vertical Size 05 29
Vertical
Position
Control 28
x0000000
x1000000
x1111111
3.2V
3.5V
3.8V
Vertical
Linearity 29
x0xxxxxx
Inhibited
x1111111
Vertical
Linearity 29
x1000000
x1111111
9106A
9106A
7.E
106A
2.25V
3.75V
VPP
VPP =4%
VPP
VPP =3%VPP
VPP =3%
TDA9106A
12/30
GEOMETRY OUTPUT WAVEFORMS
Function Sub
Address Pin Byte Specification Picture Image
Trapezoid
Control 0A 31
EWamp
Typ.
Pin Cushion
Control 09 31
Keystone
Inhibited
1x000000
1x111111
Parrallelogram
Control 0E Internal
SPB
Inhibited
x1000000
x1111111
Side Pin
Balance
Control Internal
Parallelogram
Inhibited
X10000000
x1111111
Vertical
Dynamic
Focus
06A
3.75V
2.75V
2.5V
3.75V
2.75V
2.5V
2.5V
2.5V
1.4%TH3.7V
3.7V 1.4%TH
1.4%TH
3.7V
1.4%TH
3.7V
2.5V
TDA9106A
13/30
Function Sub
Address Pin Byte Specification Picture Image
Corner Control 0B 31
EWamp
Typ.
x1111111
Corner Balance
Control 0C 31
EWamp
Typ.
Note: The specificationof output voltageis indicatedon 3.75VPP vertical sawtooth output condition.The output voltagedependson vertical
sawtooth output voltage.
06A
106A
GEOMETRY OUTPUT WAVEFORMS (continued)
without
Corner
Corner
effect
Corner
effect
Corner
effect
Corner
effect
TDA9106A
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2C BUSADDRESS TABLESubAddress Definition
Slave Address (8C): Write Mode D7 D6 D5 D4 D3 D2 D1 x x x x 0 0 0 0 Horizontal Drive Selection x x x x 0 0 0 1 Horizontal Position x x x x 0 0 1 0 Safety Frequency x x x x 0 0 1 1 Synchro Priority/ Horizontal Focus Amplitude x x x x 0 1 0 0 Refresh/ Horizontal Focus Keystone x x x x 0 1 0 1 Vertical Ramp Amplitude x x x x 0 1 1 0 Vertical Position Adjustment x x x x 0 1 1 1 S Correction x x x x 1 0 0 0 C Correction x x x x 1 0 0 1 E/W Amplitude x x x x 1 0 1 0 E/W Keystone x x x x 1 0 1 1 Cbow Corner x x x x 1 1 0 0 Spin Corner x x x x 1 1 0 1 Side Pin Balance x x x x 1 1 1 0 Parallelogram x x x x 1 1 1 1 Moire Control Amplitude
Slave Address (8D): ReadMode D7 D6 D5 D4 D3 D2 D1 x x x x 0 0 0 0 Synchro and Polarity Detection
TDA9106A
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