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TMS320C6474FZUNATIN/a55avai Multicore Digital Signal Processor


TMS320C6474FZUNA , Multicore Digital Signal Processor SPRS552H–OCTOBER 2008–REVISED APRIL 20111.2 DescriptionThe TMS320C64x+ DSPs (including the TMS320C ..
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TMS320C6474FZUNA
Multicore Digital Signal Processor
TMS320C6474
www.ti.com
SPRS552H–OCTOBER 2008–REVISED APRIL 2011
TMS320C6474 Multicore Digital Signal Processor Features
1.2-GHz Device: -40°Cto 95°C(1)• Key Features 1-GHz Device: -40°Cto 100°C High-Performance Multicore DSP (C6474)3 TMS320C64x+™ DSP Cores Instruction Cycle Time: 0.83 ns (1.2-GHz
Device);1 ns (1-GHz Device); 1.18 ns
Dedicated SPLOOP Instructions
(850-MHz Device)
Compact Instructions (16-Bit) Clock Rate:1 GHzto 1.2 GHz (1.2-GHz Exception HandlingDevice);1 GHz (1-GHz Device); 850 MHz TMS320C64x+ Megamodule L1 Memory(850-MHz Device) Architecture Commercial Temperature and Extended 256 K-Bit (32 K-Byte) L1P Program CacheTemperature [Direct Mapped]3 TMS320C64x+™ DSP Cores; Six RSAs for 256 K-Bit (32 K-Byte) L1D Data CacheCDMA Processing(2 per core) [2-Way Set-Associative] Enhanced VCP2/TCP2 512 K-Bit (64 K-Byte) L3 ROM Frame Synchronization Interface Enhanced VCP2 16-/32-Bit DDR2-667 Memory Controller Supports Over 694 7.95-Kbps AMR EDMA3 Controller Enhanced Turbo Decoder Coprocessor (TCP2) Antenna Interface Supports upto Eight 2-Mbps3 GPP Two 1x Serial RapidIO® Links, v1.2 (6 Iterations)Compliant Endianness: Little Endian, Big Endian One 1.8-V Inter-Integrated Circuit (I2C) Bus Frame Synchronization Interface Two 1.8-V McBSPs Time Alignment Between Internal 1000 Mbps Ethernet MAC (EMAC) Subsystems, External Devices/System Six 64-Bit General-Purpose Timers OBSAI RP1 Compliant for Frame Burst Data 16 General-Purpose I/O (GPIO) Pins Alternate Interfaces for non-RP1 and Internal Semaphore Module non-UMTS Systems System PLL and PLL Controller/DDR PLL 16-/32-Bit DDR2-667 Memory Controller
and PLL Controller, Dedicatedto DDR2
EDMA3 Controller (64 Independent Channels)Memory Controller Antenna Interface High-Performance Multicore DSP (C6474)6 Configurable Links (Full Duplex) Time: Supports OBSAI RP3 Protocol, v1.0: 0.83-ns 768-Mbps, 1.536-, 3.072-Gbps Link Rates 1-ns Supports CPRI Protocol V2.0: 614.4-Mbps, 1.18 ns 1.2288-, 2.4576-Gbps Link Ratesor Shared with CPU Two1x Serial v1.2 Compliant 1.25-, Rates Message Passing DirectIO Eight 32-Bit Error Management Extensions Congestion Control One 1.8-V Inter-Integrated 0°Cto 100°C Two 1.8-V McBSPs
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