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TS4975STN/a560avaiStereo Headphone Drive Amplifier with I2C Bus Digital Volume Control
TS4975EIJTSTN/a5000avaiStereo Headphone Drive Amplifier with I2C Bus Digital Volume Control


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TS4975-TS4975EIJT
Stereo Headphone Drive Amplifier with I2C Bus Digital Volume Control
Operating from VCC = 2.5V to 5.5V I²C bus control interface 43mW output power @ Vcc=3.3V, THD=1%, F=1kHz, with 16Ω load Ultra low consumption in stdby mode: 0.8 Digital volume control range from 18dB to -
34dB
14 steps digital volume control 9 different output mode selections Pop & click noise reduction circuitry Flip-chip package 12 x 300µm bumps Lead-free flip-chip package
Description

The TS4975 is a stereo audio headphone driver
capable of delivering up to 110mW per channel of
continuous average power into a 16Ω single-
ended loads with 1% THD+N from a 5V power
supply. This device utilizes the I²C bus to control
its functionality, which minimizes the number of
external components needed.
The overall gain of these headphone drivers is
controlled digitally by the volume control registers
which are programmed via the I²C interface. It has
also an internal thermal shutdown protection
mechanism.
Pin Connections (top view)
Applications
Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices
Order Codes

Stereo Headphone Drive Amplifier with
I2C Bus Digital Volume Control
PRODUCT PREVIEW
TS4975
TS4975 Absolute Maximum Ratings
1 Absolute Maximum Ratings
Table1: Key parameters and their absolute maximum ratings
Table2: Operating Conditions
Table3: Electrical characteristic for I²C
All voltages values are measured with respect to the ground pin. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V Device is protected in case of over temperature by a thermal shutdown active @ 150°C. Exceeding the power derating curves during a long period, may involve abnormal operating condition. Human body model, 100pF discharged through a 1.5kOhm resistor, into pin to Vcc device.
Application Diagram TS4975 Application Diagram
Figure 1: Typical application schematics
TS4975 Application Information
3 Application Information
I²C Operation description

The TS4975 uses a serial bus, which conforms to the I²C protocol, to control the chip’s functions with two
wires: Clock and Data. The Clock line is uni-directional. The Data line is bi-directional (open-collector)
with an outside chip pullup resistor (typically 10 kOhm). The maximum clock frequency specified by the
I²C standard is 400kHz.:
The slave address of the TS4975 is CC or CE hex. The host MCU can write into the TS4975 control
registers. These registers can only be written via the I²C bus; the Reading function is undefined.
In order to write data into the TS4975, after the "start" message, the MCU must send the following data: the I²C address slave byte with a low level for the R/W bit the byte to the internal register address where the MCU wants to write data the data
Figure 2: I²C write operation

All bytes are sent with MSB bit first. The transfer of written data is ended with a "stop" message. When
transmitting several data, the register addresses and data can be written with no need to repeat the start
and slave addresses
Table4: I²C Bus Interface - Pin descriptions
Table5: Device Slave Address
Application Information TS4975
Table6: Ouput mode selection: G from -34 dB to + 18dB (by step of 4dB)

(SD = Shutdown Mode, In1 = Audio Input 1, In2= Audio Input2, G = Gain from Audio Input 1and Input 2 to
Output1 and Output2)
Gain Register Operation

The gain of the TS4975 ranges from -34dB to +18 dB. At Power-up, both the right and left channels are
set in Stand-by mode.
Table7: Gain Settings Truth Table
TS4975 Application Information
Table8: Output mode settings truth table
Table9: Stand-by mode I²C condition
Table 10: I²C control byte states
Acknowledge

The number of data bytes transferred between the start and the stop conditions from the CPU master to
the TS4975 slave is not limited. Each byte of eight bits is followed by one acknowledge bit.
The TS4975 which is addressed, generates an acknowledge after the reception of each byte that has
been clocked out.
Electrical Characteristics TS4975 Electrical Characteristics
Table 11: VCC = +2.5 V, GND = 0V, Tamb = 25°C (unless otherwise specified)
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ F = 217Hz
TS4975 Electrical Characteristics
Table 12:VCC = +3.3V, GND = 0V, T amb = 25°C (unless otherwise specified)
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ F = 217Hz
Electrical Characteristics TS4975
Table 13:VCC = +5V, GND = 0V, T amb = 25°C (unless otherwise specified)
Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to Vcc @ F = 217Hz
TS4975 Electrical Characteristics
Figure 3: THD+N versus Output power
Figure 4: THD+N versus Output power
Figure 5: THD+N versus Output power
Figure 6: THD+N versus Output power
Figure 7: THD+N versus Output power
Figure 8: THD+N versus Output power
Electrical Characteristics TS4975
Figure 9: THD+N versus Output power
Figure 10: THD+N versus Output power
Figure 11: THD+N versus Output power
Figure 12: THD+N versus Output power
Figure 13: THD+N versus Output power
Figure 14: THD+N versus Output power
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