TSA1002CFT ,10-BIT, 50MSPS, 50MW A/D CONVERTERBLOCK DIAGRAM VREFP+2.5VGNDAVINReferencestage stageINCM stageIPOLcircuit 1 2 nVINBVR ..
TSA1201IF ,12-BIT, 50MSPS, 150MW A/D CONVERTERNCD11 (MSB)DRORVCCBEVCCBEGNDBEGNDBEVCCBIGNDBINC DGNDSRCNC OEBDGNDDFSBCLKAVCCDGNDAVCCD ..
TSA1203IF ,DUAL-CHANNEL, 12-BIT, 40MSPS A/D CONVERTERD1GNDBID0(LSB)DVCCVCCBEDGNDGNDBESELECTVCCBICLKVCCBIDGNDOEBDVCCAVCC AVCCAVCCAGNDINCMIINCMQREFMIREFMQ ..
TSA1203IF ,DUAL-CHANNEL, 12-BIT, 40MSPS A/D CONVERTERAPPLICATIONS Q channelVINBQ■ Medical imaging and ultrasoundGND GNDBE■ 3G basestation■ I/Q signal pr ..
TSA1203IFT ,DUAL-CHANNEL, 12-BIT, 40MSPS A/D CONVERTERBLOCK DIAGRAM on a pipeline structure and digital error correction+2.5V/3.3V CLK SELECT OEB VC ..
TSA1203IFT ,DUAL-CHANNEL, 12-BIT, 40MSPS A/D CONVERTERapplications■ High speed data acquisition systemPACKAGE ■ Portable instrumentationORDER CODE ..
UAF1780 ,DUAL 2A LOW DROP OUT INTELLIGENT POWER SWITCHCO SGS-THOMSON
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UAF1780-1781-1782
DUAL 2 A LOW DROP OUT INTELLIGENT P ..
UAF41 , DIODE-PENTODE
UAF42AP ,Universal Active Filter.PIN CONFIGURATIONSP PACKAGEU PACKAGEPDIP-14SOIC-16(TOP VIEW)(TOP VIEW)Low-Pass V 1 14 Frequency Ad ..
UAF42AP ,Universal Active FilterMAXIMUM RATINGSOver operating free-air temperature range unless otherwise noted.UAF42 UNITPower Sup ..
UAF42AP ,Universal Active Filter SBFS002B –JULY 1992–REVISED OCTOBER 2010
UAF42AP+ ,Universal Active FilterMAXIMUM RATINGSOver operating free-air temperature range unless otherwise noted.UAF42 UNITPower Sup ..
TSA1002CFT
10-BIT, 50MSPS, 50MW A/D CONVERTER
10-bit A/D converter in deep submicron CMOS technology � Single supply voltage: 2.5V� Input range: 2Vpp differential� 50Msps sampling frequency� Ultra low power consumption: 50mW @
50Msps� ENOB=9.6 @ 40Msps, Fin=24MHz� SFDR typically up to 72dB @ 50Msps,
Fin=5MHz� Built-in reference voltage with external bias
capability� Pinout compatibility with TSA0801, TSA1001
and TSA1201
DESCRIPTIONThe TSA1002 is a 10-bit, 50Msps sampling
frequency Analog to Digital converter using a
CMOS technology combining high performances
and very low power consumption.
The TSA1002 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and guarantee 9.6 effective bits at
Fs=40Msps, and Fin=24MHz.
A voltage reference is integrated in the circuit to
simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with an external reference.
Especially designed for high speed, low power
applications, the TSA1002 only dissipates 50mW
at 50Msps. A tri-state capability, available on the
output buffers, enables to address several slave
ADCs by a unique master.
The output data can be coded into two different
formats. A Data Ready signal is raised as the data
is valid on the output and can be used for
synchronization purposes.
The TSA1002 is available in commercial (0 to
+70°C) and extended (-40 to +85°C) temperature
range, in a small 48 pins TQFP package.
APPLICATIONS Medical imaging and ultrasound� Portable instrumentation� Cable Modem Receivers� High resolution fax and scanners� High speed DSP interface
ORDER CODE
PIN CONNECTIONS (top view)
PACKAGE
TSA100210-BIT, 50MSPS, 50mW A/D CONVERTER
TSA1002
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS 1)Condition VRefP-VRefM>0.3V
BLOCK DIAGRAM All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages
must never exceed -0.3V or VCC+0V Corporate ST Microelectronics procedure number 0018695
TSA1002
PIN CONNECTIONS (top view)
PIN DESCRIPTION
TSA1002
ELECTRICAL CHARACTERISTICSAVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
TIMING DIAGRAM
TSA1002
CONDITIONSAVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
REFERENCE VOLTAGE See parameters definition for more information Not fully tested over the temperature range. Guaranteed by sampling.
TSA1002
CONDITIONSAVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
POWER CONSUMPTION
DIGITAL INPUTS AND OUTPUTS
ACCURACY Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF Not fully tested over the temperature range. Guaranteed by sampling.
TSA1002
CONDITIONSAVCC = DVCC = 2.5V, Fs= 40Msps Vin@ -1.0dBFS, VREFP=1V, VREFM= 0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS Rpol= 18KΩ. Equivalent load: Rload= 470Ω and Cload= 6pF Tmin= -40°C to Tmax= 85°C. Not fully tested over the temperature range. Guaranteed by sampling.
TSA1002
DEFINITIONS OF SPECIFIED PARAMETERS
STATIC PARAMETERSStatic measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 40Msps, which is high enough to fully
characterize the test frequency response. The
input level is +1dBFS to saturate the signal.
Differential Non Linearity (DNL)The average deviation of any output code width
from the ideal code width of 1 LSB.
Integral Non linearity (INL)An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERSDynamic measurements are performed by
spectral analysis, applied to an input sine wave of
various frequencies and sampled at 40Msps.
The input level is -1dBFS to measure the linear
behavior of the converter. All the parameters are
given without correction for the full scale ampli-
tude performance except the calculated ENOB
parameter.
Spurious Free Dynamic Range (SFDR)The ratio between the power of the worst spurious
signal (not always an harmonic) and the amplitude
of fundamental tone (signal power) over the full
Nyquist band. It is expressed in dBc.
Total Harmonic Distortion (THD)The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.
Signal to Noise Ratio (SNR)The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Signal to Noise and Distortion Ratio (SINAD)Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS)
SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/
FS)
The ENOB is expressed in bits.
Analog Input BandwidthThe maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delayDelay between the initial sample of the analog
input and the availability of the corresponding
digital data output, on the output bus. Also called
data latency. It is expressed as a number of clock
cycles.
TSA1002
Static parameter: Integral Non LinearityFs=50MSPS; Fin=1MHz; Icc=20mA; N=131072pts
Static parameter: Differential Non Linearity Fs=50MSPS; Fin=1MHz; Icc=20mA;N=131072pts
Linearity vs. FsFin=5MHz; Rpol adjustment
Distortion vs. FsFin=5MHz; Rpol adjustment
TSA1002
Linearity vs. FsFin=15MHz; Rpol adjustment
Linearity vs. FinFs=50MSPS; Icca=20mA
Linearity vs.TemperatureFs=50MSPS; Icca=20mA; Fin=5MHz
Distortion vs. FsFin=15MHz; Rpol adjustment
Distortion vs. FinFs=50MSPS; Icca=20mA
Distortion vs. TemperatureFs=50MSPS; Icca=20mA; Fin=5MHz;
