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TSA1204IFT
DUAL CHANNEL, 12-BIT, 20MSPS, 120MW, A/D CONVERTER
0.5Msps to 20Msps sampling frequency� Adaptative power consumption: 120mW @ 20Msps, 95mW@10Msps� Single supply voltage: 2.5VIndependant supply for CMOS output stage with 2.5V/3.3V capability� ENOB=11.2 @ Nyquist� SFDR= -81.5 dBc @ Nyquist� 1GHz analog bandwidth Track-and-Hold� Common clocking between channels� Dual simultaneous Sample and Hold inputs� Multiplexed outputs� Built-in reference voltage with external bias
capability.
DESCRIPTIONThe TSA1204 is a new generation of high speed,dual-channel Analog to Digital converter pro-
cessed in a mainstream 0.25μm CMOS technolo-
gy yielding high performances and very low powerconsumption.
The TSA1204 is specifically designed for applica-
tions requiring very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction
to provide excellent static linearity and over 11.2
effective bits at Fs=20Msps, and Fin=10MHz.
For each channel, a voltage reference is integrat-
ed to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins.
Differential or single-ended analog inputs can be
applied. A tri-state capability is available for the
outputs, allowing chip selection.
The TSA1204 is available in extended (-40 to
+85°C) temperature range, in a small 48 pins
TQFP package.
APPLICATIONS Medical imaging and ultrasound�
3G basestation�
I/Q signal processing applications�
High speed data acquisition system�
Portable instrumentation
ORDER CODE
PIN CONNECTIONS (top view)
BLOCK DIAGRAM
PACKAGE IPOL
CLK+2.5V/3.3V
VINI
VINBI
OEB
VINCMI
GND
VINQ
VINBQ
VINCMQ
SELECT
VREFPI
VREFPQ
VREFMI
VREFMQ
D11
VCCBE
GNDBE
TSA1204DUAL-CHANNEL, 12-BIT, 20MSPS, 120mW A/D CONVERTER
TSA1204
CONDITIONSAVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=10.5MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS
TIMING CHARACTERISTICS
TSA1204
TIMING DIAGRAM
PIN CONNECTIONS (top view) N+1N+2
N+5
N+3
N+4
CLKTpd I + Tod
N+9
N+12
N+13
DATA
OUTPUT
sample N+1
I channel
sample N
Q channel
sample N+1
Q channel
sample N+2
I channel
sample N+2
Q channel
sample N+3
I channel
OEBSimultaneous sampling
on I/Q channels
SELECT
sample N-9
I channel
sample N-8
I channel
sample N-7
Q channel
sample N-6
Q channelCLOCK AND SELECT CONNECTED TOGETHER
TSA1204
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC
2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ
3). Discharge to Ground of a device that has been previously charged.
4). Corporate ST Microelectronics procedure number 0018695
TSA1204
OPERATING CONDITIONS
1) Condition VRefP-VRefM>0.3V
ANALOG INPUTS
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
DIGITAL INPUTS AND OUTPUTS
TSA1204
REFERENCE VOLTAGE
POWER CONSUMPTION
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
ACCURACY
MATCHING BETWEEN CHANNELS
TSA1204
DEFINITIONS OF SPECIFIED PARAMETERS
STATIC PARAMETERS
Static measurements are performed through
method of histograms on a 2MHz input signal,
sampled at 20Msps, which is high enough to fully
characterize the test frequency response. The
input level is +1dBFS to saturate the signal.
Differential Non Linearity (DNL)
The average deviation of any output code width
from the ideal code width of 1 LSB.
Integral Non linearity (INL)
An ideal converter presents a transfer function as
being the straight line from the starting code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
DYNAMIC PARAMETERS
Dynamic measurements are performed by
spectral analysis, applied to an input sine wave of
various frequencies and sampled at 20Msps.
The input level is -1dBFS to measure the linear
behavior of the converter. All the parameters are
given without correction for the full scale ampli-
tude performance except the calculated ENOB
parameter.
Spurious Free Dynamic Range (SFDR)
The ratio between the power of the worst spurious
signal (not always an harmonic) and the amplitude
of fundamental tone (signal power) over the full
Nyquist band. It is expressed in dBc.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first five harmonic
distortion components to the rms value of the
fundamental line. It is expressed in dB.
Signal to Noise Ratio (SNR)
The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (fs /2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Signal to Noise and Distortion Ratio (SINAD)
Similar ratio as for SNR but including the harmonic
distortion components in the noise figure (not DC
signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When the applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD2Ao=SINADFull Scale+ 20 log (2A0/FS)
SINAD2Ao=6.02 × ENOB + 1.76 dB + 20 log (2A0/
FS)
The ENOB is expressed in bits.
Analog Input Bandwidth
The maximum analog input frequency at which the
spectral response of a full power signal is reduced
by 3dB. Higher values can be achieved with
smaller input levels.
Effective Resolution Bandwidth (ERB)
The band of input signal frequencies that the ADC
is intended to convert without loosing linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delay
Delay between the initial sample of the analog
input and the availability of the corresponding
digital data output, on the output bus. Also called
data latency. It is expressed as a number of clock
cycles.
TSA1204
Static parameter: Integral Non Linearity
Fs=20MSPS; Icca=40mA; Fin=2MHz
Static parameter: Differential Non Linearity
Fs=20MSPS; Icca=40mA; Fin=2MHz
Linearity vs. Fs
Fin=5MHz; Rpol adjustment
Distortion vs. Fs
Fin=5MHz; Rpol adjustment
TSA1204
Linearity vs. Fin
Fs=20MSPS; Icca=40mA
Linearity vs. Temperature
Fs=20MSPS; Icca=40mA; Fin=2MHz
Linearity vs. AVCC
Fs=20MSPS; Icca=40mA; Fin=5MHz
Distortion vs. Fin
Fs=20MSPS; Icca=40mA
Distortion vs. Temperature
Fs=20MSPS; Icca=40mA; Fin=2MHz
Distortion vs. AVCC
Fs=20MSPS; Icca=40mA; Fin=5MHz
TSA1204
Linearity vs. DVCC
Fs=20MSPS; Icca=40mA; Fin=5MHz
Linearity vs. VCCBI
Fs=20MSPS; Icca=40mA; Fin=5MHz
Linearity vs. VCCBE
Fs=20MSPS; Icca=40mA; Fin=5MHz
Distortion vs. DVCC
Fs=20MSPS; Icca=40mA; Fin=5MHz
Distortion vs. VCCBI
Fs=20MSPS; Icca=40mA; Fin=5MHz
Distortion vs. VCCBE
Fs=20MSPS; Icca=40mA; Fin=5MHz
TSA1204
Linearity vs. Duty Cycle
Fs=20MSPS; Icca=40mA; Fin=5MHz
Distortion vs. Duty Cycle
Fs=20MSPS; Icca=40mA; Fin=5MHz
Single-tone 8K FFT at 20Msps - I Channel
Fin=5MHz; Icca=40mA, Vin@-1dBFS
Dual-tone 8K FFT at 20Msps - I Channel
Fin1=9.7MHz; Fin2=10.7MHz; Icca=40mA, Vin1@-7dBFS; Vin2@-7dBFS; IMD=-76dBc
