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UBA2028TNXPN/a500avai600 V dimmable power IC for compact fluorescent lamps


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UBA2028T
600 V dimmable power IC for compact fluorescent lamps
1. General description
The UBA2028 is a high voltage power IC that drives and controls electronically ballasted
Compact Fluorescent Lamps (CFLs). The IC includes a Metal-Oxide-Semiconductor
Transistor (MOST) half-bridge power circuit, a dimming function, a high voltage level shift
circuit, an oscillator function, a lamp voltage monitor, a current control function, a timer
function and various protections.
2. Features and benefits
Two internal 600 V, 3 Ω max MOST half-bridge power circuits For steady state currents up to 280 mA For ignition currents up to 1.5A Adjustable preheat time Adjustable preheat current Current controlled operating Single ignition attempt Adaptive non-overlap time control Integrated high voltage level shift function Power-down function Protection against lamp failures or lamp removal Capacitive mode protection
3. Applications
5 W to 25 W dimmable CFLs, provided that the maximum junction temperature is not
exceeded.
UBA2028
600 V dimmable power IC for compact fluorescent lamps
Rev. 02 — 19 July 2010 Product data sheet
NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps
4. Quick reference data
Table 1. Quick reference data
VDD =13V; VFS− VSH =13V; Tamb =25 °C; all voltages are referenced to GND; unless otherwise
specified.
Start-up state

VDD(startup) start-up supply voltage for oscillator 12.4 13.0 13.6 V
VDD(stop) stop supply voltage for oscillator 8.6 9.1 9.6 V
IDD(startup) start-up supply current for oscillator;
VDD -170 200 μA
High voltage supply

Vhs high-side supply
voltage
IHV <30 μA; t<1s --600 V
Reference voltage

Vref reference voltage Ileak =10μA 2.86 2.95 3.04 V
Voltage controlled oscillator

fmax maximum frequency for bridge; CCF = 100pF 90 100 110 kHz
fmin minimum frequency for bridge; CCF = 100pF 38.9 40.5 42.1 kHz
Half-bridge power transistors

Ron on-state resistance half-bridge power - - 3 Ω drain current pulsed; tp limited by Tj(max);
T--1.5 A
Preheat current sensor

Vph preheat voltage 0.57 0.60 0.63 V
Lamp voltage sensor

Vlamp(fail) lamp fail voltage 0.77 0.81 0.85 V
Vlamp(max) maximum lamp
voltage
1.44 1.49 1.54 V
Average current sensor

Voffset offset voltage Vi(CSP) =Vi(CSN)=
0Vto 2.5V −20 +2 mV transconductance f=1 kHz 1900 3800 5700 μA/mV
Preheat timer

tph preheat time CCT= 330 nF;
RIREF =33kΩ
1.6 1.8 2.0 s
VOL LOW-level output
voltage
-1.4 -V
VOH HIGH-level output
voltage
-3.6 -V
NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps
5. Ordering information
Table 2. Ordering information
UBA2028T SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
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NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps
diagram

NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps
7. Pinning information
7.1 Pinning

7.2 Pin description

Table 3. Pin description
1 high voltage input 2 floating supply voltage; supply for high-side switch 3 floating supply voltage; supply for high-side switch
GND 4 ground
ACM 5 capacitive mode input
LVS 6 lamp voltage sensor input
VREF 7 reference voltage output
CSP 8 positive input for the average current sensor
CSN 9 negative input for the average current sensor 10 preheat timer output
CSW 11 input of voltage controlled oscillator 12 voltage controlled oscillator output
IREF 13 internal reference current input
GND 14 ground
GLO 15 gate output for the low-side switch, must be wired to pin 18
VDD 16 low voltage supply
PCS 17 preheat current sensor input
GLI 18 gate input for the low-side switch, must be wired to pin 15. 19 source for the high-side switch 20 source low-side switch, connected to PGND via a resistor;
see Figure7
NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps
8. Functional description
8.1 Start-up state

Initial start-up can be achieved by charging the low voltage supply capacitor at pin 16 (see
Figure 8 and Figure 9) via an external start-up resistor. Start-up of the circuit is achieved
under the condition that both half-bridge transistors TR1 and TR2 are non-conductive.
The circuit will be reset in the start-up state. If the low voltage supply (VDD) reaches the
value of VDD(startup) the circuit will start oscillating. A DC reset circuit is incorporated in the
High-Side (HS) driver. Below the lockout voltage at the FS pin the output voltage (TR1
gate voltage− VSH) is zero. The voltages at pins CF and CT are zero during the start-up
state.
8.2 Oscillation

The internal oscillator is a Voltage Controlled Oscillator (VCO) circuit which generates a
sawtooth waveform between the Vo(osc)max level and 0 V. The frequency of the sawtooth is
determined by capacitor CCF, resistor RIREF, and the voltage at pin CSW. The minimum
and maximum switching frequencies are determined by RIREF and CCF; their ratio is
internally fixed. The sawtooth frequency is twice the half-bridge frequency. The UBA2028
brings the transistors TR1 and TR2 into conduction alternately with a duty cycle of
approximately 50 %. An overview of the oscillator signal and driver signals is illustrated in
Figure 7. The oscillator starts oscillating at fmax. During the first switching cycle the
Low-Side (LS) transistor (TR2) is switched on. The first conducting time is made extra
long to enable the bootstrap capacitor to charge.
8.3 Adaptive non-overlap

The non-overlap time is realized with an adaptive non-overlap timing circuit (ANT). By
using an adaptive non-overlap circuit, the application can determine the duration of the
non-overlap time and make it optimum for each frequency; see Figure 7. The non-overlap
time is determined by the slope of the half-bridge voltage, and is detected by the signal
across resistor R15 see Figure 8 (R6 in Figure 9) which is connected directly to pin ACM.
The minimum non-overlap time is internally fixed. The maximum non-overlap time is
internally fixed at approximately 25 % of the bridge period time. An internal filter of 30 ns
is included at the ACM pin to increase the noise immunity.
8.4 Timing circuit

A timing circuit is included to determine the preheat time and the ignition time. The circuit
consists of a clock generator and a counter.
The preheat time is defined by CCT and RIREF connected to pins 10 and 13, and consists
of 7 pulses at CCT; the maximum ignition time is 1 pulse at CCT. The timing circuit starts
operating after the start-up state, as soon as the low supply voltage (VDD) has reached
VDD(startup) or when a critical value of the lamp voltage (Vlamp(fail)) is exceeded. When the
timer is not operating CCT is discharged to 0 V at 1 mA.
NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps
8.5 Preheat state

After starting at fmax, the frequency decreases until the momentary value of the voltage
across sense resistor R21 (see Figure 8) or R5 (Figure 9) reaches the internally fixed
preheat voltage level (pin PCS). Detection of the preheat voltage occurs during the end of
the ‘on-time’ of the low-side switch TR2 when the internal preheat fixed voltage reference
level is exceeded. Once detection has occurred the output current of the Preheat Current
Sensor (PCS) circuit discharges the capacitor CCSW, thus raising the frequency. The
internal preheat control is reset during each “on-time’ of the high-side switch TR1, thus
CCSW is charged, and the frequency decreases. It remains in this condition when no
detection occurs. The preheat time begins at the moment that the circuit starts oscillating.
During the preheat time the Average Current Sensor (ACS) circuit is disabled. An internal
filter of 30 ns is included at pin PCS to increase the noise immunity.
8.6 Ignition state

After the preheat time the ignition state is entered and the frequency will sweep down due
to charging of the capacitor at pin CSW with an internally fixed current; see Figure4.
During this continuous decrease in frequency, the circuit approaches the resonant
frequency of the load. This will cause a high voltage across the load, which normally
ignites the lamp. The ignition voltage of a lamp is designed above the Vlamp(fail) level. If the
lamp voltage exceeds the Vlamp(fail) level the ignition timer is started.
8.7 Burn state

If the lamp voltage does not exceed the Vlamp(max) level the voltage at pin CSW will
continue to increase until the clamp level at pin CSW is reached; see Figure 4. As a
consequence the frequency will decrease until the minimum frequency is reached.
When the frequency reaches its minimum level it is assumed that the lamp has ignited
and the circuit will enter the burn state. The Average Current Sensor (ACS) circuit will be
enabled. As soon as the averaged voltage across sense resistor R21 (see Figure 8) or R5
(Figure 9), measured at pin CSN, reaches the reference level at pin CSP , the average
current sensor circuit will take over the control of the lamp current. The average current
through R21 or R5, is transferred to a voltage at the voltage controlled oscillator and
regulates the frequency and, as a result, the lamp current.
8.8 Lamp failure mode
8.8.1 During ignition state

If the lamp does not ignite, the voltage level increases. When the lamp voltage exceeds
the Vlamp(max) level, the voltage will be regulated at the Vlamp(max) level; see Figure5.
When the Vlamp(fail) level is crossed the ignition timer has already started. If the voltage at
pin LVS is above the Vlamp(fail) level at the end of the ignition time the circuit stops
oscillating and is forced into the Power-down mode. The circuit will be reset only when the
supply voltage is powered down.
8.8.2 During burn state

If the lamp fails during normal operation, the voltage across the lamp will increase and the
lamp voltage will exceed the Vlamp(fail) level; see Figure 6. At that moment the ignition
timer is started. If the lamp voltage increases further it will reach the Vlamp(max) level. This
forces the circuit to re-enter the ignition state and results in an attempt to reignite the
NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps

lamp. If during restart the lamp still fails, the voltage remains high until the end of the
ignition time. At the end of the ignition time the circuit stops oscillating and the circuit will
enter the Power-down mode.
8.9 Power-down mode

The Power-down mode will be entered if, at the end of the ignition time, the voltage at pin
LVS is above Vlamp(fail). In the Power-down mode the oscillator will be stopped and both
TR1 and TR2 will be non-conductive. The VDD supply is internally clamped. The circuit is
released from the Power-down mode by lowering the low voltage supply below VDD(rst).
8.10 Capacitive mode protection

The signal across R15 see Figure 8 (R6 in Figure 9) also gives information about the
switching behavior of the half-bridge. If, after the preheat state, the voltage across the
ACM resistor (R15 or R6) does not exceed the Vdet(capm) level during the non-overlap
time, the Capacitive Mode Detection circuit (CMD) assumes that the circuit is in the
capacitive mode of operation. As a consequence the frequency will directly be increased
to fmax. The frequency behavior is de coupled from the voltage at pin CSW until CCSW has
been discharged to zero.
8.11 Charge coupling

Due to parasitic capacitive coupling to the high voltage circuitry all pins are burdened with
a repetitive charge injection. Given the typical application the pins IREF and CF are
sensitive to this charge injection. For charge coupling of approximately 8 pC, a safe
functional operation of the IC is guaranteed, independent of the current level.
Charge coupling at current levels below 50 μA will not interfere with the accuracy of the
VCS, Vi(PCS) and Vi(ACM) levels.
Charge coupling at current levels below 20 μA will not interfere with the accuracy of any
parameter.
8.12 Design equations

The following design equations are used to calculate the desired preheat time, the
maximum ignition time, and the minimum and the maximum switching frequency.
(1)
(2)
(3)
(4)
Start of ignition is defined as the moment at which the measured lamp voltage crosses the
Vlamp(fail) level; see Section 8.8.ph 1.8 CCT
330 109–×-------------------------- RIREF 103×--------------------××=ign 0.26 CCT
330 109–×-------------------------- R IREF 103×--------------------××=min 40.5 103× 100 1012–×CF---------------------------- 33 103× IREF---------- ----------××=max 2.5fmin×=
NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps

NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps

8.13 Layout considerations

The connection of PGND and GND is shown in Figure7
NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps

NXP Semiconductors UBA2028
600 V dimmable power IC for compact fluorescent lamps
9. Limiting values

[1] In accordance with the human body model, i.e. equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
[2] In accordance with the machine model, i.e. equivalent to discharging a 200 pF capacitor through a 0.75 μH coil and a 10 Ω resistor.
10. Thermal characteristics

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to GND.
VHV voltage on pin HV operating; during 1s - 600 V
operating - 510 V drain current TR1 pulsed; tp limited by Tj(max);
T-1.5 A
TR2 pulsed; tp limited by Tj(max);
T-1.5 A
VVDD voltage on pin VDD -14 V
VFS voltage on pin FS with respect to SH 0 14 V
Vi(ACM) input voltage on pin ACM −5+5 V
Vi(PCS) input voltage on pin PCS −5+5 V
Vi(LVS) input voltage on pin LVS 0 5 V
Vi(CSP) input voltage on pin CSP 0 5 V
Vi(CSN) input voltage on pin CSN −0.3 +5 V
Vi(CSW) input voltage on pin CSW 0 5 V slew rate pin SH; repetitive −4+4 V/ns
Tamb ambient temperature −25 +80 °C junction temperature −25 +150 °C
Tstg storage temperature −55 +150 °C
VESD electrostatic discharge voltage pin HV [1]- 1500 V
pins FS, SH [1]- 1000 V
pin GLO [1]- < 500 V
pin GLO [2] -150 V
Table 5. Thermal characteristics

Rth(j-a) thermal resistance from junction to ambient SO20; in free air 75 K/W
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