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USBN9604-28M |USBN960428MNSCN/a4avaiUniversal Serial Bus Full Speed Node Controller with Enhanced DMA Support
USBN9604-28MX |USBN960428MXNSN/a1000avaiUniversal Serial Bus Full Speed Node Controller with Enhanced DMA Support
USBN9604SLBNSN/a17000avaiUniversal Serial Bus Full Speed Node Controller with Enhanced DMA Support
USBN9604SLBXNSN/a49183avaiUniversal Serial Bus Full Speed Node Controller with Enhanced DMA Support


USBN9604SLBX ,Universal Serial Bus Full Speed Node Controller with Enhanced DMA SupportTable of Contents1.0 Signal/Pin Connection and Description1.1 CONNECTION DIAGRAMS .....61.2 DETAILE ..
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USBN9604-28M-USBN9604-28MX-USBN9604SLB-USBN9604SLBX
Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support
May 1998USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support
June 2003
Revision 1.3
USBN9603/USBN9604 Universal Serial Bus
Full Speed Node Controller with Enhanced DMA Support
General Description

The USBN9603/4 are integrated, USB Node controllers.
Other than the reset mechanismforthe clock generation cir-
cuit, these two devices are identical.All referencesto “the
device”in this document referto both devices, unless other-
wise noted.
The device provides enhanced DMA support with many au-
tomatic data handling features.Itis compatible with USB
specification versions 1.0 and 1.1, andisan advanced ver-
sion of the USBN9602.
The device integrates the required USB transceiver witha
3.3V regulator,a Serial Interface Engine (SIE), USB end-
point (EP) FIFOs,a versatile 8-bit parallel interface,a clock
generator anda MICROWIRE/PLUS™ interface. Seven
endpoint pipes are supported: onefor the mandatory con-
trol endpoint andsixto support interrupt, bulk and isochro-
nous endpoints. Each endpoint pipe hasa dedicated FIFO, bytesfor the control endpoint and64 bytesfor the other
endpoints. The 8-bit parallel interface supports multiplexed
and non-multiplexed style CPU address/data buses.A pro-
grammable interrupt output scheme allows device configu-
ration for different interrupt signaling requirements.
Outstanding Features
Low EMI, low standby current,24 MHz oscillator Advanced DMA mechanism Fully static HALT mode with asynchronous wake-up
for bus powered operation 5Vor 3.3V operation Improved input range 3.3V signal voltage regulator All unidirectional FIFOs are64 bytes Power-up reset and startup delay counter simplify sys-
tem design Simple programming model controlledby external controller Availablein two packages USBN9603/4SLB: small footprintfor new designs
and portable applications USBN9603/4-28M: standard package, pin-to-pin
compatible with USBN9602-28M
Block Diagram

Physical Layer Interface (PHY)
Media Access Controller (MAC)
Transceiver
24 MHz
Oscillator
Clock
Generator
XIN
XOUT
CLKOUT
Microcontroller Interface
INTR
V3.3
A0/ALE D7-0/AD7-0
Endpoint/Control FIFOs
VReg AGND
RESET
VCC
GND
MODE1-0
Serial Interface Engine (SIE)
USB EventDetect
Clock
Recovery RD WR
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