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USBUF01W6STMN/a10000avaiEMI FILTER AND LINE TERMINATION FOR USB UPSTREAM PORTS


USBUF01W6 ,EMI FILTER AND LINE TERMINATION FOR USB UPSTREAM PORTSUSBUFxxW6®EMI FILTER AND LINE TERMINATIONA.S.D.™FOR USB UPSTREAM PORTS
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USBUF01W6
EMI FILTER AND LINE TERMINATION FOR USB UPSTREAM PORTS
1/9
USBUFxxW6

EMI FILTER AND LINE TERMINATION
FOR USB UPSTREAM PORTS
March 2002- Ed:3A
A.S.D.
FUNCTIONAL DIAGRAM

TM: ASDand TRANSIL areatrademarksof STMicroelectronics.
EMI Filter and line termination for USB upstream
ports on: USB Hubs PC peripherals
APPLICATIONS
Monolithic device with recommended line termi-
nationfor USB upstream ports IntegratedRt series termination andCt bypass-
ing capacitors. Integrated ESD protection Small package size
FEATURES

The USB specification requires upstream ports be terminated with pull-up resistors from the and D- lines to Vbus. On the
implementationof USB systems, the radiated
and conducted EMI should be kept within the
required levels as stated by the FCC
regulations.In additionto the requirementsof
termination and EMC compatibility, the
computing devices are requiredtobe tested for
ESD susceptibility.
The USBUFxxW6 provides the recommended line
termination while implementinga low pass filterto
limit EMI levels and providing ESD protection
which exceeds IEC61000-4-2 level4 standard.
The deviceis packagedina SOT323-6L whichis
the smallest available lead frame package (50%
smaller than the standard SOT23).
DESCRIPTION
EMI/ RFI noise suppression Required line termination for USB upstream
ports ESD protection exceedingIEC61000-4-2 level4 High flexibilityin the designof high density
boards Tailoredto meet USB 1.1 standard
BENEFITS
USBUFxxW6
IEC61000-4-2, level4
±15 kV (air discharge)kV (contact discharge)
MIL STD 883E, Method 3015-7
Class3 C= 100pF R= 1500Ω positive strikes and3 negative strikes (F=1Hz)
COMPLIES WITH THE FOLLOWING ESD
STANDARDS:
ABSOLUTE RATINGS (Tamb = 25°C)
TECHNICAL INFORMATION
Fig. A1:
USB Standard requirements
USBUFxxW6
Fig. A2:
Implementation of ST' solutions for USB ports
APPLICATION EXAMPLE
USBUFxxW6
Current FCC regulations requires that classB computing devices meet specified maximum levelsfor both
radiated and conducted EMI. Radiated EMI covers the frequency range from 30MHzto 1GHz. Conducted EMI covers the 450kHzto 30MHz range.
For the typesof devices utilizing the USB, the most difficult testto passis usually the radiated EMI test. For
this reason the USBUFxxW6 deviceis aimingto minimize radiated EMI.
The differential signal (D+ and D-)of the USB does not contribute significantlyto radiatedor conducted
EMI because the magnetic fieldof both conductors cancels each other.
The insideof the PC environmentis very noisy and designers must minimize noise coupling from the
different sources. D+ andD- must notbe routed near high speed lines (clocks spikes).
Induced common mode noise canbe minimizedby running pairsof USB signals parallelto each other and
running grounded guardtraceon each sideof the signal pair from the USB controllerto the USBUF device. possible, locate the USBUF device physically near the USB connectors. Distance between the USB con-
troller and the USB connector mustbe minimized.
The 47pF (Ct) capacitors are usedto bypass high frequency energyto ground andfor edge control, and
are placed between the driver chip and the series termination resistors (Rt). BothCt andRt should be
placedas closeto the driver chipasis practicable.
The USBUFxxW6 ensuresa filtering protection against ElectroMagnetic and RadioFrequency Interferences
thankstoits low-pass filter structure. This filteris characterizedby the following parameters: cut-off frequency Insertion loss high frequency rejection.
EMI FILTERING
Fig. A3:
USBUFxxW6 typical attenuation curve.
Fig. A4:
Measurement configuration additionto the requirementsof termination and EMC compatibility, computing devices are requiredtobe
testedfor ESD susceptibility. This testis describedin the IEC 61000-4-2 andis alreadyin placein Europe.
This test requires thata device tolerates ESD events and remains operational without user intervention.
The USBUFxxW6is particularly optimizedto perform ESD protection. ESD protectionis basedon the use device which clampsat: RIcl BR dPP=+ .
This protection functionis splittedin2 stages. As shownin figure A5, the ESD strikes are clampedby the
first stage S1 and thenits remaining overvoltageis appliedto the second stage through the resistor Rt.
Sucha configuration makes the output voltage very lowat the output.
ESD PROTECTION
USBUFxxW6
Fig. A5:
USBUFxxW6 ESD clamping behavior
Fig. A6:
Measurement board havea good approximationof the remaining voltagesat both Vin and Vout stages, we give the typical
dynamical resistance value Rd. By taking into account these following hypothesis: Rt>Rd, Rg>Rd and
Rload>Rd,it gives these formulas:
Vinput RV RV
gBR dg= + ..
Voutput RV R Vinput
tBR d= + ..
The resultsof the calculation done for Vg=8kV, Rg=330Ω (IEC61000-4-2 standard), VBR=7V (typ.)
and Rd= 1Ω (typ.) give:
Vinput= 31.2V
Voutput= 7.95V
This confirms the very low remaining voltage across the devicetobe protected.Itis also importantto note
thatin this approximation the parasitic inductance effect was not taken into account. This could be few
tenthsof volts during fewnsat the Vinput side. This parasitic effectis not presentat the Voutput side due
the low current involved after the resistance Rt.
The measurements done hereafter show very clearly (Fig. A7) the high efficiencyof the ESD protection:no influenceof the parasitic inductanceson Voutput stage Voutput clamping voltage very closeto VBR (breakdown voltage)in the positive way
and -VF (forward voltage)in the negative way
USBUFxxW6
Fig. A7:
Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge.
Please note that the USBUFxxW6is not only actingfor positive ESD surges but alsofor negative ones. For
these kindsof disturbancesit clamps closeto ground voltageas shownin Fig. A7b.
The early ageing and destructionof IC’sis often dueto latch-up phenomenon whichis mainly inducedby
dV/dt. Thankstoits structure, the USBUFxxW6 providesa high immunityto latch-up phenomenon by
smoothing very fast edges.
LATCH-UP PHENOMENA
CROSSTALK BEHAVIOR
Fig. A8:
Crosstalk phenomenon
The crosstalk phenomenonis dueto the coupling between2 lines. The coupling factor( β12or β21)in-
creases when the gap across lines decreases, particularlyin silicon dice.In the example above the ex-
pected signalon load RL2is α2VG2,in fact the real voltageat this point has gotan extra value β21VG1. This
partof the VG1 signal represents the effectof the crosstalk phenomenonof the line1 on the line2. This
phenomenon hastobe taken into account when the drivers impose fast digital dataor high frequency ana-
log signalsin the disturbing line. The perturbed line willbe more affectedifit works with low voltage signal high load impedance (few kΩ).
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