HEF4557BT ,1-to-64 bit variable length shift registerINTEGRATED CIRCUITSDATA SHEETFor a complete data sheet, please also download:• The IC04 LOCMOS HE40 ..
HEF4557BT ,1-to-64 bit variable length shift registerFeatures and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized ..
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HEF4557BT
1-to-64 bit variable length shift register
1. General descriptionThe HEF4557B is a static clocked serial shift register whose length may be programmed
to be any number of bits between 1 and 64. The number of bits selected is equal to the
sum of the subscripts of the enabled length control inputs (L1, L2, L4, L8, L16, and L32)
plus one. Serial data may be selected from the DA or DB data inputs with the A/B select
input. This feature is useful for recirculation purposes. Information on DA or DB is shifted
into the first register position and all the data in the register is shifted one position to the
right on the LOW to HIGH transition of CP0 while CP1 is LOW or on the HIGH to LOW
transition of CP1 while CP0 is HIGH. A HIGH on master reset (MR) resets the register and
forces Q to LOW and Q to HIGH, independent of the other inputs.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Ordering information
HEF4557B
1-to-64 bit variable length shift register
Rev. 6 — 18 November 2011 Product data sheet
Table 1. Ordering informationAll types operate from 40 C to +85C
HEF4557BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4557BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
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NXP Semiconductors HEF4557B
1-to-64 bit variable length shift register
4. Functional diagram
NXP Semiconductors HEF4557B
1-to-64 bit variable length shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 2. Pin description tableL1, L2, L4, L8, L16, L32 2, 1, 15, 14, 13, 12 bit-length control input 3 asynchronous master reset
CP0 4 clock input
CP1 5 clock input
DA, DB 7, 6 data input
VSS 8 ground (0 V)
A/B 9 select data input
NXP Semiconductors HEF4557B
1-to-64 bit variable length shift register
6. Functional description[1] The moment Dn appears at Q depends on the bit-length shown in Table 4; H = HIGH voltage level; L = LOW voltage level; = don’t care; = positive-going transition; = negative-going transition; D1,D2 = either HIGH or LOW. 10 buffered output 11 complementary buffered output
VDD 16 supply voltage
Table 2. Pin description table …continued
Table 3. Function table[1] D1 D2 LD2 D1 D2 LD1 D1 D2 H D2 D1 D2 H D1 XXX XX L
Table 4. Bit-length select function table LLLL1-bit LLLH 2-bits LLH L3-bits LLH H 4-bits LH LL5-bits LH LH 6-bits L L H H L 7-bits L L HHH8-bits
L1 to L16 continue to increment in a binary count with L32 LOW H HHHH32-bits L LLLL33-bits L LLLH 34-bits
L1 to L16 continue to increment in a binary count with L32 HIGH HHL L 61-bits HHL H62-bits HHHL 63-bits HHHH64-bits
NXP Semiconductors HEF4557B
1-to-64 bit variable length shift register
7. Limiting values[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO< 0.5 V or VO >VDD + 0.5V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW power dissipation per output - 100 mW
Table 6. Recommended operating conditionsVDD supply voltage 3 - 15 V input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
NXP Semiconductors HEF4557B
1-to-64 bit variable length shift register
9. Static characteristicsTable 7. Static characteristicsVSS = 0 V; VI = VSS or VDD unless otherwise specified.
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 -3.5 -3.5 - V
10 V 7.0 -7.0 -7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA input leakage current 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0A 5 V - 50 - 50 - 375 A
10 V - 100 - 100 - 750 A
15 V - 200 - 200 - 1500 A input capacitance - - - - 7.5 - - pF
NXP Semiconductors HEF4557B
1-to-64 bit variable length shift register
10. Dynamic characteristicsTable 8. Dynamic characteristicsVSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
tPHL HIGH to LOW
propagation delay
CP0, CP1 to Q, Q;
see Figure4
5 V [1] 213 ns + (0.55 ns/pF)CL - 240 480 ns
10 V 79 ns + (0.23 ns/pF)CL - 90 180 ns
15 V 57 ns + (0.16 ns/pF)CL - 65 130 ns to Q; see Figure4 5 V 143 ns + (0.55 ns/pF)CL - 170 340 ns
10 V 69 ns + (0.23 ns/pF)CL - 80 160 ns
15 V 52 ns + (0.16 ns/pF)CL - 60 120 ns
tPLH LOW to HIGH
propagation delay
CP0, CP1 to Q, Q;
see Figure4
5 V [1] 213 ns + (0.55 ns/pF)CL - 240 480 ns
10 V 79 ns + (0.23 ns/pF)CL - 90 180 ns
15 V 57 ns + (0.16 ns/pF)CL - 65 130 ns to Q; see Figure4 5 V 113 ns + (0.55 ns/pF)CL - 140 280 ns
10 V 59 ns + (0.23 ns/pF)CL - 70 140 ns
15 V 47 ns + (0.16 ns/pF)CL - 55 110 ns transition time see Figure4 5 V [1] 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL - 3060ns
15 V 6 ns + (0.28 ns/pF)CL - 2040ns
tsu set-up time DA, DB, A/B to CP0,
CP1; L1to L32= LOW;
see Figure5
5 V [2] 360 180 - ns
10 V 140 70 - ns
15 V 9045- ns
DA, DB, A/B to CP0,
CP1; L32= HIGH;
see Figure5
5 V +40 20 - ns
10 V +35 10 - ns
15 V +30 5- ns hold time DA, DB, A/B to CP0,
CP1; L1to L32= LOW;
see Figure5
5 V [2] 40 110 - ns
10 V 10 45 - ns
15 V 0 30 - ns
DA, DB, A/B to CP0,
CP1; to L32= HIGH;
see Figure5
5 V 9030- ns
10 V 6020- ns
15 V 5015- ns pulse width CP0 input LOW;
minimum width;
see Figure5
5 V 180 90 - ns
10 V 6030- ns
15 V 4020- ns
CP1 input HIGH;
minimum width;
see Figure5
5 V 180 90 - ns
10 V 6030- ns
15 V 4020- ns
MR input HIGH;
minimum width;
see Figure5
5 V 150 75 - ns
10 V 7035- ns
15 V 5025- ns
NXP Semiconductors HEF4557B
1-to-64 bit variable length shift register[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] The set-up, hold, and recovery times vary with the minimum number of bits selected. For intermediate numbers not specified, interpolate
as shown in Table9.
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
trec recovery time MR input; to L32= LOW;
see Figure5
5 V [2] 500 250 - ns
10 V 250 125 - ns
15 V 150 75 - ns
MR input;
L32= HIGH
5 V 110 50 - ns
10 V 7030- ns
15 V 6025- ns
fmax maximum
frequency
see Figure5 5 V 2.5 5 - MHz
10 V 7 14 - MHz
15 V 1020- MHz
Table 8. Dynamic characteristics …continuedVSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
Table 9. Interpolation table [1]LLLLLL1 see Table8 500 ns LLLLL2 (interpolate in 6
equal steps)
435 ns H LLLL3 370 ns X H LLL5 305 ns
XXXH L L 9 240 ns
XXXXH L 17 175 ns
XXXXXH 33 see Table8 110 ns
Table 10. Dynamic power dissipation PDPD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. dynamic power
dissipation
5 V PD = 3500 fi + (fo CL) VDD2 fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
10 V PD = 15000 fi + (fo CL) VDD2
15 V PD = 37000 fi + (fo CL) VDD2
